Design and Draw the Layout of an RS Flip-Flop Using Two NAND Gates

Design and draw the layout of an RS flip-flop using two NAND gates

Sam Tran

CENG 5931.02 Introduction to Microelectronics

Instructor: Hatem N. Nounu

August 2, 2004 Project Outline

I. Define the target.

1. What is a RS flip-flop using NAND gates?

2. Requirements of the design.

a. Layout rules. b. Minimization.

II. How to make it.

1. Figure out whole picture.

2. Minimize.

3. Design.

a. NAND gate. b. RS Flip-Flop.

III. Conclusion.

IV. References. Define the target

The target of this project is to use L-edit to design an RS flip-flop using two

NAND gates. So, what is a RS flip-flop and what are the requirements of the design on

L-edit.

What is a RS flip-flop using NAND gates.

A flip-flop is a basic memory cell. It is capable to store one bit of information.

Usually, a flip-flop has two outputs, one for normal value and one for the complement value for the bit stored. Normally, a flip-flop maintains the binary state until a coming pulse switches the state. Here is a RS (reset/set) flip-flop constructed by two NAND gates (Figure 1):

Figure 1: RS flip-flop using 2 NAND gates.

S R Q /Q 1 0 0 1 1 1 0 1 (after S=1, R=0) 0 1 1 0 1 1 1 0 (after S=0, R=1) 0 0 1 1 (Not allowed)

Figure 2: The truth table of the flip-flop. As on the truth table (Figure 2), the flip-flop is in set state (Q=1, /Q = 0) when the reset input (R) is 1. In the case of the set input (S) is 1, the flip-flop is in reset state (Q=0,

/Q=1). If both inputs are set to 0, the two outputs are 1. This condition should be avoided in normal operation of a flip-flop.

Requirements of the design

To work with L-edit, we have to follows rules of the software. Actually, these rules come from practice. For example, the minimum size for a Metal is 3, distance between the Metal1 is at least 3, a contact size is 2x2, and etc. Every technique of integration has a specific set of rules. Or, users can define their own rules. Here is an example (Figure 3):

Figure 3: Rules of the MOSIS/AMI N20 2P2M NPN Another important thing on the design is minimization. Minimization is a process in which every part of the layout gets the minimum value from the set of rules. It ensures that the chip is the smallest. No rooms or materials are wasted.

In summary, there are two things that we have to care about: the rules of the design and the minimization. In the next section, we will consider how to solve these problems.

How to make it

As the natural way to solve a problem, the designer has to figure out the whole picture of the problem. In this case, we consider how many objects that we have, what is the minimum size of each according to the rules.

Figure out the whole picture

As we can see from Figure 1, the flip-flop consists of two NAND gates. Each

NAND gate is formed by 2 N-MOS and 2 P-MOS as in the Figure 4:

Figure 4: Structure of an NAND gate All in all, the flip-flop contains 4 N-MOS, 4 P-MOS, two inputs, two outputs, a voltage supplier (VDD), and a ground (GND).

Minimize

After recording all objects of the flip-flop, we categorize them into two groups: basic objects and containing objects. The basic object is the object that cannot contain any object, like contact, via. The containing object is the object that contains one or more other objects. Because the basic object has the size fixed (for example, the contact size is

2x2), so we can calculate the minimum size of the containing object. The below (Figure

5) demonstrates how to calculate the minimum size of N select from the basic objects

(the contacts):

26 

Figure 5: A minimized N-well The contact size is 2x2, the minimum distance from the contact to the border is

2. So, the minimum size of the Metal1 with contact is 6. Continue with this way, we get the minimum length of the N select is 26. Actually, we can shrink 1  because the minimum distance between Metal 1 is 3. However, it looks clearer with the design as above.

Design

Follow the method said above, here are the results.

NAND gate (Figure 6):

Figure 6: a minimized NAND gate. RS flip-flop (Figure 7):

Figure 7: Minimized layout and cross-section of the RS flip-flop. Conclusion

The design consists of three steps: figure out all objects of the chip, categorize objects into groups, and then minimize based on the objects and the rules. References

 Innovatia Laboratories. RS Flip-Flop. Retrieve July 29, 2004 from Innovatia Laboratories website: http://www.innovatia.com/Design_Center/RS_Flip- Flops.htm.

 Peter W. Wagacha. ICS 217 Digital Electronic lecture. Retrieve July 28, 2004 from University of Nairobi at: http://www.uonbi.ac.ke/acad_depts/ics/course_material/Digital_electronic s/ICS217Part0.ppt.

 Tanner Corporation. MAMIS035DL Digital Low Power Standard Cell Library for Mosic AMI 0.5 micro Sub-micron Process. Retrieve July 15, 2004 from Tanner Company at: www.tanner.com/ces.