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ADS54J40 Dual-Channel, 14-Bit, 1.0-GSPS Analog-To-Digital Converter

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ADS54J40 Dual-Channel, 14-Bit, 1.0-GSPS Analog-To-Digital Converter Product Order Technical Tools & Support & Folder Now Documents Software Community ADS54J40 SBAS714B –MAY 2015–REVISED JANUARY 2017 ADS54J40 Dual-Channel, 14-Bit, 1.0-GSPS Analog-to-Digital Converter 1 Features 3 Description The ADS54J40 is a low-power, wide-bandwidth, 14- 1• 14-Bit Resolution, Dual-Chanel, 1-GSPS ADC bit, 1.0-GSPS, dual-channel, analog-to-digital • Noise Floor: –158 dBFS/Hz converter (ADC). Designed for high signal-to-noise • Spectral Performance (fIN = 170 MHz at –1 dBFS): ratio (SNR), the device delivers a noise floor of – SNR: 69.0 dBFS –158 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. – NSD: –155.9 dBFS/Hz The device supports the JESD204B serial interface – SFDR: 86 dBc with data rates up to 10.0 Gbps, supporting two or – SFDR: 89 dBc (Except HD2, HD3, and four lanes per ADC. The buffered analog input Interleaving Tones) provides uniform input impedance across a wide frequency range and minimizes sample-and-hold • Spectral Performance (f = 350 MHz at –1 dBFS): IN glitch energy. Each ADC channel optionally can be – SNR: 66.3 dBFS connected to a wideband digital down-converter – NSD: –153.3 dBFS/Hz (DDC) block. The ADS54J40 provides excellent – SFDR: 75 dBc spurious-free dynamic range (SFDR) over a large input frequency range with very low power – SFDR: 85 dBc (Except HD2, HD3, and consumption. Interleaving Tones) The JESD204B interface reduces the number of • Channel Isolation: 100 dBc at fIN = 170 MHz interface lines, allowing high system integration • Input Full-Scale: 1.9 VPP density. An internal phase-locked loop (PLL) • Input Bandwidth (3 dB): 1.2 GHz multiplies the ADC sampling clock to derive the bit • On-Chip Dither clock that is used to serialize the 14-bit data from each channel. • Integrated Wideband DDC Block • JESD204B Interface with Subclass 1 Support: Device Information – 2 Lanes per ADC at 10.0 Gbps PART NUMBER PACKAGE BODY SIZE (NOM) – 4 Lanes per ADC at 5.0 Gbps ADS54J40 VQFNP (72) 10.00 mm × 10.00 mm – Support for Multi-Chip Synchronization (1) For all available packages, see the orderable addendum at the end of the data sheet. • Power Dissipation: 1.35 W/ch at 1 GSPS • Package: 72-Pin VQFNP (10 mm × 10 mm) 2 Applications FFT for 170-MHz Input Signal • Radar and Antenna Arrays 0 • Broadband Wireless -20 • Cable CMTS, DOCSIS 3.1 Receivers • Communications Test Equipment -40 • Microwave Receivers -60 • Software Defined Radio (SDR) -80 • Digitizers (dBFS) Amplitude • Medical Imaging and Diagnostics -100 -120 0 100 200 300 400 500 Input Frequency (MHz) D003 SNR = 69 dBFS; SFDR = 86 dBc; fIN = 170 MHz, IL spur = 84 dBc; non HD2, HD3 spur = 89 dBc 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS54J40 SBAS714B –MAY 2015–REVISED JANUARY 2017 www.ti.com Table of Contents 1 Features .................................................................. 1 8.3 Feature Description................................................. 24 2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 32 3 Description ............................................................. 1 8.5 Register Maps......................................................... 43 4 Revision History..................................................... 2 9 Application and Implementation ........................ 68 5 Device Comparison Table..................................... 3 9.1 Application Information............................................ 68 9.2 Typical Application .................................................. 73 6 Pin Configuration and Functions ......................... 4 10 Power Supply Recommendations ..................... 75 7 Specifications......................................................... 6 10.1 Power Sequencing and Initialization ..................... 76 7.1 Absolute Maximum Ratings ...................................... 6 7.2 ESD Ratings.............................................................. 6 11 Layout................................................................... 77 7.3 Recommended Operating Conditions....................... 6 11.1 Layout Guidelines ................................................. 77 7.4 Thermal Information.................................................. 7 11.2 Layout Example .................................................... 78 7.5 Electrical Characteristics........................................... 7 12 Device and Documentation Support ................. 79 7.6 AC Characteristics .................................................... 8 12.1 Documentation Support ........................................ 79 7.7 Digital Characteristics ............................................. 11 12.2 Receiving Notification of Documentation Updates 79 7.8 Timing Characteristics............................................. 12 12.3 Community Resources.......................................... 79 7.9 Typical Characteristics............................................ 14 12.4 Trademarks ........................................................... 79 8 Detailed Description ............................................ 23 12.5 Electrostatic Discharge Caution............................ 79 8.1 Overview ................................................................. 23 12.6 Glossary ................................................................ 79 8.2 Functional Block Diagram ....................................... 23 13 Mechanical, Packaging, and Orderable Information ........................................................... 79 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (October 2015) to Revision B Page • Added Device Comparison Table........................................................................................................................................... 4 • Added CDM row to ESD Ratings table................................................................................................................................... 6 • Changed the minimum value for the input clock frequency in the Recommended Operating Conditions table ................... 6 • Changed Sample Timing, Aperture jitter parameter typical specification in Timing Characteristics section........................ 12 • Added the FOVR latency parameter to the Timing Characteristics table............................................................................. 12 • Changed Overview section .................................................................................................................................................. 23 • Changed Functional Block Diagram section: changed Control and SPI block and added dashed outline to FOVR traces 23 • Changed SYSREF Signal section: changed Table 4 and added last paragraph................................................................. 28 • Added SYSREF Not Present (Subclass 0, 2) section .......................................................................................................... 29 • Changed the number of clock cycles in the Fast OVR section ............................................................................................ 30 • Deleted Lane Enable with Decimation subsection .............................................................................................................. 39 • Added the Program Summary of DDC Modes and JESD Link Configuration table............................................................. 41 • Added Figure 80 to Register Maps section .......................................................................................................................... 43 • Changed the Register Map................................................................................................................................................... 44 • Deleted register 39h, 3Ah, and 56h ..................................................................................................................................... 44 • Added Table 53 .................................................................................................................................................................... 61 • Changed Power Supply Recommendations section ........................................................................................................... 75 • Added the Power Sequencing and Initialization section....................................................................................................... 76 • Added the Receiving Notification of Documentation Updates section ................................................................................. 79 Changes from Original (May 2015) to Revision A Page • Released to production .......................................................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714B –MAY 2015–REVISED JANUARY 2017 5 Device Comparison Table PART NUMBER SPEED GRADE (MSPS) RESOLUTION (Bits) CHANNEL ADS54J20 1000 12 2 ADS54J42 625 14 2 ADS54J40 1000 14 2 ADS54J60 1000 16 2 ADS54J66 500 14 4 ADS54J69 500 16 2 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation
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