2011

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 15, Number 4 WINTER The Heat Is On 2012 Revolutionary and Evolutionary Innovations in Thermal Management page 17

ALLVIA, Inc. – providing Silicon Interposer and TSV foundry services to Semiconductor, Optoelectronics and MEMS industries. page 18

INSIDE THIS ISSUE

Packaging and Test Many Factors Both Silicon 3D Players Markets Face Some Driving Chips Interposers and Need to Figure Substantial Headwinds Up Into the 3D Memory Out Their Spot as We Come to the Vertical Space Stacking Avail- in the Supply End of 2011 able From IBM Chain 14 20 22 SPRING 201130 MEPTEC Report 3

BOARD LETTER

MEPTEC – Network to Innovate

Nikhil Kelkar, Sr. Director of Package Development and Assembly Engineering Intersil Corporation MEPTEC Advisory Board Member

Numerous op-eds in the last smart energy, medical, etc. For example, With fewer hands-on training opportuni- few years have discussed the transforma- it is interesting to note that future package ties on-shore, MEPTEC is an excellent tion of the Package and Assembly industry requirements for the lighting industry may resource for gaining practical insights and more generally about the transforma- be similar to those of deep down drilling and tapping into experts for development tion of the overall semiconductor industry but with life expectancy of automotive and problem solving. in the United States. With the advent of the electronics! Therefore, MEPTEC’s busi- mepteC has survived and thrived outsourced manufacturing model, not only ness model continues to be flexible to during the last three plus decades due to has manufacturing moved offshore but attract and include engineers from paral- its business model of providing a plat- so has process and equipment engineer- lel and adjunct industries because today’s form for networking and in doing so has, ing. However, innovation is still present package and test engineers are going to probably inadvertently, contributed to in the US – which we all strive to support solve tomorrows lighting and MEMS innovation in semiconductor package and for future success of semiconductor and problems. Second, continue to build a test industry. A revamped advisory board related industries. vertical network within the semiconduc- with “new blood” working alongside mepteC provides an unparalleled tor industry. Boundaries between wafer industry veterans will make MEPTEC platform for semiconductor package and fabrication and IC packaging as well as even stronger in its quest to bring inno- test engineers to build their network with between IC packaging and systems are vative package and test technologies to their peers, customers, and suppliers of more blurred than ever. For example, the forefront for years to come. ◆ materials, equipment and assembly/test wafer level 2D/3D packaging is drawing services. To quote Prof. Andrew Hargadon, suppliers of wafer, assembly, MEMS and Nikhil Kelkar is Sr. Director of “Innovation is about connecting and not solar packaging technologies to innovate Package Development and Assembly inventing. No idea will make a difference new methods and designs for competi- Engineering at Intersil Corporation, without building around it the networks tive package solutions. Last but not least, a global technology leader special- that will support it as it grows, and net- MEPTEC provides a forum for package izing in the design and manufacturing work partners with which it will ultimately and test engineers to discuss capabilities of high performance analog semi- flourish.” Therefore, earlier in 2011 when and requirements with customers – many conductors. Prior to joining Intersil I was approached to be a member of the of those have significantly grown their in 2005, Nikhil held a succession of MEPTEC advisory board, I immediately respective packaging groups and are play- engineering and management posi- thought of it as an excellent opportunity to ing a direct role in package technology tions at National Semiconductor and be an integral part of the network (going development. pioneered micro SMD wafer level beyond never missing Jim Walker’s Sep- i cannot close this article without packaging technology. He holds a B.E. tember Industry Forecast Luncheon!). mentioning the acquisition of National in Mechanical Engineering from Govt. to provide a network that will support Semiconductor by Texas Instruments. I College of Engineering Pune (India) and grow with innovative ideas, MEPTEC am probably one of the last generations and a Masters in Mechanical Engi- continues to focus in the following three of new college grads who attended the neering from University of Maryland specific areas: First, promote building a ‘National Semiconductor University’ and at College Park. He is a member of network of packaging and test engineers benefited from its access to abundant theo- IEEE and holds over 40 US patents. across parallel industries such as lighting, retical knowledge and practical training. FOUR NEW MEPTEC SYMPOSIUM CDs NOW AVAILABLE ONLINE.

In Association With A SPECIAL ONE-DAY TECHNICAL SYMPOSIUM MEPTEC&SMTAPRESENT A SPECIAL ONE-DAY TECHNICAL SYMPOSIUM A SPECIAL ONE-DAY TECHNICAL SYMPOSIUM Microelectronics Packaging & Test Engineering Council Surface Mount Technology Association A SPECIAL TWO-DAY TECHNICAL SYMPOSIUM KNOWN MEMS - 2011 2.5D, 3D KGD PLUS 20% OFF DRIVING INNOVATION Medical Electronics and Beyond GOOD Symposium / Day One Bringing 3D Integration MEMS, THERMAL, Existing Technologies Enable 2011 DIE Future Innovations Vital Technologies for Health to the Packaging Mainstream In an Era of Multi-Die Packaging and 3D Integration AND MEDICAL SAN JOSE • CALIFORNIA ASU CAMPUS • TEMPE • ARIZONA SANTA CLARA • CALIFORNIA SANTA CLARA • CALIFORNIA Presented by 5.19.11 9. 2 7.11 Presented by 11.9.11 Presented by 11.10.11 CD PACKAGES. ORDER ONLINE AND DOWNLOAD TODAY AT MEPTEC.ORG meptec.org WINTER 2011 MEPTEC REPORT 3 2011 The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council P. O. Box 222, Medicine Park, OK 73557 Tel: (650) 714-1570 Email: [email protected] WINTER A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 15, Number 4 Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown 2011 On The Cover Sales Manager Gina Edwards A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 15, Number 4 WINTER

The Heat Is On THE HEAT IS ON 2012 – “Revolutionary and Evolutionary Innova- MEPTEC Advisory Board 2012 Board Members Revolutionary and Evolutionary Innovations 17 tions in Thermal Management”. MEPTEC is pleased to announce in Thermal Management page 17 the continuation of our “Heat is On” Thermal Management Symposiums, Ivor Barber LSI Corporation which for the second year will be co-located with the 28th Annual Joel Camarda SemiOps ALLVIA, Inc. – providing Silicon Interposer and TSV foundry services to Semiconductor, Optoelectronics Jerry Dellheim ASM Pacific and MEMS industries. SEMI-THERM Conference and Exposition. Both events will be held at the page 18 Jeff Demmin Tessera Inc. INSIDE THIS ISSUE DoubleTree Hotel in San Jose, California. The Heat Is On 2012 will be Packaging and Test Many Factors Both Silicon 3D Players Markets Face Some Driving Chips Interposers and Need to Figure Substantial Headwinds Up Into the 3D Memory Out Their Spot Douglass Dixon Henkel Corporation as We Come to the Verticle Space Stacking Avail- in the Supply End of 2011 able From IBM Chain 14 20 22 SPRING 201130 MEPTEC Report 3 held on Monday, March 19th. SEMI-THERM runs March 18th to the 22nd. Nikhil Kelkar Intersil Corporation Nick Leonardi Premier Semiconductor Services Phil Marcoux ALLVIA, Inc. ANALYSIS – The markets for semiconductor packaging ANALYSIS FOLLOW-UP Semiconductor Manufacturing Markets 2.5D, 3D and Beyond Bhavesh Muni Dow Chemical Corp. Facing Uncertain 2012 Bringing 3D Integration to the Packaging Mainstream

Mark Stromberg Mark LaPedus, Senior Editor and test face some substantial headwinds as we come Gartner SemiMD Raj Pendse STATS ChipPAC The markeTs for semiconducTor for decades, The ic ProducTion, in-house memory and logic technologies, 14 packaging and test face some substantial packaging and test flows have been fabs and packaging expertise. headwinds as we come to the end of straightforward and predictable. for vendors that use third-party 2011. most notably is the global eco- But as the world moves toward the foundries and packaging houses in 2.5d nomic situation, highlighted by europe’s 2.5d and 3d chip era, the lines in the ic or 3D, the production flow consists of debt markets, and the recent flooding in manufacturing flow are blurring. Within multiple and complex choices, which, to the end of 2011. Most notably is the global economic situ- Thailand that severely damaged several these emerging segments, the chip “sup- in turn, will put pressure on the supply back-end processing plants. our cur- ply chain model is under stress,” said chain. during a presentation, rice out- rent projections call for essentially flat rich rice, senior vice president of sales lined several models for the interposer Rich Rice ASE (US) Inc. conditions in 2011 with saTs providers for north america at ase inc., the u.s. flow – all of which are viable: growing revenues about 2%, while back- arm for advanced semiconductor engi- • The foundry handles all steps, includ- end equipment suppliers will report sales neering inc. (ase) of Taiwan. ase is ing front-end production, interposer inte- in the negative 5 to 10% range. in 2012, the world’s largest ic-packaging and test gration and the backend steps. the saTs market will grow about 4% house. (plus or minus a percent or two) while There is little margin for error for • The foundry handles the front-end ation, highlighted by Europe’s debt markets, and the recent equipment vendors will record sales of 2.5d and 3d. The costs, yield and production. The interposer step is han- negative 15%. logistical issues are such that the par- dled by a separate “interposer foundry.” Jim Walker Gartner uncertainty continues to surround ties involved – chip makers, foundries, The backend steps are done at an ic- the world economic picture, but modest ic-packaging houses and others – must packaging house. global growth is still expected through of strong device sales growth has moder- There is also the major shift to Wafer- avoid risky IC projects and find a suit- • The foundry handles both the front- next year. There are substantial concerns ated this pace since the summer months. Level-Packaging and flip chip technolo- able return-on-investment. so, in the end and interposer production. Then, the regarding the european region, as each Test equipment orders fell off throughout gies. These package types will be the 2.5d and 3d chip worlds, it is essential backend steps are done at an ic-packag- week seems to deliver another solution the third quarter as memory pricing came dominate growth driver for the next half that chip makers develop a viable or ing house. soon followed by another crisis. The into question and the global economic decade. Growth in through-silicon-via “marketable product” and not devise flooding in Thailand. european situation, along with stagnant picture became less bright. equipment (TsV) will also begin to impact the “science projects,” rice said. • The foundry handles the front-end John Xie Altera Corporation conditions in the us, is placing substan- orders will likely remain sluggish until packaging market. memory vendors will sunil Patel, interim director for the production, while the ic-packaging tial roadblocks for the general electron- the macro picture begins to improve. begin ramping to production volumes of customer Package Technology Group house does the interposer and backend ics and semiconductor markets. for This will likely be the condition through TsV devices in 2012 and pilot produc- at Globalfoundries inc., agreed. “The steps. the semiconductor device market, 2011 the first half of 2012, at which point the tion will be seen at most major foundries current model is under strain. it has is still a debate regarding which seg- • Providing another viewpoint, Global- started strong, but has been hit with dif- market should be primed for substantial by the end of the year. copper wire to evolve,” Patel said. “an integrated ment – the front-end fabs or assembly foundries’ Patel outlined three separate ficulties since the Japan earthquake. Most capital budget increases leading into bonding will continue to capture share supply chain that offers yield account- houses – will actually do the interposer models in 2.5D and 3D: foundry plus, recently the market was impacted by the 2013. for 2013, the equipment market through our forecast horizon and will ability and competitive pricing needs to or through-silicon via (TsV) work. osaT plus and third party. Thailand floods which have placed sub- could very well be looking at another likely sit around 85% of all wire bonding emerge.” another question is which vendor stantial strain on the hard disk drive sup- strong cycle as pent up demand meets an processing by the end of this decade. during the “2.5d, 3d and Beyond,” will take charge of the interposer and in the foundry plus model, the found- ply chain. for 2011, the device market improved macro picture and forces sub- for 2011, the semiconductor market conference held november 9th in santa TsV-related failures. other unresolved ries handle most of the steps in the 2.5d is expected to fall by about 1% and will stantial capital purchases. has seen truly difficult conditions, which clara, california, sponsored by the questions include which vendor will be and 3D production flows. “The foundries be followed by a historically modest 2% on the packaging side there has are going to persist at least through the microelectronics Packaging and Test in charge of the bill of materials, inven- will be accountable for the yields,” he sales increase next year. saTs vendors been consistent movement towards the first half of next year. While naturally engineering council (mePTec), rice tory, integration and yield. said. Special Advisors remain cautious as sales have moder- leadless-leadframe package designs. This caused events such as the Japanese earth- and Patel separately described the vari- some vendors may have it easier in osaT plus, the foundries provide By Mark Stromberg ated in recent months. This has placed segment is the fastest growing portion of quake and Thailand floods cannot be ous business and supply chain models in than others in 2.5d and 3d. “idms are the front-end and interposer production, additional pressure on cap-ex budgets, as the packaging market and will continue foreseen, the era austerity from reduced the 2.5d and 3d chip arena. sitting pretty. They have the means and while the ic-packaging houses handle spending for SATS firms is now expected to dominate the space for the remainder government and individual spending is The IC industry is scrambling to find resources,” ase’s rice said. “The fab- the assembly steps. in the third-party to be in the negative 5% range next year. of our forecast period. (see graph above). here. While today’s savings will eventu- the right model for good reason. Both less-foundry-osaT supply chain model model, the customer or chip maker will for the equipment market, orders The leadless-leadframe market has ally lay the foundations for more robust 2.5d and 3d chip technologies are mak- is under stress.” manage the flow at the foundry or pack- have been modest since the end of 2010. also driven the wire bonder market and growth in the future a period of weak ing progress on the technology front, The integrated device manufactur- aging house and will take responsible for saTs vendors are willing to spend, but prolonged this technology’s use into the general semiconductor growth will pre- although there are still challenges. ers (idms), notably intel, samsung and the yield. This model is least likely to ◆ Bance Hom Consultech International, Inc. only once their bookings and long-term future by providing reduced form-factor vail for much of the next year and will But the projected product pricing possibly iBm, may have the resources succeed or take place, he added. Gartner contracts are locked in. While the transi- and improved functionality from tra- negatively impact the entire chain of the delta and the supply chain logistics in-house to set up a turnkey 3d chip ◆ Reprinted with permission of Semiconductor tion to copper bonding continues, a lack ditional QfP and soic package types. industry. remain problematic. for example, there operation. for example, samsung has the Manufacturing & Design (www.semimd.com). 14 MEPTEC REPORT WINTER 2011 meptec.org meptec.org WINTER 2011 MEPTEC REPORT 15 Ron Jones N-Able Group International Mary Olsson Gary Smith EDA Mike Pinelis MEMS Investor Journal PROFILE PROFILE – The Co-Founder and current CEO of World-Class Through-Silicon Via Development and Foundry Services

ALLVIA, Inc. offers a full lineup of Silicon Interposer processing and Through-Silicon Via foundry services for customers seeking quick turn Honorary Advisors custom R&D applications. With a full line of in-house processing equip- ALLVIA, Inc. coined the term TSV in 1997 as part of ment, ALLVIA offers services for prototyping as well as low volume production runs. 18 A portion of ALLVIA’s TSV fabrication equipment farm. Seth Alavi Sunsil Silicon Interposer Providing Silicon Interposer and Through-Silicon Via (TSV) Foundry Services ogy would be faster than what has since services to all interested parties. Design and happened. Drawing parallels with the his- Immediate plans call for ALLVIA to Manufacturing his original business plan. The vision of the business plan was to Semiconductor, Optoelectronics and MEMS Industries tory of flip chip technology may explain rapidly increase its production capability, why it is happening slowly. … There are to install additional quality and process five steps to be analyzed: feasibility, niche assurance tools, and to expand its design TO MAny PEOPLE THROUgH- In 2004 the company name was applications, reliability, cost reduction, center. Frontside/Filled Silicon Vias or TSVs is a new concept. changed from Tru-Si to ALLVIA when Dr. and high-volume production.” For more information about ALLVIA Vias ◆ Gary Catlin Plexus In truth the Co-Founder and current CEO Savastiouk was convinced that the indus- In 2009, ALLVIA focused on develop- services go to www.allvia.com. of ALLVIA, Inc. coined the term TSV in try was ready for TSVs. That same year, ment of silicon interposers with embedded 1997 as part of his original business plan. the company abandoned development of capacitors. Several different dielectrics From the beginning, the vision of the 3-D chip stacking and focused primarily have been evaluated for both manufactur- to create a through silicon interconnect since these would business plan was to create a through sili- on development of silicon interposers. ability and reliability. In 2010 the com- Backside/Conformal con interconnect since these would offer Since then ALLVIA has provided the TSV pany offered interposers with and without Vias significant performance improvements design and process development services embedded passives as a commercial over wirebonds. for numerous products and companies. service. Over the past decade, ALLVIA Located in Sunnyvale, California, Much development has been applied to continued to accumulate invaluable expe- Rob Cole ALLVIA’s Sunnyvale, California facility. ALLVIA started in 1997 under the com- creating manufacturing processes for both rience and to file for numerous patents pany name of Tru-Si Technologies. The 2.5-D chip stacking to wafer level stack- thick and thin wafer vias. ALLVIA uses related to TSV in its applications. Redistribution Layers company first focused on development ing in the future. In one of the sections DRIE etching, conventional copper plat- Early 2010, the company sponsored a RDL from Via’s to Solderable Pads #2. and manufacturing equipment capable of titled Through-Silicon Vias, Dr. Sergey ing and semiconductor photolithography webcast titled “Silicon Interposers with offer significant performance improvements over wirebonds. Atmospheric Downstream Plasma thin- Savastiouk wrote: “Investment in tech- processes for fabricating both the thick TSVs and Thin-Film Capacitors”. During ning of silicon wafers. The company nologies that provide both wafer-level and thin vias. Thick vias prefer different this webcast ALLVIA released a series of rapidly became identified with its demon- vertical miniaturization (wafer thinning) etch, via insulation and plating techniques tables showing favorable test results for temperature cycling, electrical measure- Via Deep strated ability to produce very thin (< 100 and preparation for vertical integration than thin shallow vias. Etching Skip Fehr micron) wafers which were very flexible. (through silicon vias) makes good sense.” After ten years of TSV trials and errors ments and capacitance measurements for Even though in the timeframe of 1997 He continued: “by removing the arbitrary as well as intensive work with custom- a number of test lots fabricated by the - 1999 the need for TSVs was non-exis- 2-D conceptual barrier associated with ers, another article was published in Solid company. This is one of the earliest sets tent, the company developed the very first Moore’s Law, we can open up a new State Technology magazine in December of data from a TSV development foundry interposer with TSVs prototype in 1999. dimension in ease of design, test, and of 2008 “Moore’s Law – the Z dimen- and was widely greeted as an indica- Via Copper tion that TSVs, Silicon Interposers, and The article “Moore’s Law – the Z manufacturing of IC packages. When we sion: a Decade Later” where analysis of a Revealed TSVs with Solder Bumps. Filling dimension” was published in Solid State need it the most – for portable comput- delay in adoption of TSV was presented. Capacitors on interposers are reliable and Technology magazine in January 2000. ing, memory cards, smart cards, cellular Dr. Sergey Savastiouk wrote about the last manufacturable. Since this webcast there Anna Gualtieri Elle Technology This article outlined the roadmap of the phones, and other uses – we can follow decade in TSVs: “Then, the expectation as been a rapid expansion of interest in TSV development as a transition from Moore’s Law into the Z dimension.” was that the acceptance of TSV technol- TSVs and interposers. Recently ALLVIA and Invensas (Tes- Via Backside Opening ALLVIA, INC. sera, Inc.) announced a joint venture. Under the terms of the venture Invensas agreed to acquire 64 of ALLVIA’s patents dealing with TSVs and related intercon- nection technology. ALLVIA agreed to provide Invensas ongoing process devel- Via Die Marc Papageorge Semiconductor Outsourcing opment and prototyping services. Having Attaching license-back of all its IP from Invensas, Silicon Interposer with Embedded Member company profile Back Side Via After Etch. Via After Etch. Via Copper Filled Vias Revealed. ALLVIA continues to provide the same Capacitors Solder Bumped to BT Substrate.

18 MEPTEC REPORT WINTER 2011 meptec.org meptec.org WINTER 2011 MEPTEC REPORT 19

Contributors INTEGRATION – “More Than Moore” is the name INTEGRATION Kevin Becker The industry has talked about Known when DRAM die are sold to be stacked, Consortia 3D Activity Integrating Multi-Die: Good Die (KGD) for at least two decades surely the integrator will want to know since MCMs were first made. The issue, of every detail about how to repair defective Sematech Design Enablement The Infrastructure Complexity course, is cascading yield, which with mul- die in the stack and avoid scrapping the IMEC Test Henkel Electronic Materials LLC tiple stacked die, means that any one die entire stack. ITRI 3D Foundry not working will kill the entire stack since Test is another critical area that will Ron Leckie CEA/Leti 2.5D to 3D Transition there is no ability to repair/replace defec- have a significant impact across the entire Infrastructure Advisors tive components at the 3D level with TSV 3D stacking process. Starting with Design, JEDEC Wide I/O Interface that has been coined for multi-die structures that en- technology. it will be essential to have extensive CMOSAIC Cooling Yield has always been the primary cost Design-For-Test (DFT) strategies imple- THERE ARE MAnY FACTORS variable in semiconductor manufactur- mented to ensure that the various functions Figure 2. Consortia Support of 3D. driving the industry to take chips up Richard Chen 20 ing, but there are many others too. When across the die stack can be accessed for into the vertical space. Moore’s Law has outsourcing, it should be remembered that controllability and observability to enable IBM and 3M are jointly working on devel- enabled the industry to cram more and the suppliers must also run their business fault identification and detection. The ATE oping underfill materials that will provide more functionality onto a single piece of model to make a profit and give returns to (tester hardware) is unlikely to be different suitable mechanical strength to the stacked silicon and it is getting to the point that shareholders. In the ideal outsource case, from what it is today, but to test die either thin die, while electrically isolating them unless you are making very large logic the supplier’s economies of scale will on wafers or individually by contacting but providing a thermally conductive envi- able the multiple die of different technologies to be stacked chips with hundreds of millions – even bil- enable them to sell at a price that is lower micro-bumps requires new probing tech- ronment. Dow Electronic Materials lions of transistors – it is getting difficult to than the buyer could build the component nologies. When available, probe cards that These are all good activities, but many employ all the transistors that can be placed for internally. With die for a 3D stack, the can achieve the targeted bump size and of the challenges will be solved by the pio- side-by-side on the silicon. “More Than main reasons to go to another supplier are pitch will be expensive. neers who drive 2.5D and 3D technologies Moore” is the name that has been coined because of their IP or because it is faster to Another question to consider is where through to real products. for multi-die structures that enable the market to buy rather than build that compo- to test the stack. Clearly, the die must be multiple die of different technologies to be nent. Either way, costs need to be carefully tested as thoroughly as possible by the die Market Adoption stacked together in a single package con- monitored and analyzed at the product defi- supplier to give the highest assurance that There are 2.5D products emerging now, taining most, if not all of the entire system. Jeffrey C. Demmin together in a single package containing most, if not all of the Figure 1. Disintegrated Flow. nition stage to assure that the end product they are “known good”. There is debate such as the Xilinx Virtex-7 2000T FPGA, The benefits are that not all functions will deliver the right price-performance whether there should be test steps at inter- which integrates an incredible 6.8 billion need to be put on a single, complex and ratio for the end customer. im stages as the stack is assembled, but this transistors across 4 die on a silicon sub- expensive piece of silicon. Different func- For some time, it was unclear where these the “good old days” of the semiconductor There are challenges at the Design stage seems excessive from a cost perspective. strate. For 3D with TSV technology, the tions can be made separately and more silicon substrates would be manufactured, industry when all companies were IDMs where system-level co-design is required Then there is the question of whether and first products will most likely be memory effectively before being integrated together but recently the Foundries have started to and controlled the entire process from start and involves not only the right tool set, but how to test any interposers that will be stacks that are being made by the large for a resulting cost-performance level that step up and provide manufacturing support to finish. After the Foundry model emerged Tessera, Inc also extremely close cooperation across used. Apparently, Xilinx has decided to not memory suppliers. With first products com- can make the challenges worthwhile. The for these. to fuel the OSAT and Fabless segments, all of the vendors supplying the various test silicon interposers, but to rely on more ing from Memory IDMs, this should help industry started doing this at simpler lev- In transitioning to full “3D”, the key soon this too became more complex as components. It requires 3D floor planning conservative design rules and inspection. contain some of the supply chain variables entire system. els with hybrids, which then evolved into process requirement is Thru-Silicon-Vias IDMs also use OSATs and Foundries. Some to encompass such elements as footprint, Of necessity for the TSV process, the while the process is proven. Multi-chip Modules (MCMs) and more (TSVs), a technology that has been widely IDMs even provide Foundry services. With TSV placement, interconnection paths, die are ultra thin and this will present han- With the cost challenges that are recently into System-in-Package (SiP) and covered in publications and the trade press stacked die, the flows will disintegrate fur- power distribution, noise floor, mechanical dling challenges throughout from wafer involved, we will continue to see these type Package-on-Package (PoP) technologies. to enable die to be tightly stacked verti- ther with, for example, a Fabless company simulation, etc. The parasitic models need level through shipping, to test and assem- of multi-die stacking solutions driven by Today’s “3D” packaging technology takes cally on top of each other. However, while designing a 3D stacked product with its to be extracted and validated for the TSV bly. The ITRS roadmap identifies die thick- products requiring the highest levels of per- that further with tighter, higher performing this wafer-level process, which essentially own logic die, a wireless chip from another Shashi Gupta structures, micro-bumps and interposers ness (or should I say thinness) targets that formance and integration density. It will be chip-to-chip interconnect plus the advan- involves “drilling” holes through from one Fabless company and memory chips from which all enable faster and lower-power go down to 10 microns, which is almost an some time before 3D technology is consid- tage of lower power consumption. side of thinned silicon to the other and an IDM. With each component supplier chip-to-chip interconnects. Thermal design order of magnitude thinner than a human ered as a solution to drive cost reduction. The technology that has emerged as “filling” it with conductive material is well having its own in-sourced or out-sourced needs to consider peak and ambient power, hair. At these levels, handling will raise In the end, widespread adoption of an interim step for some, but may be a understood, the bigger challenges will most manufacturing strategy and with potentially looking to manage and minimize hot spots the risk of bow, warp, stress and ultimately 3D will depend more on resolution of the permanent practical solution for others, is likely come from other elements in the sup- different manufacturing partners, one can within the structure. failure. above-mentioned infrastructure challenges named “2.5D”. This uses silicon interpos- ply chain. see the potential for extremely complex Henkel Electronic Materials, LLC IP disclosure and sharing will need to than on the fundamental process technol- ers to connect vertically and/or horizontally flows. be taken to new levels as the information Potential Solutions ogy. ◆ between multiple chips. The interposers use Infrastructure Challenges For such a complex logistics flow to necessary to be shared between die buyers All of these challenges may seem over- conventional wafer processing signal redis- The supply chain and infrastructure work, it will take extremely tight supplier and suppliers is much greater than it was whelming, but there are various organiza- Ron Leckie is President of infra- tribution technology to provide a higher- required to manufacture chips with TSVs relationships to assure process & footprint when simply buying packaged parts. Con- tions working diligently to address many structure Advisors, a consulting prac- BY Ron Leckie density and higher-performance intercon- has many more complexities and potential compatibility, specification control and sider, for example, a scenario where a 3D of them. Fig. 2 shows a table of several tice where he provides services such as nect between chips. This enables improved pitfalls than the standard manufacturing critical change control. When things go product design includes a stack of multiple Consortia activities that aim to pre-compet- strategic marketing, business develop- electrical and thermal performance over flows found in IDMs, Fabless, Foundry and wrong, which they inevitably do, there will DRAM die. When a DRAM vendor sells itively identify solutions. As can be seen, ment, M&A support, diligence, expert conventional wire bond technology. The OSAT companies. These challenges include be no time for finger pointing, just for very Subramanian S. Iyer, Ph.D. packaged DRAMS, they have the opportu- there is minimal overlap, so the tasks have witness and independent analyst current manufacturing challenges with yield, cost, quality & reliability, technol- fast problem solving and corrective action. nity to perform redundancy repair at wafer been divided up in line with the expertise services to clients. His technology and 2.5D revolve primarily around the silicon ogy, Intellectual Property (IP) and logistics. There will be little or no chance for alter- level and often also at packaged level to available at each organization and its mem- business experience spans 40 years in interposers. Other concerns involve how to In terms of logistics, consider the three nate sourcing of die or the 3D packaging repair die with defective or damaged cells. bership. semiconductor, capital equipment and the related supply chain. His website test these and their corresponding micro- simplified flows shown in Fig 1. The first is process, so partner selection will be critical. The IP surrounding such a repair strategy Additionally there are commercial col- Infrastructure Advisors is www.infras-advisors.com. bumps that are on the chips to be attached. the classic simple situation that existed in The biggest impact to cost will be yield. is not usually shared with customers, but laboration activities such as the one where IBM Corporation 20 MEPTEC REPORT WINTER 2011 meptec.org meptec.org WINTER 2011 MEPTEC REPORT 21 Ron Jones N-Able Group International Y.S. Kim TECHNOLOGY TECHNOLOGY – Performance improvement of Henkel Electronic Materials, LLC die in a multi-stacked 3D structure. tions and data are fed to the processor 3D Silicon Memory Applications Processor + Registers Some functions may be better suited from the L1 cache which in turn is fed by to a CMOS logic process where others the higher level caches. Subramanian S. Iyer, IBM Fellow and Michael Shapiro, 3DIC Business Manager are performance optimized in a DRAM Figure 4 shows a potential evolu- IBM Corporation L1 Cache process. Products can be built with die tion of the memory subsystem. In early from various technology and different Power™ processors (Power is a trademark lithography nodes. These products can of IBM Corporation), the L1 and L2 Mark LaPedus Figure 1. L2 Cache also be upgraded by simply replacing one caches were integrated onto the proces- of the die in the stack while keeping all sor chip using SRAM technology in SOI. semiconductors through device scaling is decreasing Performance improvement the other strata the same. Thus IP reuse is The L3 cache used logic based embedded of semiconductors through L3 Cache enabled with a simple substitution. DRAM in bulk silicon technology and device scaling is decreas- The 3D base technology advantages was integrated on a ceramic multi-chip 22 are important for adding memory capa- module (MCM). However, as we scaled ing from generation to gen- Figure 3. Memory subsystem schematic. SemiMD bility into system architectures. into the 45 nm generation, the latencies eration. 3D chip stacking and bandwidths available on MCMs lower Power MeMory evoluTIon In sysTeMs proved inadequate and the embedded technology is now a viaable High speed I/Os between chips can Memory plays a key role in modern DRAM was integrated monolithically account for almost as much as a third system design. System performance is onto the processor chip in SOI. This from generation to generation. 3D chip stacking technology option to increase the effec- tive performance of a sys- of the chip power. Low power signaling known to increase monotonically with allowed for an unprecedented improve- is possible with 3D technology because increased memory up to a point. How- ment in performance, power and the tem. Memory applications signals do not have to be driven through ever, the latency and bandwidth of this elimination of the MCM for memory Ron Leckie are good candidates for Base Technology advanTages Increased Bandwidth packages and boards. The data transfer memory must be optimized. Memory integration. of 3d 2D chips are I/O limited through the between two stacked chips is done on – processor integration has been a proto- 3d MeMory dIrecTIons applying 3D. IBM has devel- Both silicon interposers and 3D stacks package to which they are mounted. short vertical interconnect lines. Simple, typical SOC implementation and promis- oped both silicon interposer provide advantages over traditional Large advanced packages have ~1000s of low power drivers and receivers can be es to be one for 3D applications as well. Going forward, there are two distinct module on board assemblies in order board connections for power ground and used for signaling since there is much The memory subsystem is character- areas where we think 3D will play an is now a viable option to increase the effective performance and active chip stacking to increase the memory available for a signals. But with 3D, chips are stacked or less loss and noise. In ideal cases, a chip ized by a cache hierarchy depicted sche- increasingly important role. 3D stacking Infrastructure Advisors technology to enable clients central processor. A silicon interposer is a put on an interposer, the electrical con- stack may only have drivers and receiv- matically in Figure 3. The lower level will enable large local caches with low ers on the bottom tier which communi- caches tend to be smaller in size and fast- latencies. Silicon interposers will allow to design 3D semiconductors solution that can combine many ordinary nections can be reduced in size, leading 2D die (Figure 1). For example, when to a much larger number of I/O connec- cates with other chips on a board. The er compared to the higher level caches large memory capacities to be closely with large amounts of mem- four chips are interconnected on a silicon tions leading to higher bandwidths. As rest of the stack has no I/O which saves which tend to be slower but significantly connected to processors with low power signaling power. larger. Caches are also addressed through I/O. Some applications may even com- ory for their end products. interposer, only the interposer requires a result much more data can be passed TSVs. A 3D stack will add TSVs to between the chips vs. if they are mounted a directory unlike main memory, which bine both these versions of 3D memory heterogeneous combinations die that have active circuits (Figure 2). to a circuit board. This is especially is addressed directly. Typically the L1 hierarchy to optimize performance. Subramanian S. iyer, Ph.D. is Stacking of multiple chips allows for and L2 caches are based on fast SRAM ibm Fellow and Chief Technologist Because interconnection in a 3D stack important for multi-core die, because as of a system. Phil Marcoux the mixing of different semiconductor technology while the L3 is usually made 3d stack Memory applications at the microelectronics Division, involves short distances, the power of processor core counts increased, there ibm Systems & Technology Group. the chip the chip I/O is minimized. So is a need for higher bandwidth in order technologies. It is possible to separate up of a dense memory which can either The advent of multi-core processors he joined the ibm T. J. Watson depending on the application, a silicon to keep the cores from being starved of different functions onto a dedicated be SRAM or embedded DRAM. Instruc- and the logic power wall will prompt the research Center in 1981 and was interposer or a 3D stack may be more data. Also, now that the chip to chip con- proliferation of scale-out architectures. manager of the exploratory Struc- advantageous. There are three base nections are much shorter, signal transit This will put pressure to increase the tures and Devices Group until 1994, advantages that 3D technology offers times are much shorter. Die to die con- number of cores. However, this needs to ALLVIA, Inc. when he founded Sibond LLC. he compared to traditional 2D configura- nections in a 3D stack are shorter than be done while maintaining a balanced rejoined ibm in 1997 and developed tions in microelectronic applications. those on a silicon interposer. cache hierarchy. Unfortunately die size 2 ibm’s embedded Dram and eFuSe is constrained to about 600mm even for technology. he also led the develop- very high end systems and this means the ment of the 45 nm node in both SOi number of cores will be limited. An alter- and bulk. native is to stack the processor die on the memory die as shown in Figure 4 – this miChaeL ShaPirO, Ph.D. is allows us to maximize both the cores and the 3DiC business manager in the George Meyer memory in a manner that is technically microelectronics Division, ibm TIM1 TIM2 Logic Die feasible. The memory die is typically a By Subramanian Iyer, Ph.d. and Michael Shapiro, ph.d. Systems & Technology Group. his few to several watts while the processor work in multi-core architectures and Lid silicon processing convinced him that die is typically 100-200 W and needs to 3D technology was critical to the Memory be close to the heat sink as shown. This future of the semiconductor industry. Package TSV Die means that power delivery to the proces- Celsia Technologies Dr. Shapiro is an ibm austin master sor die must be made through the memo- inventor and holds more than 20 ry die using TSVs. The technology to do patents. PCB this has been discussed in great detail at IBM Corporation Figure 2. A 3D stack will add TSVs to die that have active circuits. Figure 4. Possible evolution of memory integration in modern multi-core processors. the recent MEPTEC conference “2.5D, 22 MEPTEC REPORT WINTER 2011 meptec.org meptec.org WINTER 2011 MEPTEC REPORT 23 Mike Pinelis, Ph.D. MEMS Investor Journal Michael Shapiro, Ph.D. IBM Corporation DEPARTMENTS 3 Board Letter 11 Industry Insights Column 26 Henkel News Mark Stromberg 5 Member News 12 Thermal Management Column 28 Dow Electronic Mtls. Gartner Tadashi Takano 10 MEMS Column 15 Event Follow-Up 30 Opinion Henkel Electronic Materials, LLC

MEPTEC Report Vol. 15, No. 4. Published quarterly by MEPCOM LLC, P. O. Box 222, Medicine Park, OK 73557. Copyright 2011 by MEPTEC/MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493, Fax Toll Free 1-866-424-0130. MEMBER NEWS

Meet the MEPTEC Advisory Board  Grand Opening of Expanded Xilinx Beijing Site, New R&D Center Xilinx, Inc. underscored its commitment to the high- growth China market at opening ceremonies for its new offices in Beijing. The company has expanded its footprint in the Asia Pacific region to include an R&D center, consolidating its local sales, marketing and application engineering Ivor Barber Jim Walker Dr. John Yuanlin Xie operations into a single LSI Corporation Gartner Altera Corporation site. The new 20,000 square-foot site will sup- In this issue we continue jim walker is Vice Dr. John xie is Senior port local, regional and introducing our fourteen Advisory President of Semiconductor Manager, Packaging Technol- multi-national customers. Board Members. All Board mem- Manufacturing and Emerging ogy Department, Altera Corp. bers are listed at the left. Technologies at Gartner. Jim and President, Chinese Insti- www.xilinx.com has been heavily involved in tute of Engineers USA, San ivor barber graduated  DELPHON CEO from Napier University in the science of semiconductor Francisco Bay Area Chapter. packaging since graduating Dr. Xie has been with Altera Jeanne Beacham Edinburgh, Scotland in 1981 Receives Two Pres- with a Bachelors degree in from California State Poly- Corporation for 12 years. He technic University. From 1982 leads the packaging design tigious Awards Technology. He has worked in Delphon Industries CEO package assembly and design to 1989, Jim performed vari- engineering, process engi- Jeanne Beacham was re- at National Semiconductor, ous roles at National Semi- neering and supply chain cently presented with two Fairchild Semiconductor and conductor, including serving engineering team. Prior to VLSI Technology. Ivor has as Surface Mount Packaging Altera, he was a technology separate awards for her spent the last 21 years at LSI Marketing Manager. Upon his development manager at leadership role in the Corporation in Milpitas in departure from National Semi, Prolinx Labs. Dr. Xie gradu- womans’ business com- various Engineering and Man- Mr. Walker co-founded Hana- ated from the Department of munity. Ms. Beacham agement positions in Assem- USA, a contract packaging Physics, Peking University, received the prestigious foundry. A founding member and holds a Ph.D. Degree in bly, Package Characterization “Woman Entrepreneur of of the Surface Mount Tech- Physics from the Institute of and Package Design. Ivor is the Year” award for manu- currently Director of Package nology Association (SMTA), Physics, Chinese Academy of Jim served as secretary and Sciences and Post Doctoral facturing from the Wom- Design and Characterization en’s Initiative in October. at LSI Corporation. Ivor holds treasurer before becoming from the Department of Phys- On September 22, 2011 12 U.S. patents related to President in 1990. Jim has ics, University of California, Delphon Industries was package design. authored over 40 techni- Berkeley and Lawrence cal articles and professional Berkeley Laboratory. Dr. Xie ranked #17 on the San papers on semiconductor has 24 published patents with Francisco Business Times’ packaging and surface mount 10 more pending and over 40 list of “Largest Women technology. academic and technical pub- Owned Businesses in the lications. Bay Area.” Together these awards recognize the dif- ference Ms. Beacham is SEMI Announces “Call for Presenters” for SEMICON West 2012 making in the community SEMI has announced a “Call for Presenters” for technical sessions and presentations at SEMICON West 2012, – mentoring others, lead- which takes place July 10-12 at the Moscone Center in San Francisco, California. Technical presentation ing by example, innovating abstracts are due March 15, 2012. SEMICON West 2012 will feature more than 40 hours of technical sessions within Delphon’s markets, and presentations across three show floor technology stages – the TechXPOTs – focused on critical industry and stimulating the local topics shaping design and manufacturing of semiconductors, high-brightness (HB) LEDs, MEMS, printed and economy. flexible electronics, and other related technologies. SEMI is soliciting technical presentations in topic areas www.delphon.com including: Wafer Processing, Test, Packaging, and “Extreme Electronics”. Prospective presenters are invited to submit abstracts on key industry issues and topics in the areas listed above for consideration.  Submissions may be made online from the SEMICON West 2012 website. For more details visit the SEMI website at www.semiconwest.org/Participate/SPCFP. ◆ meptec.org WINTER 2011 MEPTEC REPORT 5 MEMBER NEWS

 Intel, Micron STATS ChipPAC Completes Expansion of 300mm Extend NAND Wafer Bump and WLCSP Operation in Taiwan Flash Technology Leadership Capacity Expansion Supports Comprehensive Offering of Full Turnkey Intel Corporation and Wafer Bump and Wafer Level Packaging for Advanced 40µm Technology Micron Technology, Inc. have announced a new Singapore – STATS Chip- increases our ability to pro- benchmark in NAND flash PAC Ltd. has announced that vide customers with more it has completed the expan- cost-effective, high density technology - the world’s sion of its 300mm wafer wafer level packaging solu- first 20 nm, 128 Gb, multi- bump and Wafer Level Chip tions for thin, light weight, level-cell device. The com- Scale Packaging (WLCSP) portable products. We have panies also announced operation in Taiwan. STATS tripled our Class 100 clean- mass production of their ChipPAC has invested more room space to 3,478 square 64Gb 20nm NAND, which than US$150 million in tially the same size as the die, meters or 37,437 square feet further extends the compa- Taiwan to provide a strong achieving one of the most and significantly increased nies’ leadership in NAND full turnkey wafer bump and compact semiconductor pack- both our 300mm bump and process technology. WLCSP offering. With the age footprints with increased WLCSP capacity. We have Developed through recent expansion, production functionality, improved been working to expand our Intel and Micron’s joint- capacity at STATS Chip- thermal performance and technology processes to sup- PAC Taiwan Co., Ltd. has finer pitch interconnection port bump pitches down to development venture, IM increased to 420,000 bumped to the printed circuit board. 40µm,” said Richard Weng, Flash Technologies (IMFT), wafers per year and 60,000 STATS ChipPAC Taiwan’s Managing Director, STATS the new 20nm monolithic WLCSP devices per year. An advanced wafer level process ChipPAC Taiwan. “Our 128Gb device is the first official inauguration was held technologies include low cure customers have responded in the industry to enable a at STATS ChipPAC Taiwan temperature polymers and the favorably and we are working terabit of data storage in a with more than 80 honoured use of copper for under bump closely with them to acceler- fingertip-size package by guests and company manage- metallization (UBM) and ate our production ramp to using just eight die. ment participating. redistribution layers (RDL) to support the strong growth in www.intel.com For WLCSP, all of the achieve higher densities and demand for full turnkey wafer www.micron.com manufacturing process steps increased package reliabili- bump and wafer level packag- are performed in parallel ties. ing services.”  NEW Atomic- at the silicon wafer level “The addition of fully Further information about Level Film Treat- rather than sequentially on integrated wafer level pro- STATS ChipPAC products ment to Reduce individual chips. The result cessing capabilities in our and services is available at Chip Power is a package that is essen- Hsin-chu Hsien facility www.statschippac.com. ◆ Consumption Applied Materials, Inc. has announced a break- Market Growth for Packaging Materials through technology for reducing power consump- Advanced Packaging Unit Growth Drives Material Consumption tion in semiconductor Following a record year in terms a mobile form factor. Important growth areas in chips with its new Applied of semiconductor sales and unit shipments, 2011 packaging include chipscale packaging (CSP) Producer® Onyx™ film treat- turned into a lower growth year than initially – both laminate and leadframe based, stacked- ment system. By optimiz- expected with several challenges emerging for die and other 3-D packaging form factors, ing the molecular structure the packaging material suppliers. First, there wafer-level packaging (WLP), power device of the low k films that was the Tohuku earthquake and tsunami in packaging, LED packaging, and other system- insulate the miles of wiring, March that severely disrupted the packaging in-package (SiP) type technologies. The outlook or interconnects, on each materials supply chain. Numerous key suppli- for advanced packaging continues to remain ers lost production capability for several weeks strong, and this includes ball grid array (BGA), chip, the Producer Onyx and longer. While the supply chain recovered by CSP (including leadframe-based), flip chip, system enables customers the second quarter, a slowing global economy and WLP packages. And it will be new materi- to continue their relentless reduced the outlook for the semiconductor als that will enable packaging technologies to drive to fabricate faster, industry growth for the year. Finally, higher raw deliver solutions in terms of meeting demanding more power-efficient logic material costs, such as pricing for gold, silver, performance and reliability requirements. ◆ devices as they scale to tin, and copper metal, put the squeeze on suppli- the above information is an excerpt from the 22nm and below. er’s margins as customers pushed for lower cost recently completed market research study, Global www.appliedmaterials.com material solutions for their packaging needs. Semiconductor Packaging Materials Outlook – 2011-2012 Edition, produced by SEMI and Tech- packaging technology continues to be an  Search International. To order your copy contact Dr. important industry segment enabling growth in Dan P. Tracy at SEMI via email: [email protected], electronics that are increasing in functionality in or call 1.408.943.7987. 6 MEPTEC REPORT WINTER 2011 meptec.org MEMBER NEWS

 Camtek LTD. Global Low-Cost launches next generation AOI system Wafer Bumping Services Camtek Ltd. has announc- ed the launch of the Phoe- • Europe – USA – Asia • nix product family: The next generation of Auto- matic Optical Inspection (AOI) systems for the PCB and IC Substrates industry. The Phoenix product fam- ily is designed to support a broad range of the most demanding PCB and IC substrate applications, while keeping in pace with the PCB market’s dynamic technology changes. The Phoenix product family Quick-turn and is enhanced with Spark mass-production Available Processes – Camtek’s unique and Highly competitive, Electroless Ni/Au under-bump metallization powerful detection engine low-cost bumping providing high detection Ni/Au bump for ACF or NCP assembly technology capabilities, while minimiz- Exceptional quality Solder paste stencil printing ing false calls. Spark’s through high-level Solder ball drop for wafer-level CSP open architecture software expertise enables easy adaptation to Solder jet for micro-ball placement new applications and tech- BGA and CSP reballing nology, and supports criti- cal dimensions detection. Pac Tech GmbH Wafer backside thinning and wafer dicing Tel: +49 (0)3321/4495-100 www.camtek.co.il [email protected] Special Features/Technologies www.pactech.de Over 10 years experience  Freescale Pac Tech USA Launches “Free- Tel: 408-588-1925, ext. 202 U.S. Government Certified scale Mobile” [email protected] 4- to 12-inch wafer capability for Smartphone www.pactech-usa.com Platforms Pac Tech Asia Sdn. Bhd. Wafer pad metallization: Al and Cu Freescale Semiconduc- Tel: +60 (4) 6430 628 Solder alloys: eutectic SnPb37, lead-free, tor is putting its website [email protected] into customers’ hands with www.pactech-asia.com low-alpha, and AuSn the launch of “Freescale NAGASE & CO., LTD. Fluxless and contactless bumping for MEMS Mobile,” now available on Tel: +81-3-5640-2282 [email protected] and optoelectronics selected mobile brows- www.nagase.co.jp ers. Design engineers or Ni/Au interface for wire-bond applications anyone who needs imme- diate access to Freescale The leader in low-cost electroless wafer bumping. information can now eas- ily access and navigate World’s First Extensible Processing Platform – Now Shipping through information on Freescale’s portfolio of Xilinx, Inc. has announced its first Zynq™-7000 embedded processing Extensible Processing Platform (EPP) shipments to customers, solutions from the conve- a major milestone in the roll-out of a complete embedded pro- nience of a mobile device. cessing platform that for the first time offers developers ASIC www.freescale.com levels of performance and power consumption, the flexibility of an FPGA and the programmability of a microprocessor. Visit the  Xilinx website at www.xilinx.com for more information. ◆ meptec.org WINTER 2011 MEPTEC REPORT 7 MEMBER NEWS 3M and IBM to Develop New Types of Adhesives  ADI Enhances to Create 3D Semiconductors Signal Isolation with Industry’s Innovation leading to the creation of ‘Silicon Skyscrapers’ First 5-kV rms Signal tions. Processors could be tightly packed with Analog Devices, Inc. has memory and networking, for example, into a “brick” of silicon that would create a computer expanded its isolated inter- chip 1,000 times faster than today’s fastest face product portfolio with microprocessor enabling more powerful smart- the first signal-only isolated phones, tablets, computers and gaming devices. CAN (controller area net- the companies’ work can potentially leap- work) transceiver to pro- frog today’s current attempts at stacking chips vide an isolation rating to 5 vertically – known as 3D packaging. The joint kV rms with 125˚C opera- research tackles some of the thorniest techni- tion. The fully certified cal issues underlying the industry’s move to ADM3054 offers isolated true 3D chip forms. For example, new types power-detect functionality of adhesives are needed that can efficiently in a highly integrated single conduct heat through a densely packed stack of chips and away from heat-sensitive compo- surface mount package nents such as logic circuits. capable of operating in “Today’s chips, including those containing harsh industrial applica- ‘3D’ transistors, are in fact 2D chips that are tions. By reducing PCB still very flat structures,” said Bernard Meyer- component count by as son, VP of Research, IBM. “Our scientists are much as 70% compared to aiming to develop materials that will allow us traditional discrete, opto- ST. PAUL, MN & ARMONK, NY - 3M and to package tremendous amounts of computing coupler based component IBM have announced that the two companies power into a new form factor – a silicon ‘sky- circuits, the new CAN plan to jointly develop the first adhesives that scraper.’ We believe we can advance the state- transceiver greatly simpli- can be used to package semiconductors into of-art in packaging, and create a new class of fies design while reducing densely stacked silicon “towers.” The compa- semiconductors that offer more speed and capa- nies are aiming to create a new class of materi- bilities while they keep power usage low – key board space by up to 61%. als, which will make it possible to build, for the requirements for many manufacturers, espe- www.analog.com first time, commercial microprocessors com- cially for makers of tablets and smartphones.” posed of layers of up to 100 separate chips. For more information about IBM Micro-  UTAC Group such stacking would allow for dramatically electronics visit www.ibm.com/chips. For more to restructure higher levels of integration for information about 3M Electronics Markets Materials Divi- ITS Singapore technology and consumer electronics applica- sion visit www.3M.com/electronicbonding. ◆ operations UTAC Holdings Ltd. has announced that it plans to Gartner Says Worldwide Semiconductor Spending to Reach invest more than S$140 $309 Billion in 2012, a 2.2 Percent Increase from 2011 million over the next five years in its Singapore Worldwide semiconductor rev- slowed the PC market even percent increase from 2011. operations as part of a enue is forecast to reach $309 further. Gartner estimates that Gartner analysts said that as significant restructuring. billion in 2012, a 2.2 percent the supply chain disruption smartphones ramp up in vol- UTAC said the investment increase from 2011, according that resulted from the tragedy ume, they will dominate 2012 will increase the fixed to Gartner, Inc. This outlook is in Thailand meant that the PC semiconductor growth. down from Gartner’s previous production will be limited by the DRAM market is on assets, R&D and technical projection in the third quarter HDD availability over the next pace to decline 26 percent capabilities in Singapore for 4.6 percent growth in 2012. few quarters until the HDD in 2011, and the market will as part of a Group-wide pC production unit industry can resume full pro- return to growth when global strategy to re-align its growth for 2012 is projected duction. DRAM revenue is forecast manufacturing footprint in to increase 5 percent, which Gartner’s 4Q11 forecast to increase 3 percent in 2012. four countries and position is down from 10.1 percent does revise the mobile phone NAND flash is the expected to its Singapore operations – growth in the previous fore- production unit growth up be the fastest-growing device also the Group corporate cast. While the weak economic slightly for 2012 from 7 per- in 2012 with 16.6 percent headquarters – higher up backdrop played its part in this cent to 7.5 percent. The media growth because of strong the value chain. reduction, Gartner said that the tablet production forecast has growth in mobile consumer www.utacgroup.com ◆ floods that hit Thailand this been lowered from 110 mil- devices. year resulted in a hard-disk lion to 107 million in 2012, For more information visit drive (HDD) shortage that has although this is still a 63 www.gartner.com. ◆ 8 MEPTEC REPORT WINTER 2011 meptec.org PwC Report: China Storms Ahead in Semiconductor Consumption and IPOs

During the last decade, through ing for four of the five spots in the list of the ups and downs of two semiconductor largest semiconductor manufacturers in business cycles, China’s consumption China. growth has been greater than the rest of During 2010, two of the top ten world- the world for nine of the last ten years wide MNCs (multinational corporations) growing at a 24.8 per cent compound semiconductor companies established annual growth rate (CAGR). Worldwide wafer fabrication capabilities in China, consumption since 2000 has grown at a becoming the second and third largest mere 3.9 per cent with China accounting companies to do this. The top three MNC SRO – Solder for more than 40 per cent of overall global fabs in China represent 22 per cent of consumption. China’s current wafer fab capacity and al- Reflow Ovens Both the Chinese and worldwide semi- most all of its advance process technology. I Perfect reflow soldering conductor markets reached record levels in Throughout this period China increased I Rapid thermal annealing under controlled 2010 with China growing by 30.4 per cent wafer fabrication (fabs) capacity faster atmosphere, vacuum and pressure I to reach a new record of US$132 billion than the worldwide average. The net num- Perfect solder joints, no voids which was just slightly below the overall ber of fabs in production rose by 21 or 17 Also available industry growth of 31.8 per cent. per cent, which increased China’s capacity PEO – Semiconductor pricewaterhouseCooper’s report by 19 per cent. Worldwide, the net number Process Furnaces “China’s Impact on the Semiconductor of additional fabs in production (20) only Industry 2011 Update” predicts no near- increased worldwide capacity by 11 per term change in the factors leading to cent. U.S. and Canada China’s domination of semiconductor con- Representative: sumption. The continuing shift in world- Semiconductor Packaging, Assembly 328 Martin Avenue • Santa Clara, CA 95050 wide production of electronic products to and Test Tel: 408-588-1925 • Fax: 408-588-1927 China and the growing silicon content of China’s semiconductor packaging, Email: [email protected] these products are likely to drive further assembly and test (SPA&T) revenues grew www.pactech.de growth of semiconductor consumption in by a record 27.5 per cent to US$9.3 bil- the country. lion. The 106 SPA&T facilities represent: raman Chitkara, global Technology • 20 per cent of the total number of and Semiconductor leader, PwC said: SPA&T facilities “China continues to overshadow the rest of the world in semiconductor consump- • Almost 20 per cent of worldwide IC Assembly tion. And this domination has also SPA&T manufacturing floor space ranking Custom Package Development them ahead of Taiwan (just less than 20 contributed to China now accounting for a • Quick Turns, NPI, Volume Production majority of total semiconductor IPOs.” per cent) and Japan (18 per cent). • ITAR Registered • 23 per cent of reported worldwide • ISO 13485:2003 Medical Certified Mobile Devices Propel Growth in SPA&T employees, ahead of Malaysia (15 Plastic over molded, plastic IC Design Segment per cent) and Taiwan (15 per cent). open cavity & ceramic pack- age IC assembly. PROMEX led by mobile devices, the Integrated is a recognized leader in circuit (IC) design segment of China’s Greater China Semiconductor Industry stacked die, thin molded, semiconductor industry continued its the Greater China semiconductor 2D, 3D, SMT and RoHS compliant custom package explosive growth with a CAGR of 46 per industry also enjoyed a good 2010. development and volume cent over the past 10 years to reach rev- Taiwan’s semiconductor companies are assembly. SiPs, MEMS, Sen- enues of US$5.4 billion in 2010 up from well positioned to take advantage of the sors, RF Modules, Medical & Military Microelectronics. US$178 million in 2001. continuing growth in the Chinese mar- Companies in the communications sec- ket, which has become an increasingly JEDEC standard plastic tor, particularly mobile phones, achieved important production and sales location molded QFN/TQFN/DFN’s with custom versions rapid growth in revenues and size but for Taiwanese electronic manufacturing available. Same day quick those in the IC card sector saw a relative services (EMS) and original design manu- turns, development, pro- decline. IC design companies involved in facturers (ODM) companies and their totyping, “fast track” new product introductions mobile device design now dominate the supply chains. The easing of cross-Strait from beta manufacturing list of top ten IC designers. investment restrictions will also have a through onshore or pre- significant influence on the direction of Asia volume production. MNCs Key to Advanced Process growth of the semiconductor industry in Silicon Valley’s Packaging Foundry Technology in China this region. Tel. 408.496.0222 multinational integrated design manu- the PricewaterhouseCooper’s report facturers (IDMs) continue to dominate the is a public document and can be found at www.promex-ind.com Chinese semiconductor industry, account- www.pwc.com/chinasemicon. ◆ meptec.org WINTER 2011 MEPTEC REPORT 9 COLUMN

includes MEMS devices such as acceler- automotive vehicles with 18.3 million MEMS ometers, gyros, microphones, RF compo- units produced in 2010. As a comparison, nents, magnetic sensors, pico projectors the combined vehicle production in the TECHNOLOGY and others, the total market in China for EU was 17.1 million units, whereas Japan By Mike Pinelis, Ph.D. MEMS in smartphones can be as high and the US were at 9.6 and 7.8 million as $1.2-$1.4 billion. And this is just for units respectively. smartphones, not including other types of even though China is now the largest consumer electronics. automotive market, most of the cars that MEMS Activity interestingly, just this month a market are currently made and bought in China research firm Strategy Analytics reported are smaller and simpler than those in the in China: that, for the first time, China has over- US. Still, as the middle class in China taken the US as the largest smartphone accumulates more wealth, the consumers Trends and market. According to the latest numbers, will increasingly demand vehicles with 23.9 million smartphones were sold in advanced safety and performance features Developments China during the third quarter of this that are now common in the US and year while US shipments came in at 23.3 Europe. Furthermore, the Chinese govern-  Over the past two decades, million units. These numbers translate ment is already requiring advanced safety China has become an economic super- to roughly 100 million smartphones sold features such as tire pressure monitoring power that now rivals the United States in China per year. To be sure, the US and electronic stability control on the next and the European Union. In 2011, based smartphone market is still larger in terms generation of vehicles. Thus, the number on the purchasing power parity GDP mea- of revenue because smartphones in China of sensors and MEMS devices per car in sure, China already had the second larg- have a lower selling price than those in China’s market will continually increase. est national economy worldwide with its the US. According to Strategy Analytics, This trend, combined with the fact that GDP at $10.2 trillion. The US still holds Nokia currently has the largest smart- China is already the largest automotive the number one spot at $14.7 trillion, phone market share in China with 6.8 mil- market worldwide, will drive increased while countries of the EU have a com- lion units shipped in the third quarter of demand and rapid growth for automotive bined GDP of $15.2 trillion. To put this 2011. Nokia’s share equates to 28.5% of MEMS in China throughout this decade. in perspective, China’s economy is now all quarterly shipments in China. Samsung in addition to these trends in the larger than that of Japan, at $4.3 trillion, has a 17.6% market share with 4.2 million consumer electronics and automotive seg- and India, at $4.1 trillion, combined. units shipped. But Nokia and Samsung ments, China is also becoming a major Clearly, China is already a major eco- may not hold their dominant positions for market for MEMS applications in bio- nomic force and it is still growing at 7-8% too much longer as there is an emerging medical, aerospace and industrial sectors. per year. However, most of the Chinese wave of low-cost Android models from To gain an advantage in China’s emerging economy is still based on “low tech” local Chinese brands such as ZTE. MEMS marketplace, consider investing in manufacturing which does not generally the top companies in the US smart- our market research report and database as include technologies and infrastructure phone market, HTC and Apple, are also described below. ◆ used in making MEMS based devices and contenting for the top positions in China. systems. Still, as China pushes to expand In a recent conference call with industry Reprinted with permission from MEMS Investor Journal, Inc. its advanced manufacturing sector, it is analysts, Apple’s CEO Tim Cook said gradually establishing a domestic infra- that the company’s China revenue now structure of MEMS design houses, found- represents 16% of the total, as compared Dr. Mike Pinelis (mike@mem- ries and system integrators to become to only 2% in 2009. Apple is expanding sjournal.com) is the President and even more competitive with advanced its retail channel in China and now has 6 CEO of MEMS Investor Journal. technologies such as MEMS, semiconduc- retail stores and over 200 dedicated resell- This article is a part of MEMS tors, biotech and advanced materials. ers there. “How far can it go? Certainly Investor Journal’s ongoing market as with the overall MEMS market in my lifetime, I’ve never seen a coun- research project on MEMS activity worldwide, the leading MEMS applica- try with as many people rising into the in China. Currently they have devel- tions in China are those for the consumer middle class that aspire to buy products oped a report that lists 140+ of the electronics and automotive sectors. These that Apple makes. And so I think it’s an key MEMS companies and organiza- are the largest MEMS markets segments area of enormous opportunity, and it has tions in China. If you would like to in the US and Europe, and China is fol- quickly become number two on our list of receive this report, please contact lowing along the same trends. top revenue countries and we’re obviously them at [email protected] China’s domestic market for consumer placing additional investment,” said Cook. for more information about rates and electronics is huge, with the country’s another rapidly growing market for report contents. 1.34 billion citizens wanting the latest MEMS in China is the country’s automo- generations of devices and gadgets such tive industry. China became the world’s MEMS Investor Journal is the largest as smartphones, tablets, laptops, as well largest car market in 2009 when it over- MEMS publication with over 16,700 as gaming and navigation systems. To took the US in that position. Currently, subscribers worldwide. For more be sure, most of China’s population is there are 12-13 million new cars and light information about MEMS Investor still relatively poor and cannot afford trucks sold in the US, whereas China Journal and to subscribe, please go the latest products. Still, even if 20% of is getting close to the 20 million mark. to www.memsinvestorjournal.com. China’s population buys a smartphone that China is also now the largest maker of

10 MEPTEC REPORT WINTER 2011 meptec.org COLUMN

features and functions being designed into together multiple “standard” packages and INDUSTRY the lowly ubiquitous cell phone. Instead components into a high functioning final of arguing the idea of the SM or TC, let’s assembly. Over the years, we have known INSIGHTS look at the enablers that make these and these as hybrids, multichip modules, and By Ron Jones similar products practical in their current today as 2.5 and 3D assemblies. MCM’s and evolving form and function. were architecture than had multilayer the beginning is the circuit design substrates for chip connections, but typi- which underlies the product. There is cally only a single layer of chips. Today, it SmartPhones certainly a need for speed, not just in the is not feasible to integrate these multiple processing (operation) of the device, but chips and functions into a single chip, so and Tablets in the ability to move from one generation they must be assembled together using the to the next. The approach is to be able to vertical dimension for packing density.  An annual event I never miss initially integrate and manage functional The additional processing and components, is the Gartner update of the Semiconduc- building blocks into the final design. This such as interposers, have begun to blur tor Industry delivered by Jim Walker each includes GPS chips, multiple camera the line between what has typically been September at the MEPTEC luncheon. The chips, accelerometers, video processing, done by fabs versus SAT’s versus EMS’s. presentation includes macroeconomic driv- 3 axis gyroscopes, accelerometers, and Because there are so many different ap- ers and then drills down through product compasses. It takes an adaptable approach proaches for various applications, there and end market sectors to the implications to be able to accommodate all these new will be applications where fabs take on for fab, assembly and test. One slide in his functions quickly and efficiently, either more processes, those where SAT’s take on presentation this year captured my atten- internal or external, and that circuit is the more and those that are shared. tion and got me thinking about implica- application processor (AP), which is a this is a very exciting time for package tions to our industry going forward. The System on a Chip platform. The heart of development and the challenges will be slide had to do with revenue growth, but the AP is one or several processor cores. met by bright, talented and energetic mem- it was not the growth percent itself, but These are typically designed by ARM bers of our community. ◆ rather the makeup of the growth. Corporation, although Qualcomm designs Three-fourths (75%) of the semicon- their own cores. Typical AP’s used in the RON JONES is CEO and Founder ductor revenue growth between 2011 and SmartPhones and Tablet market are the TI of N-Able Group International. Visit 2012 will come from SmartPhones and OMAP, the NVIDIA Tegra or the Qual- www.n-ablegroup.com or email Ron Media Tablets. Notice, I said revenue comm Snapdragon. Due to the potential at [email protected] for growth, not total revenue. When you add of AP’s, other suppliers such as Marvell, more information. in solid state drives, the percentage goes Broadcom, Samsung and Renesas are up to 85%. A few other segments including entering the market. servers, PC’s, communications and auto- a second enabler is the wafer fab. The motive will be in mid-single digits and the Application Processors typically chase the remaining myriad sectors will experience leading edge fab processes. The current DON’T MISS shrinkage. stable of offerings is at 65 and 45 nm with this does not mean that companies announced plans for the next generations YOUR CHANCE associated with SmartPhones and Tablets going to 28 nm and below. While there are will be the only ones that will be success- myriad challenges to the march down the TO ADVERTISE ful. What it does say to me, however, is node pathway, there are many other appli- that companies that can capture the mind- cations that add impetus to the require- IN UPCOMING share of consumers in this space or support ments. In addition, the AP’s are large those that do, will be in line for explosive chips and potentially provide the volumes ISSUES OF growth over the next several years. that will help justify the move to 450 mm so what are the challenges to being wafers. THE MEPTEC able to deliver these and similar increas- in the old days, assembly and packag- ingly complex end products? There is no ing was a no brainer compared to wafer segment that has a lock on the challenges. fab. Whatever the fab guys could build, the REPORT One could argue that the basic concept for assembly guys could package. We are now the SmartPhones or the Tablet computer in a brave new world where factors such as For rates and schedule was key, though precursors of both have speed, power delivery and dissipation and contact Gina Edwards at been around for years. The Tablet PC packing density (x, y and z) are as large or was introduced by Microsoft in 2001, a larger challenges than design or fab. There [email protected] decade ago. It did not contain a camera, for is a proliferation of packages that mimic instance, but neither did the laptops of the Moore’s law for chips. It seems that the time. They did have the ability to listen and number of packages doubles about every 4 talk. One could argue that they were touted years. as a new form of computer, rather than as a there is a new challenge emerging that personal entertainment device, which made formerly was addressed by the EMS pro- the difference. SmartPhones, such as the viders. In order to achieve design guide- www.meptec.org iPhone are the natural evolution of more lines, it is necessary to find ways to cobble meptec.org WINTER 2011 MEPTEC REPORT 11 COLUMN

cost, and several studies have shown that THERMAL higher performing/higher cost thermal Open Cavity solutions actually have a rather short MANAGEMENT term payback in the reduction in electri- QFN By George Meyer cal consumption. Of course there is still a large part of the market where cost is the primary driver and the designs are priced out per pound. Trends and let’s take a look at some of the challenges in the thermal market today. Challenges We will start by taking a look at what DARPA is funding. DARPA currently  The field of electronics has several programs in the area of ther- Your thermal management is in its middle ages mal management. These are the TGP, Die MACE and NTI programs. Here and one would think that things would be getting a little boring. They are not! Looking back at the history of thermal NanoThermal Interfaces (NTI) “DARPA is soliciting innovative Fabless • MEMS • RF • Sensors management of electronics one can find reference material dating to mid-century, research proposals in the area of Nano- 1900’s. Seems odd saying mid-century Thermal Interfaces (NTI). The primary when discussing electronics thermal goal of this program is the development management! The history of thermal and demonstration of ideas based on management followed a pretty typical novel materials and structures that can technology development. First engineers provide significant reductions in the discovered heat was an issue, did some thermal resistance of the interface layer research and had something machined to (often called the TIM) between the back- (866) 404-8800 fit. Sometimes it worked, sometimes it side of an electronic device and the next failed. Traditionally, brown board testing layer of the package, which might be a was done, which means a new design spreader or a heatsink.” www.MirrorSemi.com was run and brown spots were looked for on the board. Seriously, this was an early Thermal Ground Plane (TGP) development process. Once the demand the Defense Advanced Research for these cooling things developed so did Projects Agency is soliciting research companies to serve the market. Most of proposals in the area of Thermal Ground these were the same machine shops that Plane (TGP). Proposed research should made the parts for the first prototypes. investigate innovative uses of 2-phase These companies, mostly western com- cooling, as in common heat pipes, where panies, enjoyed nice growth during the the benefits include very high thermal Underfi ll for Your Current 80s and 90s. The next big bang was due conduction and extreme reliability in a and Future Requirements to the dot com bust or at least set off by light-weight, thin, 2-D package that is the bust. Once the crash occurred, sur- also engineered to match the thermal viving OEM companies set about saving expansion of semiconductor substrates. money any way they could to stay afloat. This included sourcing all of their hard- Microtechnologies for Air-Cooled ware with the lowest possible suppliers, Exchangers (MACE) e.g. Asian sources. the primary goal of this program NAMICS is a leading source for high this was a severe blow to western is the development and demonstration technology underfi lls, encapsulants, suppliers, even those that had Asian of air-cooled exchangers that offer sig- coatings and specialty adhesives used facilities, as the lowest bids came from nificant reductions in thermal resistance by producers of semiconductor devic- low overhead Asian based companies. (from case to air) and significant reduc- es. Headquartered in Niigata, Japan The effect of this was that any real tions in the total electrical power used to with subsidiaries in the USA, Europe, research and development in the area of force the air through the system. Singapore and China, NAMICS serves thermal management ground to a halt. its worldwide customers with enabling Low margins equal little investment in Now keep in mind that these pro- products for leading edge applica- R&D. The good news is that this tran- grams are aimed at the requirements for tions. sition is behind us. The wounds have the military and may or may not mirror pretty much healed and there are serious the needs in the commercial world, but it challenges and opportunities in the ther- does shed some light on the challenges. For more information visit our website mal field again. interface materials continue to be a or call 408-516-4611 some of the challenges that we face challenge. This is due to several causes; today have more to do with energy one is the bulk conductivity of materi- www.namics.co.jp usage/costs than component or system als that meet the requirements of the

12 MEPTEC REPORT WINTER 2011 meptec.org market and the second is the interface of level and not the component level. We these materials with the semiconductor will continue to see the adoption of liq- Advanced and heat sink materials. We have had uid cooling. One key example of this is Component improvements in both areas but not often IBMs’ move back to using liquid cool- Labs, Inc. both combined, i.e., it is easy to improve ing. For a good look at a liquid cooling the bulk conductivity of interface materi- system that meets todays requirements als or the wetting of the materials but it take a look at the Coolit web site. is difficult to do both. The advancement One last note: about every ten years of nanomaterials holds promise but it’s developments come along that threaten too early to tell. the thermal management business. First the two other areas being addressed there was CMOS and most recently the by DARPA, two phase spreading and word on the street is that low power advances on the heat exchanger side, ARM chips will take a bite out of the may or may not have any impact on thermal market. I am not suggesting that “Time Critical” commercial applications in the foresee- it is not possible, all I know is that every able future. This is because the commer- time there is a reduction in power the Organic Substrates cial world has already done a pretty good demand for system performance quickly job of addressing these two areas and BGA, CSP, Flip Chip, High Frequency, heats things up again. How long do you High Speed, Rigid, Cavity and DARPA is looking to squeeze more per- think 4G will satisfy the consumers hun- Flex Packages formance for very high end applications. ger for bandwidth? - 20µm Lines and Spaces - one area ripe for an improvement is how do today’s engineers keep up ACL is the only in the area of air movers. Over the last to date on advances in this field? There North American company 15 years there has been steady improve- are several forums for doing this. The focusing exclusively ment in fan design giving us long lasting, traditional ones are events such as Semi- high performance air movers but the Therm, MEPTEC’s “The Heat is On” on the fabrication of issue of noise is a huge problem. Cool- Thermal Management Symposium, High Density Interconnects. ing electronics using air quickly reaches IMAPS-ATW, I-Therm and Interpack ITAR Registered a limit due to noise constraints. There and new forums such as Linkedin ther- Phone: 408.327.0200 Email: [email protected] are several new products being presented mal groups. For engineers in this field recently claiming to make improvements attending these events should be a must, www.aclusa.com from companies such as the Livermore not only for technical knowledge but National Labs, Novel Concepts and for networking. Generally speaking, Bergquist. The most interesting to me are someone at these events has encountered the miniature blowers being developed a problem you are facing and knowing by Bergquist. who you can contact to ask questions is very valuable, not only to your company Liquid Cooling but to you and your career. ◆ liquid cooling is often treated as the black sheep of cooling even though it offers the best performance next to direct George Meyer is an industry immersion cooling. Liquid cooling is veteran with over three decades simply a way to move heat efficiently, experience in electronics thermal and if it was not effective, your automo- management. He has been with biles would be using some other type of Celsia Technolgies since December cooling system. The drawbacks for liquid 2005, first as VP Sales and Market- cooling are primarily in two areas. First ing for the Americas and Europe and foremost is the risk of a leak. The regions and then as COO and CTO. best liquid cooling systems use water Visit www.celsiatechnologies.com or as a working fluid which we all know is email George at gmeyer@celsiatech- not a good thing to have in an electrical nologies.com for more information. system. From observations, the leak risk is more a human factor than a technical factor. Liquid cooling systems can be designed to be leak free. Tubing, fittings, etc, are available that meet the require- SPECIAL SEMI-THERM 28 EXPO OFFER! ments for reliability. The problems occur In a special offer for MEPTEC “Heat Is On when costs cutting is done or when user 2012” exhibitors only, SEMI-THERM is offer- induced damage occurs. The second con- ing exclusive table-top exhibit space for two cern is over cost. A liquid cooling system days in the foyer in front of the main SEMI- may cost several times that of a passive THERM exhibit hall. Contact Gina Edwards at system but the cost/benefit analysis needs [email protected] for more information. to be done at the system performance meptec.org WINTER 2011 MEPTEC REPORT 13 ANALYSIS

Semiconductor Manufacturing Markets Facing Uncertain 2012

Mark Stromberg Gartner

The markets for semiconductor packaging and test face some substantial headwinds as we come to the end of 2011. Most notably is the global eco- nomic situation, highlighted by Europe’s debt markets, and the recent flooding in Thailand that severely damaged several back-end processing plants. Our cur- rent projections call for essentially flat conditions in 2011 with SATS providers growing revenues about 2%, while back- end equipment suppliers will report sales in the negative 5 to 10% range. In 2012, the SATS market will grow about 4% (plus or minus a percent or two) while equipment vendors will record sales of negative 15%. uncertainty continues to surround the world economic picture, but modest global growth is still expected through of strong device sales growth has moder- There is also the major shift to Wafer- next year. There are substantial concerns ated this pace since the summer months. Level-Packaging and flip chip technolo- regarding the European region, as each Test equipment orders fell off throughout gies. These package types will be the week seems to deliver another solution the third quarter as memory pricing came dominate growth driver for the next half soon followed by another crisis. The into question and the global economic decade. Growth in through-silicon-via European situation, along with stagnant picture became less bright. Equipment (TSV) will also begin to impact the conditions in the US, is placing substan- orders will likely remain sluggish until packaging market. Memory vendors will tial roadblocks for the general electron- the macro picture begins to improve. begin ramping to production volumes of ics and semiconductor markets. For This will likely be the condition through TSV devices in 2012 and pilot produc- the semiconductor device market, 2011 the first half of 2012, at which point the tion will be seen at most major foundries started strong, but has been hit with dif- market should be primed for substantial by the end of the year. Copper wire ficulties since the Japan earthquake. Most capital budget increases leading into bonding will continue to capture share recently the market was impacted by the 2013. For 2013, the equipment market through our forecast horizon and will Thailand floods which have placed sub- could very well be looking at another likely sit around 85% of all wire bonding stantial strain on the hard disk drive sup- strong cycle as pent up demand meets an processing by the end of this decade. ply chain. For 2011, the device market improved macro picture and forces sub- For 2011, the semiconductor market is expected to fall by about 1% and will stantial capital purchases. has seen truly difficult conditions, which be followed by a historically modest 2% on the packaging side there has are going to persist at least through the sales increase next year. SATS vendors been consistent movement towards the first half of next year. While naturally remain cautious as sales have moder- leadless-leadframe package designs. This caused events such as the Japanese earth- ated in recent months. This has placed segment is the fastest growing portion of quake and Thailand floods cannot be additional pressure on cap-ex budgets, as the packaging market and will continue foreseen, the era austerity from reduced spending for SATS firms is now expected to dominate the space for the remainder government and individual spending is to be in the negative 5% range next year. of our forecast period. (See graph above). here. While today’s savings will eventu- For the equipment market, orders the leadless-leadframe market has ally lay the foundations for more robust have been modest since the end of 2010. also driven the wire bonder market and growth in the future a period of weak SATS vendors are willing to spend, but prolonged this technology’s use into the general semiconductor growth will pre- only once their bookings and long-term future by providing reduced form-factor vail for much of the next year and will contracts are locked in. While the transi- and improved functionality from tra- negatively impact the entire chain of the tion to copper bonding continues, a lack ditional QFP and SOIC package types. industry. ◆

14 MEPTEC REPORT WINTER 2011 meptec.org FOLLOW-UP

2.5D, 3D and Beyond Symposium Bringing 3D Integration to the Packaging Mainstream

Mark LaPedus, Senior Editor SemiMD

For decades, the IC production, in-house memory and logic technologies, packaging and test flows have been fabs and packaging expertise. straightforward and predictable. For vendors that use third-party But as the world moves toward the foundries and packaging houses in 2.5D 2.5D and 3D chip era, the lines in the IC or 3D, the production flow consists of manufacturing flow are blurring. Within multiple and complex choices, which, these emerging segments, the chip “sup- in turn, will put pressure on the supply ply chain model is under stress,” said chain. During a presentation, Rice out- Rich Rice, senior vice president of sales lined several models for the interposer for North America at ASE Inc., the U.S. flow – all of which are viable: arm for Advanced Semiconductor Engi- • The foundry handles all steps, includ- neering Inc. (ASE) of Taiwan. ASE is ing front-end production, interposer inte- the world’s largest IC-packaging and test gration and the backend steps. house. there is little margin for error for • The foundry handles the front-end 2.5D and 3D. The costs, yield and production. The interposer step is han- logistical issues are such that the par- dled by a separate “interposer foundry.” ties involved – chip makers, foundries, The backend steps are done at an IC- IC-packaging houses and others – must packaging house. avoid risky IC projects and find a suit- • The foundry handles both the front- able return-on-investment. So, in the end and interposer production. Then, the 2.5D and 3D chip worlds, it is essential backend steps are done at an IC-packag- that chip makers develop a viable or ing house. “marketable product” and not devise “science projects,” Rice said. • The foundry handles the front-end sunil Patel, interim director for the production, while the IC-packaging Customer Package Technology Group house does the interposer and backend at GlobalFoundries Inc., agreed. “The steps. current model is under strain. It has is still a debate regarding which seg- • Providing another viewpoint, Global- to evolve,” Patel said. “An integrated ment – the front-end fabs or assembly Foundries’ Patel outlined three separate supply chain that offers yield account- houses – will actually do the interposer models in 2.5D and 3D: foundry plus, ability and competitive pricing needs to or through-silicon via (TSV) work. OSAT plus and third party. emerge.” another question is which vendor During the “2.5D, 3D and Beyond,” will take charge of the interposer and in the foundry plus model, the found- conference held November 9th in Santa TSV-related failures. Other unresolved ries handle most of the steps in the 2.5D Clara, California, presented by the questions include which vendor will be and 3D production flows. “The foundries Microelectronics Packaging and Test in charge of the bill of materials, inven- will be accountable for the yields,” he Engineering Council (MEPTEC), Rice tory, integration and yield. said. and Patel separately described the vari- some vendors may have it easier in OSAT plus, the foundries provide ous business and supply chain models in than others in 2.5D and 3D. “IDMs are the front-end and interposer production, the 2.5D and 3D chip arena. sitting pretty. They have the means and while the IC-packaging houses handle The IC industry is scrambling to find resources,” ASE’s Rice said. “The fab- the assembly steps. In the third-party the right model for good reason. Both less-foundry-OSAT supply chain model model, the customer or chip maker will 2.5D and 3D chip technologies are mak- is under stress.” manage the flow at the foundry or pack- ing progress on the technology front, the integrated device manufactur- aging house and will take responsible for although there are still challenges. ers (IDMs), notably Intel, Samsung and the yield. This model is least likely to But the projected product pricing possibly IBM, may have the resources succeed or take place, he added. ◆ delta and the supply chain logistics in-house to set up a turnkey 3D chip Reprinted with permission of Semiconductor remain problematic. For example, there operation. For example, Samsung has the Manufacturing & Design (www.semimd.com). meptec.org WINTER 2011 MEPTEC REPORT 15 SYMPOSIUM

MEPTEC PRESENTS The Heat Is On 2012 Revolutionary and Evolutionary Innovations in Thermal Management Monday, March 19, 2012 • DoubleTree Hotel • San Jose, CA

Topics will include: Keynote Speaker n Trends and Challenges in Thermal Management n What’s New in Thermal Devices n Thermal Management Issues for 3D Packages n Thermal Management Issues for Data Centers n New Thermal Materials for Tablets, Handhelds, etc. n Energy Efficiency in Thermal Management Dr. Veerendra Mulay is responsible for thermal manage- n Advanced Research in Thermal Management ment of Facebook’s data centers and hardware. As a member of hardware design team, Veerendra lead the re-engineering of Face- book’s co-location data centers resulting in significant improve- ment in energy efficiency. He has been supporting design and con- struction of Facebook’s new highly efficient data center facilities. He is also a key contributor in Face- book’s custom designed servers and other hardware.

REGISTER ONLINE TODAY AT WWW.MEPTEC.ORG

Media Sponsors SEMI-THERM 2012 MEPTEC Thermal Management Symposium Monday, March 19, 2012 DoubleTree Hotel, San Jose, California

MEPTEC is pleased to  announce the continuation of our “Heat is On” symposiums, Packaging of electronics Opportunities for Exhibiting Symposium Committee and Sponsorship which for the second year will continues on rapid paths and Session Chairs be co-located with the 28th toward smaller size and/or there are several oppor- Annual SEMI-THERM confer- higher efficiency, sometimes David Copeland tunities to promote your ence and exposition. Thermal Engineer and company at Heat is On. A both. Inside their enclo- Packaging Technology In addition, in a special offer Sponsorship will provide sures, whether handheld or Oracle Systems for MEPTEC exhibitors only, rackmount, mobile or sta- Microelectronics many benefits, including SEMI-THERM is offering table- top exhibit space for two days Andy Delano, Ph.D. extensive marketing exposure tionary, indoor or outdoor, in the foyer in front of the main Technical Team Leader, through partnerships with the demand continues for SEMI-THERM exhibit hall. Advanced Thermal other industry organizations higher power and lower Management and publications. Options to SEMI-THERM has added temperature. Materials used Honeywell Electronic Materials some exciting new programs exhibit include just the Heat for packaging and cooling of Bhavesh Muni for 2012: is On, or a special discounted electronics are seeing evolu- Global Marketing Manager n The SEMI-THERM organiz- tionary, and sometimes revo- Dow Electronic Materials price to have an exhibit table ers are pleased for present a at Heat is On and a booth at Data Center Track targeted at lutionary, innovations which Thomas Tarter thermal issues ranging from enable continued progress. President SEMI-THERM 28. Please the component level through Energy conversion, transpor- Package Science Services LLC visit the event page at www. ◆ the system level all the way tation and lighting add their meptec.org for details. up to the complete center own thermal challenges to level. A panel discussion will be included, bringing together those of computing and com- Topics will include: leading members of the data munication. center industry to discuss key this symposium will n Trends and Challenges in Thermal Management industry issues. Collectively, offer outlooks of thermal n What’s New in Thermal Devices this comprehensive overview n Thermal Management Issues for 3D Packages of thermal issues at the various management devices and levels is must for participants, n materials, as well as integra- Thermal Management Issues for Data Centers in the data center industry and tion into electronic packag- n New Thermal Materials for Tablets, Handhelds, etc. for those that, wish to learn ing, from the viewpoints n Energy Efficiency in Thermal Management more about this fast growing industry. of suppliers and end users. n Advanced Research in Thermal Management n Six new technical courses We will look at forecast- are being offered in the ing trends as well as novel SEMI-THERM pre-conference methods and materials that program. These highly informa- go beyond the theoretical. tive courses span two days: Sunday, March 18 and Monday, Engineering and management March 19. These reasonably professionals alike will ben- priced and outstanding techni- efit from focused presenta- cal courses are focused on tions that will help them with the thermal sciences and are presented by leaders in the future planning, gaining a semiconductor cooling field. viewpoint from not just their own application and issues, but from the larger field of thermal management. Join us to hear the experts discuss where we are headed in this very important aspect of The DoubleTree Hotel is located at 2050 Gateway Place in San Jose, microelectronic packaging. ◆ CA and is adjacent to San Jose International Airport. meptec.org WINTER 2011 MEPTEC REPORT 17 PROFILE

Providing Silicon Interposer and Through-Silicon Via (TSV) Foundry Services to Semiconductor, Optoelectronics and MEMS Industries

To many people Through- In 2004 the company name was Silicon Vias or TSVs is a new concept. changed from Tru-Si to ALLVIA when Dr. In truth the Co-Founder and current CEO Savastiouk was convinced that the indus- of ALLVIA, Inc. coined the term TSV in try was ready for TSVs. That same year, 1997 as part of his original business plan. the company abandoned development of From the beginning, the vision of the 3-D chip stacking and focused primarily business plan was to create a through sili- on development of silicon interposers. con interconnect since these would offer Since then ALLVIA has provided the TSV significant performance improvements design and process development services over wirebonds. for numerous products and companies. located in Sunnyvale, California, ALLVIA’s Sunnyvale, California facility. much development has been applied to ALLVIA started in 1997 under the com- creating manufacturing processes for both pany name of Tru-Si Technologies. The 2.5-D chip stacking to wafer level stack- thick and thin wafer vias. ALLVIA uses company first focused on development ing in the future. In one of the sections DRIE etching, conventional copper plat- and manufacturing equipment capable of titled Through-Silicon Vias, Dr. Sergey ing and semiconductor photolithography Atmospheric Downstream Plasma thin- Savastiouk wrote: “Investment in tech- processes for fabricating both the thick ning of silicon wafers. The company nologies that provide both wafer-level and thin vias. Thick vias prefer different rapidly became identified with its demon- vertical miniaturization (wafer thinning) etch, via insulation and plating techniques strated ability to produce very thin (< 100 and preparation for vertical integration than thin shallow vias. micron) wafers which were very flexible. (through silicon vias) makes good sense.” after ten years of TSV trials and errors Even though in the timeframe of 1997 He continued: “by removing the arbitrary as well as intensive work with custom- - 1999 the need for TSVs was non-exis- 2-D conceptual barrier associated with ers, another article was published in Solid tent, the company developed the very first Moore’s Law, we can open up a new State Technology magazine in December interposer with TSVs prototype in 1999. dimension in ease of design, test, and of 2008 “Moore’s Law – the Z dimen- the article “Moore’s Law – the Z manufacturing of IC packages. When we sion: a Decade Later” where analysis of a dimension” was published in Solid State need it the most – for portable comput- delay in adoption of TSV was presented. Technology magazine in January 2000. ing, memory cards, smart cards, cellular Dr. Sergey Savastiouk wrote about the last This article outlined the roadmap of the phones, and other uses – we can follow decade in TSVs: “Then, the expectation TSV development as a transition from Moore’s Law into the Z dimension.” was that the acceptance of TSV technol-

Back Side Via After Etch. Via After Etch. Via Copper Filled Vias Revealed.

18 MEPTEC REPORT WINTER 2011 meptec.org World-Class Through-Silicon Via Development and Foundry Services

ALLVIA, Inc. offers a full lineup of Silicon Interposer processing and Through-Silicon Via foundry services for customers seeking quick turn custom R&D applications. With a full line of in-house processing equip- ment, ALLVIA offers services for prototyping as well as low volume production runs.

A portion of ALLVIA’s TSV fabrication equipment farm. Silicon Interposer ogy would be faster than what has since services to all interested parties. Design and happened. Drawing parallels with the his- immediate plans call for ALLVIA to Manufacturing tory of flip chip technology may explain rapidly increase its production capability, why it is happening slowly. … There are to install additional quality and process five steps to be analyzed: feasibility, niche assurance tools, and to expand its design applications, reliability, cost reduction, center. Frontside/Filled and high-volume production.” For more information about ALLVIA Vias In 2009, ALLVIA focused on develop- services go to www.allvia.com. ◆ ment of silicon interposers with embedded capacitors. Several different dielectrics have been evaluated for both manufactur- ability and reliability. In 2010 the com- Backside/Conformal pany offered interposers with and without Vias embedded passives as a commercial service. Over the past decade, ALLVIA continued to accumulate invaluable expe- rience and to file for numerous patents related to TSV in its applications. Redistribution Layers Early 2010, the company sponsored a RDL from Via’s to Solderable Pads #2. webcast titled “Silicon Interposers with TSVs and Thin-Film Capacitors”. During this webcast ALLVIA released a series of tables showing favorable test results for temperature cycling, electrical measure- Via Deep Etching ments and capacitance measurements for a number of test lots fabricated by the company. This is one of the earliest sets of data from a TSV development foundry and was widely greeted as an indica- Via Copper tion that TSVs, Silicon Interposers, and Revealed TSVs with Solder Bumps. Filling Capacitors on interposers are reliable and manufacturable. Since this webcast there as been a rapid expansion of interest in TSVs and interposers. recently ALLVIA and Invensas (Tes- Via Backside sera, Inc.) announced a joint venture. Opening Under the terms of the venture Invensas agreed to acquire 64 of ALLVIA’s patents dealing with TSVs and related intercon- nection technology. ALLVIA agreed to provide Invensas ongoing process devel- Via Die opment and prototyping services. Having Attaching license-back of all its IP from Invensas, Silicon Interposer with Embedded ALLVIA continues to provide the same Capacitors Solder Bumped to BT Substrate. meptec.org WINTER 2011 MEPTEC REPORT 19 INTEGRATION

Integrating Multi-Die: The Infrastructure Complexity

Ron Leckie Infrastructure Advisors

There are many factors driving the industry to take chips up into the vertical space. Moore’s Law has enabled the industry to cram more and more functionality onto a single piece of silicon and it is getting to the point that unless you are making very large logic chips with hundreds of millions – even bil- lions of transistors – it is getting difficult to employ all the transistors that can be placed side-by-side on the silicon. “More Than Moore” is the name that has been coined for multi-die structures that enable the multiple die of different technologies to be stacked together in a single package con- taining most, if not all of the entire system. Figure 1. Disintegrated Flow. The benefits are that not all functions need to be put on a single, complex and expensive piece of silicon. Different func- For some time, it was unclear where these the “good old days” of the semiconductor tions can be made separately and more silicon substrates would be manufactured, industry when all companies were IDMs effectively before being integrated together but recently the Foundries have started to and controlled the entire process from start for a resulting cost-performance level that step up and provide manufacturing support to finish. After the Foundry model emerged can make the challenges worthwhile. The for these. to fuel the OSAT and Fabless segments, industry started doing this at simpler lev- In transitioning to full “3D”, the key soon this too became more complex as els with hybrids, which then evolved into process requirement is Thru-Silicon-Vias IDMs also use OSATs and Foundries. Some Multi-chip Modules (MCMs) and more (TSVs), a technology that has been widely IDMs even provide Foundry services. With recently into System-in-Package (SiP) and covered in publications and the trade press stacked die, the flows will disintegrate fur- Package-on-Package (PoP) technologies. to enable die to be tightly stacked verti- ther with, for example, a Fabless company Today’s “3D” packaging technology takes cally on top of each other. However, while designing a 3D stacked product with its that further with tighter, higher performing this wafer-level process, which essentially own logic die, a wireless chip from another chip-to-chip interconnect plus the advan- involves “drilling” holes through from one Fabless company and memory chips from tage of lower power consumption. side of thinned silicon to the other and an IDM. With each component supplier the technology that has emerged as “filling” it with conductive material is well having its own in-sourced or out-sourced an interim step for some, but may be a understood, the bigger challenges will most manufacturing strategy and with potentially permanent practical solution for others, is likely come from other elements in the sup- different manufacturing partners, one can named “2.5D”. This uses silicon interpos- ply chain. see the potential for extremely complex ers to connect vertically and/or horizontally flows. between multiple chips. The interposers use Infrastructure Challenges For such a complex logistics flow to conventional wafer processing signal redis- the supply chain and infrastructure work, it will take extremely tight supplier tribution technology to provide a higher- required to manufacture chips with TSVs relationships to assure process & footprint density and higher-performance intercon- has many more complexities and potential compatibility, specification control and nect between chips. This enables improved pitfalls than the standard manufacturing critical change control. When things go electrical and thermal performance over flows found in IDMs, Fabless, Foundry and wrong, which they inevitably do, there will conventional wire bond technology. The OSAT companies. These challenges include be no time for finger pointing, just for very current manufacturing challenges with yield, cost, quality & reliability, technol- fast problem solving and corrective action. 2.5D revolve primarily around the silicon ogy, Intellectual Property (IP) and logistics. There will be little or no chance for alter- interposers. Other concerns involve how to in terms of logistics, consider the three nate sourcing of die or the 3D packaging test these and their corresponding micro- simplified flows shown in Fig 1. The first is process, so partner selection will be critical. bumps that are on the chips to be attached. the classic simple situation that existed in the biggest impact to cost will be yield.

20 MEPTEC REPORT WINTER 2011 meptec.org The industry has talked about Known when DRAM die are sold to be stacked, Consortia 3D Activity Good Die (KGD) for at least two decades surely the integrator will want to know since MCMs were first made. The issue, of every detail about how to repair defective Sematech Design Enablement course, is cascading yield, which with mul- die in the stack and avoid scrapping the IMEC Test tiple stacked die, means that any one die entire stack. ITRI 3D Foundry not working will kill the entire stack since test is another critical area that will CEA/Leti 2.5D to 3D Transition there is no ability to repair/replace defec- have a significant impact across the entire tive components at the 3D level with TSV 3D stacking process. Starting with Design, JEDEC Wide I/O Interface technology. it will be essential to have extensive CMOSAIC Cooling yield has always been the primary cost Design-For-Test (DFT) strategies imple- variable in semiconductor manufactur- mented to ensure that the various functions Figure 2. Consortia Support of 3D. ing, but there are many others too. When across the die stack can be accessed for outsourcing, it should be remembered that controllability and observability to enable IBM and 3M are jointly working on devel- the suppliers must also run their business fault identification and detection. The ATE oping underfill materials that will provide model to make a profit and give returns to (tester hardware) is unlikely to be different suitable mechanical strength to the stacked shareholders. In the ideal outsource case, from what it is today, but to test die either thin die, while electrically isolating them the supplier’s economies of scale will on wafers or individually by contacting but providing a thermally conductive envi- enable them to sell at a price that is lower micro-bumps requires new probing tech- ronment. than the buyer could build the component nologies. When available, probe cards that these are all good activities, but many for internally. With die for a 3D stack, the can achieve the targeted bump size and of the challenges will be solved by the pio- main reasons to go to another supplier are pitch will be expensive. neers who drive 2.5D and 3D technologies because of their IP or because it is faster to another question to consider is where through to real products. market to buy rather than build that compo- to test the stack. Clearly, the die must be nent. Either way, costs need to be carefully tested as thoroughly as possible by the die Market Adoption monitored and analyzed at the product defi- supplier to give the highest assurance that There are 2.5D products emerging now, nition stage to assure that the end product they are “known good”. There is debate such as the Xilinx Virtex-7 2000T FPGA, will deliver the right price-performance whether there should be test steps at inter- which integrates an incredible 6.8 billion ratio for the end customer. im stages as the stack is assembled, but this transistors across 4 die on a silicon sub- there are challenges at the Design stage seems excessive from a cost perspective. strate. For 3D with TSV technology, the where system-level co-design is required Then there is the question of whether and first products will most likely be memory and involves not only the right tool set, but how to test any interposers that will be stacks that are being made by the large also extremely close cooperation across used. Apparently, Xilinx has decided to not memory suppliers. With first products com- all of the vendors supplying the various test silicon interposers, but to rely on more ing from Memory IDMs, this should help components. It requires 3D floor planning conservative design rules and inspection. contain some of the supply chain variables to encompass such elements as footprint, of necessity for the TSV process, the while the process is proven. TSV placement, interconnection paths, die are ultra thin and this will present han- With the cost challenges that are power distribution, noise floor, mechanical dling challenges throughout from wafer involved, we will continue to see these type simulation, etc. The parasitic models need level through shipping, to test and assem- of multi-die stacking solutions driven by to be extracted and validated for the TSV bly. The ITRS roadmap identifies die thick- products requiring the highest levels of per- structures, micro-bumps and interposers ness (or should I say thinness) targets that formance and integration density. It will be which all enable faster and lower-power go down to 10 microns, which is almost an some time before 3D technology is consid- chip-to-chip interconnects. Thermal design order of magnitude thinner than a human ered as a solution to drive cost reduction. needs to consider peak and ambient power, hair. At these levels, handling will raise in the end, widespread adoption of looking to manage and minimize hot spots the risk of bow, warp, stress and ultimately 3D will depend more on resolution of the within the structure. failure. above-mentioned infrastructure challenges ip disclosure and sharing will need to than on the fundamental process technol- be taken to new levels as the information Potential Solutions ogy. ◆ necessary to be shared between die buyers all of these challenges may seem over- and suppliers is much greater than it was whelming, but there are various organiza- Ron Leckie is President of Infra- when simply buying packaged parts. Con- tions working diligently to address many structure Advisors, a consulting prac- sider, for example, a scenario where a 3D of them. Fig. 2 shows a table of several tice where he provides services such as product design includes a stack of multiple Consortia activities that aim to pre-compet- strategic marketing, business develop- DRAM die. When a DRAM vendor sells itively identify solutions. As can be seen, ment, M&A support, diligence, expert packaged DRAMS, they have the opportu- there is minimal overlap, so the tasks have witness and independent analyst nity to perform redundancy repair at wafer been divided up in line with the expertise services to clients. His technology and level and often also at packaged level to available at each organization and its mem- business experience spans 40 years in repair die with defective or damaged cells. bership. semiconductor, capital equipment and the related supply chain. His website The IP surrounding such a repair strategy additionally there are commercial col- is www.infras-advisors.com. is not usually shared with customers, but laboration activities such as the one where meptec.org WINTER 2011 MEPTEC REPORT 21 TECHNOLOGY

3D Silicon Memory Applications

Subramanian S. Iyer, IBM Fellow and Michael Shapiro, 3DIC Business Manager IBM Corporation

Figure 1. Performance improvement of semiconductors through device scaling is decreasing from generation to genera- tion. 3D chip stacking tech- nology is now a viable option to increase the effective performance of a system. Memory applications are good candidates for applying Base Technology Advantages Increased Bandwidth of 3D 2D chips are I/O limited through the 3D. IBM has developed both Both silicon interposers and 3D stacks package to which they are mounted. silicon interposer and active provide advantages over traditional Large advanced packages have ~1000s of chip stacking technology to module on board assemblies in order board connections for power ground and to increase the memory available for a signals. But with 3D, chips are stacked or enable clients to design 3D central processor. A silicon interposer is a put on an interposer, the electrical con- semiconductors with large solution that can combine many ordinary nections can be reduced in size, leading 2D die (Figure 1). For example, when to a much larger number of I/O connec- amounts of memory for their four chips are interconnected on a silicon tions leading to higher bandwidths. As end products. interposer, only the interposer requires a result much more data can be passed TSVs. A 3D stack will add TSVs to between the chips vs. if they are mounted Subramanian S. Iyer, Ph.D. is die that have active circuits (Figure 2). to a circuit board. This is especially IBM Fellow and Chief Technologist Because interconnection in a 3D stack important for multi-core die, because as at the Microelectronics Division, involves short distances, the power of processor core counts increased, there IBM Systems & Technology Group. the chip the chip I/O is minimized. So is a need for higher bandwidth in order He joined the IBM T. J. Watson depending on the application, a silicon to keep the cores from being starved of Research Center in 1981 and was interposer or a 3D stack may be more data. Also, now that the chip to chip con- manager of the Exploratory Struc- advantageous. There are three base nections are much shorter, signal transit tures and Devices Group until 1994, advantages that 3D technology offers times are much shorter. Die to die con- when he founded SiBond LLC. He compared to traditional 2D configura- nections in a 3D stack are shorter than rejoined IBM in 1997 and developed tions in microelectronic applications. those on a silicon interposer. IBM’s embedded DRAM and eFUSE technology. He also led the develop- ment of the 45 nm node in both SOI and Bulk.

MICHAEL SHAPIRO, PH.D. is the 3DIC Business Manager in the Microelectronics Division, IBM Systems & Technology Group. His TIM1 TIM2 Logic Die work in multi-core architectures and Lid silicon processing convinced him that 3D technology was critical to the Memory future of the semiconductor industry. Package TSV Die Dr. Shapiro is an IBM Austin Master Inventor and holds more than 20 patents. PCB Figure 2. A 3D stack will add TSVs to die that have active circuits.

22 MEPTEC REPORT WINTER 2011 meptec.org die in a multi-stacked 3D structure. tions and data are fed to the processor Processor + Registers Some functions may be better suited from the L1 cache which in turn is fed by to a CMOS logic process where others the higher level caches. are performance optimized in a DRAM Figure 4 shows a potential evolu- L1 Cache process. Products can be built with die tion of the memory subsystem. In early from various technology and different Power™ processors (Power is a trademark lithography nodes. These products can of IBM Corporation), the L1 and L2 L2 Cache also be upgraded by simply replacing one caches were integrated onto the proces- of the die in the stack while keeping all sor chip using SRAM technology in SOI. the other strata the same. Thus IP reuse is The L3 cache used logic based embedded L3 Cache enabled with a simple substitution. DRAM in bulk silicon technology and The 3D base technology advantages was integrated on a ceramic multi-chip are important for adding memory capa- module (MCM). However, as we scaled Figure 3. Memory subsystem schematic. bility into system architectures. into the 45 nm generation, the latencies and bandwidths available on MCMs Lower Power Memory Evolution in Systems proved inadequate and the embedded high speed I/Os between chips can memory plays a key role in modern DRAM was integrated monolithically account for almost as much as a third system design. System performance is onto the processor chip in SOI. This of the chip power. Low power signaling known to increase monotonically with allowed for an unprecedented improve- is possible with 3D technology because increased memory up to a point. How- ment in performance, power and the signals do not have to be driven through ever, the latency and bandwidth of this elimination of the MCM for memory packages and boards. The data transfer memory must be optimized. Memory integration. between two stacked chips is done on – processor integration has been a proto- short vertical interconnect lines. Simple, typical SOC implementation and promis- 3D Memory Directions low power drivers and receivers can be es to be one for 3D applications as well. Going forward, there are two distinct used for signaling since there is much the memory subsystem is character- areas where we think 3D will play an less loss and noise. In ideal cases, a chip ized by a cache hierarchy depicted sche- increasingly important role. 3D stacking stack may only have drivers and receiv- matically in Figure 3. The lower level will enable large local caches with low ers on the bottom tier which communi- caches tend to be smaller in size and fast- latencies. Silicon interposers will allow cates with other chips on a board. The er compared to the higher level caches large memory capacities to be closely rest of the stack has no I/O which saves which tend to be slower but significantly connected to processors with low power signaling power. larger. Caches are also addressed through I/O. Some applications may even com- a directory unlike main memory, which bine both these versions of 3D memory Heterogeneous Combinations is addressed directly. Typically the L1 hierarchy to optimize performance. stacking of multiple chips allows for and L2 caches are based on fast SRAM the mixing of different semiconductor technology while the L3 is usually made 3D Stack Memory Applications technologies. It is possible to separate up of a dense memory which can either the advent of multi-core processors different functions onto a dedicated be SRAM or embedded DRAM. Instruc- and the logic power wall will prompt the proliferation of scale-out architectures. This will put pressure to increase the number of cores. However, this needs to be done while maintaining a balanced cache hierarchy. Unfortunately die size is constrained to about 600mm2 even for very high end systems and this means the number of cores will be limited. An alter- native is to stack the processor die on the memory die as shown in Figure 4 – this allows us to maximize both the cores and memory in a manner that is technically feasible. The memory die is typically a few to several watts while the processor die is typically 100-200 W and needs to be close to the heat sink as shown. This means that power delivery to the proces- sor die must be made through the memo- ry die using TSVs. The technology to do this has been discussed in great detail at Figure 4. Possible evolution of memory integration in modern multi-core processors. the recent MEPTEC conference “2.5D, meptec.org WINTER 2011 MEPTEC REPORT 23 TECHNOLOGY

are reduced (Figure 5). Several new 3D stacking, a straightforward extension of Custom inspired protocols are being discussed 2D design concepts is adequate. This is Logic by JEDEC which promise to increase the because in most of the die-die integration bandwidth of DRAM memory for both schemes proposed for memory integra-

Stacked low power and high performance appli- tion, we are integrating at the I/O and Memory cations (separately). Several memory power delivery levels and for most part Silicon Interposer suppliers have demonstrated prototypes design systems that are used today for Figure 5. Placing a 3D memory on a silicon of stacked die that localize active I/O cir- package definition will be adequate with interposer with a processor die reduces the cuits to a single strata with the potential small modifications. I/O power significantly because the wiring of up to 50% power savings. the use of TSVs does complicate distances are reduced. if such memory becomes widely memory design as care should be taken available at competitive prices, we can that these do not disrupt array efficiency envisage the development of the system and yet permit a uniform distribution of 3D and Beyond”. We will discuss some on an interposer. In this scenario, the power to the chip above. TSVs will be of the design issues related to 3D later. processor cache stack is mounted on an placed around the memory macros to We expect the stacking of memory and interposer and surrounded by high band- bring power and ground to the stacked processors to be one of the early appli- width memory stacks. For many systems die. Redistribution metal is employed to cations for 3D integration in the logic this would be all that is needed, and re-route the electrical connections back arena. further scale out would be possible by over the top of the memory elements increasing the number of such interposer and up to the top die. The acceptable Silicon Interposer Memory units on a board. length of the wiring is determined by the Applications power needed by the top die, so a careful memory scaling also presents some 3D Design analysis of noise and droop is required big challenges. The usual productivity The implementation of 3D technology as shown in Figure 6. Today tools exist improvements attained by scaling are presupposes the existence of a design to perform this evaluation, though TSV getting more difficult to obtain especially system that comprehends 3D. Such placement is done in a custom manner. as lithography has become more com- design systems are evolving but for the For most designs the penalty for TSVs is plex. In addition, the use of very high memory applications outlined here, the relatively small (~10% area addition). speed I/O protocols such as DDR3 and methodologies are relatively simple. For Finally, memory die stacking DDR4 has made I/O power the dominant silicon interposers, existing multi-chip requires the use of known good die and power component (about 50-65%) of module wiring tools exist today to lay advanced module test techniques. This the total DRAM power. Placing a 3D out multiple die on large passive silicon is a complex requirement and the reader memory on a silicon interposer with a substrates. These design methods have is referred to several good papers that processor die reduces the I/O power sig- been used for years to design advanced were presented at the MEPTEC “Known nificantly because the wiring distances computer MCMs. For most 3D memory Good Die Conference”. Design for test techniques for silicon interposer and 3D stack modules is an emerging area. The Top-Chip IR Drop Contours module test pins need to access multiple die or built in self test must be employed to determine final functionality. If burn- in is required at module level, further complexity is involved to inject patterns to the logic and memory elements in multiple chips.

Conclusion revolutionary memory hierarchies are becoming available through silicon interposers and 3D stacks. Designers can increase the size and bandwidth of local and remote caches while at the same time reducing the I/O power. Computer server, networking and wireless applica- tions all plan to take advantage of this new memory paradigm. IBM has made both silicon interposers and 3D memory stacking available for designers in the 3DIC Cross-Section Bottom-Chip Steady-State Transient VDD Compression semiconductor industry. ◆ Figure 6. Analysis of noise and droop required to determine acceptable length of wiring.

24 MEPTEC REPORT WINTER 2011 meptec.org • Semiconductor • PhotovoltaicS • led SEMI • memS • Printed/Flexible e lectronicS Expositions • e merging m arketS

t he P remier international eventS F or micro – and nano – S cale manuF acturing

Semiconductor

december 7–9, 2011 sEMiCon Japan Chiba, Japan

February 7–9, 2012 sEMiCon Korea seoul, Korea

march 20–22, 2012 sEMiCon China shanghai, China

may 2–4, 2012 sEMiCon singapore singapore

may 15–16, 2012 sEMiCon Russia Moscow, Russia

July 10–12, 2012 sEMiCon West san Francisco, California

September 5–7, 2012 sEMiCon taiwan taipei, taiwan

october 9–11, 2012 sEMiCon Europa Dresden, Germany

PhotovoltaicS

november 9–11, 2011 soLARCon india Hyderabad, india

december 5–7, 2011 pVJapan Chiba, Japan

march 20–22, 2012 soLARCon China shanghai, China may 15–16, 2012 soLARCon Russia Moscow, Russia Conference and pavilion June 13–15, 2012 intersolar Europe Munich, Germany July 10–12, 2012 intersolar north America san Francisco, California

october 3–5, 2012 pV taiwan taipei, taiwan

FPd and led

october 26–28, 2011 FpD international Yokohama, Japan February 7–9, 2012 LED Korea seoul, Korea

march 20–22, 2012 FpD China shanghai, China

June 19–21, 2012 Display taiwan taipei,taiwan

For the complete schedule of SEMI expositions and events, visit www.semi.org/events Winter 2011

New Conductive Die Attach Films Extend Advantages to Leadframe Applications

Kevin Becker, Shashi Gupta, YS Kim and Tadashi Takano Henkel Electronic Materials, LLC

Until now, the undisputable tive die attach film portfolio that ensures applications that have previously relied on process benefits of die attach films have consistent silver distribution, thereby standard, non-power die attach pastes. been limited to laminate-based packages delivering a robust film solution for modern With this major breakthrough, leadframe that didn’t require conductive die attach leadframe package manufacturers. packaging specialists can now enjoy the materials. But, the same dynamics – name- The new ABLESTIK C100 conductive processability, performance and reliability ly, miniaturization and greater functional- die attach films are the first such materi- benefits that die attach films have over their ity – that are driving the laminate device als to be made commercially available and paste counterparts. The ABLESTIK C100 market are also impacting the leadframe arguably establish the benchmark for film- series of films are truly enabling, affording segment. Films, which offer added support based conductive die attach solutions. With manufacturers of modern lead-frame devices for processing today’s thin wafers, have availability in two different thicknesses the ability to produce smaller footprint pack- traditionally been available only for non- – ABLESTIK C130 in a 30 micron thick- ages with thinner die – all while improving conductive processes. ness and ABLESTIK C115 at 15 microns – process control, yield and reliability. as die have become thinner, process- Henkel’s latest innovation gives packaging But don’t just take our word for it. A ing them with conventional paste die attach specialists exceptional process flexibility. global semiconductor leader and advanced materials has become increasingly chal- chip packaging technology developer, lenging. With die thicknesses currently STMicroelectronics, recently incorporated pushing well below 75 microns to a mere ABLESTIK C100 materials into their pro- 50 microns, ensuring wafer stability and cess mix and attest to the advantages the processability is now more difficult than Henkel films deliver. STMicroelectronics ever. Die attach films, however, introduce Corporate Package Development Director a level of process control that simply isn’t for leaded package platforms, Laura Ceriati achievable with pastes, as the film itself says, “Our efforts with Henkel will enable provides additional support for the fragile and extend package scalability for the medi- wafer, making dicing and processing of the um-power applications that are a key part of wafer and subsequent die far more manage- ST’s product portfolio.” STMicroelectron- able. Not only do films offer added stability, ics has already successfully implemented they also extend numerous other perfor- Not only are there varying thicknesses for ABLESTIK C100 in very small package mance and reliability advantages including different application requirements, but the configurations. the elimination of die tilt, reduction in fillet new conducive films have been proven to of course, the materials specialists at width, and facilitation of greater bondline deliver excellent workability on die sizes Henkel aren’t stopping with the success control, therefore contributing to higher ranging from 0.2mm x 0.2mm up to 6mm of ABLESTIK C100. Next on the horizon yields, reduced package footprints, and bet- x 6mm. What’s more, the materials are suit- for conductive die attach films are highly ter long-term reliability. able for multiple package types including conductive films for power packages of Historically, the benefits of die attach QFNs and QFPs. all sizes. These next-generation products films have been limited to non-conductive From a performance point of view, will address the increased demands for applications due to the formulation chal- ABLESTIK conductive die attach films are power management by providing excellent lenges associated with developing conduc- also delivering great results. The materials in-package thermal conductivity, superior tive film materials, as well as the cost of have excellent wetting ability and lower electrical conductivity, high adhesion and manufacturing conductive films. Specifi- bonding temperatures which provide very reliability, along with the other benefits that cally, ensuring that a high volume percent- stable adhesion strength. This enables robust film adhesives always provide, such as bon- age of silver flake is evenly distributed adhesion against moisture and MSL Level 2 dline and fillet control. throughout the film, while enabling ease of performance on all leadframe surface finish- For more information on Henkel’s lamination and die attach, has been a hurdle es. While the ABLESTIK C100 films are not ABLESTIK C100 series of conductive die no materials formulator has been able to suitable for certain high power devices, their attach films, call the company headquarters overcome – until now. In an innovation thermal and electrical performance deliv- at 714-368-8000 or log onto www.henkel. milestone, Henkel has designed a conduc- ers an excellent replacement for conductive com/electronics. ◆

26 MEPTEC REPORT WINTER 2011 meptec.org

Anticipating your ideas Shows us the way to innovation

No matter where you are or what your process requires, you can count on Henkel’s expertise. Our unmatched portfolio of advanced materials for the semiconductor and assembly markets all backed by the innovation, knowledge and support of Henkel’s world-class global team ensures your success and guarantees a low-risk partnership proposition.

For more information contact: Henkel Americas: +1 888 943 6535 Henkel Europe: +44 1442 278 000 Henkel Asia: +86 21 2891 8000 www.henkel.com/electronics New Bump-plating Photoresist Offers Versatility and Lower Cost of Ownership

Richard Chen Dow Electronic Materials

The drive in consumer demand lower initial cost of dry film, this potential thickness uniformity less than 1.5% at 1 towards smaller and thinner electronics with savings is offset by the high cost of strip- standard deviation. INTERVIA™ BPN-65A more functionality is well documented, as ping. can be use in either i-Line or broad-band are the challenges associated with achiev- in response to the need for performance, exposure processing with a reduction step- ing integrated packages with the necessary ease of use and cost effectiveness in a single per or contact aligner. In addition to a lower reliability. Many packaging specialists will resist, Dow Electronic Materials is offering initial cost versus typical chemically-ampli- cite thermal management, such as changes INTERVIA™ BPN-65A Photoresist, a liquid, fied resists, reduced cost of ownership is in thermal coefficient expansion, integration single-spin, negative-tone resist that is for- achieved through the low dispense volumes of thinned wafers into stacked packages, or mulated specifically for wafer-level plating per wafer necessary for maximum perfor- meeting cost targets as some of the major (WLP) applications. The new resist’s chem- mance of the resist. A single coat of resist is challenges currently facing the industry as istry is an easy-to-strip formulation that uses all that is needed to support thick film cast- packaging designs advance. Some of these standard 0.26N TMAH developers, avoiding ing on 200 and 300 mm wafers. The dilution challenges also play into changes or new of this resist platform can be adjusted to fit material selections to better optimize current different resist thickness requirements. packaging designs. during the plating process, the pho- despite all of these complexities, reli- toresist exhibits no footing or undercut. ability and performance of advanced INTERVIA™ BPN-65A Photoresist also semiconductor packages is often only as has excellent chemical resistance, enabling good as the plated structures in each pack- the material to withstand a wide variety of age. It begins with the uniformity of plated both alkaline and acid plating chemistries structures across each die and across entire as well as etching solutions. These material wafers. With the drive towards a wider characteristics collectively result in plated variation of increasingly complex structures structures with maximum integrity. INTERVIA™ BPN-65A Photoresist, 50 μm with denser pitches, photoresists play a criti- additionally, this material provides thickness and 50 μm via. cal role more than ever in wafer-level plating excellent adhesion to a wide variety of process steps. It is clear that focusing atten- metal and organic WLP substrates, including tion on photoresist performance can make a aluminum, copper, gold, nickel, titanium, positive impact in the ultimate performance silicon, silicon dioxide, glass, ceramic and and reliability of the packaging, and it is also polyimide. INTERVIA™ BPN-65A Photore- clear that packaging fabs need new options sist retains flexibility after softbake, which that perform well, are easy to use and are is a contributing factor to the substrate com- cost effective. patibility of the material and to delivering Currently, a majority of photoresists improved reliability and quality. used for thick bump-plating applications INTERVIA™ BPN-65A Photoresist is are chemically amplified, and there are ideal for a variety of wafer-level plating trade-offs associated with using these INTERVIA™ BPN-65A Photoresist, 50 μm applications, including under-bump metal- resists. A major disadvantage to using thickness and 25 μm via. lization (UBM), SnAg and SnPb bump plat- chemically-amplified resists in packaging ing, and Cu pillar plating. The resist is ver- fabs is the extensive environmental control the environmental control complications that satile enough to deliver excellent uniformity that is necessary, resulting in expensive fab come with using chemically-amplified pho- within wafer for a range of structures, such improvements. Resist performance issues, toresists for bump plating. Both NMP and as bumps, Cu studs, capped and uncapped such as T-tops in resist profiles, can result DMSO-based strippers can work well with Cu pillars, and Cu pillar mushroom bumps. from lack of environmental control in a fab the resist, and the choice is dependent on the For packaging fabs looking for a using chemically-amplified resists. In addi- size and pitch of the features. bump-plating photoresist that provides a tion, outgassing that occurs during hotplate INTERVIA™ BPN-65A Photoresist over- wide range of capabilities and lower cost and exposure steps can cause contamination comes the environmental control obstacles of ownership without the environmental and can obstruct venting during processing. and matches stripping capabilities while pro- control requirements inherent in chemically- Clearly, tight environmental control is a viding comparable lithographic performance amplified resists, INTERVIA™ BPN-65A necessity with chemically-amplified resists. to chemically-amplified resists. INTERVIA™ Photoresist may be the ideal choice. For Although dry film resists can be used, chem- BPN-65A Photoresist is capable of imag- information regarding this material or any of ically-amplified photoresists are typically ing vertical sidewalls in features with 2:1 Dow’s advanced packaging materials, visit used for bumping applications because they or greater aspect ratios in resist thicknesses www.dow.com or call 508-481-7950. ◆ are easier than dry film to strip. Despite the between 30 and 60 µm with excellent film 28 MEPTEC REPORT WINTER 2011 meptec.org

OPINION

3D Infrastructure – Time to Place Your Bets

Jeffrey C. Demmin, Senior Director of Corporate Development Tessera, Inc.

iF anyone doubted the accel- TSV processes, not only to have a bigger For example, Sematech has put together erating reality of 3D, 2.5D, and through-sil- slice of the pie, but also to avoid yield and a handy “dashboard” that tracks all of the icon vias (TSVs), MEPTEC’s symposium handling issues associated with receiving standardization efforts. The fact that this is in November should have taken care of wafers that are already thinned. Found- necessary, however, shows that some con- that. The event – “2.5D, 3D and Beyond: ries have a similar interest in maximizing vergence is still needed. If a dashboard is Bringing 3D Integration to the Packaging their ownership of the supply chain, but required to keep track of all of the relevant Mainstream” – highlighted many chal- ChoonHeung Lee of Amkor asserted that standards efforts, there are probably too lenges and opportunities in the field, and foundries aren’t particularly interested in many of them. I expect that the appropri- emerging supply chain options bubbled interposer-only business. It is just another ate coalescence will happen as the industry to the top of that list. When the debate in offering that helps attract more convention- continues to mature. an industry moves from “Look how cool al foundry business. Given that interposers While the supply chain has been the this is!” to “Who will supply what, and will be part of primarily leading edge prod- hottest topic, MEPTEC’s symposium cov- how soon?” it is a legitimate industry. The ucts for a while, it could be a smart move ered many technical challenges as well. discussion identified multiple supply chain to offer services targeting those products. Interposer warpage was discussed at least configurations, but with the growing inter- of course, it all comes down to cost, so as much as anything else, with all three est and activity, 3D players need to figure whatever supply chain flow enables overall of the major OSATs presenting at the out their spot in it soon. cost reduction is the one that will succeed. symposium going into detail on this issue. the majority of MEPTEC’s sympo- If the lowest cost set of providers varies by This strikes me as very solvable, though, sium focused on silicon interposers, which product type, then more than one supply with clever process engineers and materi- reflected the mainstream status of this chain option will likely survive. As Rich als scientists devising solutions as needed. early incarnation of 3D technology. It was Rice of ASE stated, the traditional fabless / The packaging industry has resolved many widely agreed that interposers, which were foundry / OSAT supply chain is being chal- kinds of similar thermal mismatch issues, first categorized as “2.5D” by ASE’s Ho- lenged with roles changing and overlap- so we should be able to draw on that expe- Ming Tong, represent the key step toward ping, and companies will have to take some rience here. bringing true 3D integration to the industry. risk to make the investment to continue an encouraging sign that MEPTEC hit Many of the technical challenges of vertical playing in the world of interposers and 3D on the right topic was the response in the interconnect through ICs are being resolved technology. press to the event. Several good summaries in the development of passive silicon inter- one interesting comparison was raised appeared right after the symposium, and posers, but perhaps more importantly, the by Sunil Patel of Global Foundries, who I saw these get forwarded around through interposer step allows the industry to have posed the question of whether or not inter- various internet groups. Mark Lapedus of a trial run at establishing the infrastructure posers will follow the progression of organ- SemiMD (see page 15), Ira Feldman of for this new area of technology. ic BGA substrates over the last decade or Feldman Engineering, and Francoise von the key question for the interposer sup- so. Specifically, substrates were originally Trapp of 3D InCites all published insight- ply chain is what type of companies will be provided primarily by a concentrated set ful summaries within a few days of the doing the steps that follow the etching of of suppliers (in Japan in this case), and symposium. Perhaps those reports on 3D TSVs in interposer wafers. It was generally then the supplier base expanded with cost technology and interposers at this time next agreed that wafer processing companies, reduction and competitive evolution. This year will highlight the cost reduction that like foundries and integrated device manu- comparison suggests that there will be spe- comes with high volume manufacturing. If facturers (IDMs), would be the companies cialized suppliers of interposers as their pri- the players in the 3D and interposer world doing high volume TSV etching. There mary product. ChoonHeung Lee of Amkor figure out their roles, I would bet on that.◆ are many processes following via creation also noted that interposers can be treated as – interconnect, wafer thinning, edge treat- consigned material in the process, exactly ment, etc. – and it was stated by many like the substrates currently in widespread Jeff Demmin joined Tessera in speakers that either the wafer processors use. 2002 after serving as the editor-in- or the OSATs could perform those. Amkor, the eventual number and nature of chief of Advanced Packaging maga- ASE, and STATS ChipPAC all gave talks at interposer suppliers might hinge on the zine. Previously, Jeff held a succes- the symposium outlining their capabilities development of standards, and along these sion of assembly and test engineering for those steps. lines, Herb Reiter of eda2asic presented an posts at National Semiconductor, osats want to perform the post-etch update on 3D standards at the symposium. nCHIP, Seagate, and Textron Systems.

30 MEPTEC REPORT WINTER 2011 meptec.org Innovation drives results

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