Product Design for Wire-Bondability

2018

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 22, Number 2 SUMMER

PRODUCT DESIGN FOR WIRE-BONDABILITY Developing a Wire Bond Interconnect Begins with the End in Mind page 24 + Top 4 Considerations When Disposing of a Cleanroom Facility page 34

MEPTEC MEMBER COMPANY PROFILE Founded in 1976, Samtec is a privately held, $713 million global manufacturer of a broad line of electronic interconnect solutions. Samtec is headquartered in New Albany, Indiana, USA. Their global reach includes over 5,000 employees with 33 locations in 24 countries. page 12

-Corp. INSIDE THIS ISSUE

Copper clip The design of an Technology develop- Selling a manufactur- based package ASIC is often the ments, market trends, ing asset such as a integration sol- key to success for recent patents, and cleanroom facility can ution provides medical device news from Binghamton be a difficult and time- key advantages. developers. University. intensive process. 16 20 27 SPRING34 2011 MEPTEC Report 3 A proud legacy. An exciting future.

As the original pioneers of the OSAT industry, Amkor has helped deﬁne and advance the technology manufacturing landscape. Since 1968, we’ve delivered innovative packaging solutions with the service and capacity global customers rely on. We’re proud of what we’ve done, and can’t wait to show you what’s next.

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A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 22, Number 2 SUMMER Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards 2018 ON THE COVER A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 22, Number 2 SUMMER

PRODUCT DESIGN FOR Wire bonding is a commonly used process to create low-cost and reliable WIRE-BONDABILITY MEPTEC Advisory Board Developing a Wire Bond Interconnect electrical interconnects for microelectronic assemblies and is used to manu- Begins with the End in Mind page 24 facture the vast majority of fully packaged semiconductor products. More Board Members + Top 4 Considerations When recently, it is being used as an interconnect solution for batteries. When Disposing of a Cleanroom Facility page 34 developing a wire bond interconnect it is important to begin the design with Ivor Barber AMD MEPTEC MEMBER COMPANY PROFILE Founded in 1976, Samtec is a privately held, $713 million global manufacturer of a broad line of electronic interconnect the end in mind. The best outcomes can be achieved when the design team solutions. Samtec is headquartered in New Albany, Indiana, USA. Their global reach includes over 5,000 employees with 33 locations in 24 countries. Jack Belani Indium Corporation page 12 includes the process engineering team in the design reviews and product deci- -Corp. INSIDE THIS ISSUE

Copper clip The design of an Technology develop- Selling a manufactur- based package ASIC is often the ments, market trends, ing asset such as a sions as early in the cycle as possible. integration sol- key to success for recent patents, and cleanroom facility can SemiOps ution provides medical device news from Binghamton be a difficult and time- Joel Camarda key advantages. developers. University. intensive process. 16 20 27 SPRING34 2011 MEPTEC Report 3 Cover Photo Courtesy of SMART Microsystems Ltd. Jeff Demmin Booz Allen Hamilton

Douglass Dixon Henkel Corporation PROFILE – By integrating specialized technology centers PROFILE KEY PRODUCTS AND TECHNOLOGIES SILICON-TO-SILICON Samtec’s history is a manufacturer of high speed board-to-board intercon- SMART Microsystems Samtec’s Corporate Headquarters in New Albany, IN, USA nects and cable systems, and of having Nick Leonardi the industry’s largest variety of two-piece board stacking connector products. led by industry experts working side-by-side, Samtec fos- In the last decade Samtec’s Silicon- MICROELECTRONICS to-Silicon business model continues to distinguish and define Samtec. Simply INTERCONNECT SOLUTIONS put, Silicon-to-Silicon capabilities assist 12 designers in optimizing the high-speed serial path from bare die, to IC package QUICK HISTORY employees. FOUNDED IN 1976, Samtec is a privately and assembly, to PCB, to connectors, to In the mid-1970s, Sam Shine was The company’s business model was held, $713 million global manufacturer of cable assemblies, and back again. These Vice President of Sales and Marketing for “Sudden Service.” Simply put, the goal a broad line of electronic intercon-nect capabilities include: a mid-sized connector company that was was to deliver quality products with the solutions. Samtec is headquartered in ters an environment conducive to true innovation and collabo- best customer service in the industry. At • Assisting IC layout designers to opti- PPM Associates riding a wave of increased demand and New Albany, Indiana.Their global reach Phil Marcoux the time, Sudden Service principals were: mize power and signal integrity of the includes over 5,000 employees with 33 had decided to become a major player bare die during the IC design process locations in 24 countries. Manufacturing in the market by going public. Pleasing • Quick turn-around of orders, large is performed in 12 different locations: stock holders with growth at any cost and small • Developing complex, customized became the work of the day. As automat- New Albany, IN; Scottsburg, IN; Colo- • Quick delivery of samples IC packaging and assembly solutions Samtec’s High-Speed Cable Assemblies rado Springs, CO; Wilsonville, OR; Costa ed production processes became increas- enabling maximum IC density, preci- Rica; Huizhou China; Dongguan, China; ingly inflexible, Shine became increas- • Quick delivery of catalogs sion and ruggedness grounding and routing flexibility. They ety of high-speed interconnects, in either Johor, Malaysia; Penang, Malaysia; Tai- ingly frustrated, feeling the company was • Prompt, correct answers to technical • Enabling PCB designers to create dens- are available with up to 560 I/Os, with single ended 50 Ω or 100 Ω differential ration. They have more than 600 separate product series which wan, Singapore and Vietnam. losing its ability to service customers. and order status inquiries Samtec has more than 600 sepa- Large minimum order quantities, er, faster PCBs by providing factory stack heights up to 40 mm, with option- pairs, across a variety of centerlines and • Consistent follow-through on all rate product series which results in over long delivery lead times that sometimes and field-based technical support to al power modules. configurations. shipments 108 trillion part number combinations. stretched into months, unexpected price ensure signal chain optimization Xilinx • High speed edge card interconnects HIGH-SPEED CABLE increases as gold was deregulated, and Sudden Service worked, and the Gamal Refai-Ahmed They serve more than 23,000 customers, • Providing the products, tools, design are available in a variety of centerlines, multiple week deliveries for samples, company began a period of sustained, Samtec’s state-of-the-art High Speed in at least 125 countries, spanning all expertise and consulting services to from 0.50 mm to 2.00 mm. Many are were common in the industry at that time. substantial growth. In subsequent years Cable Plant, located in Wilsonville, OR, industries, from well-known global tech link high-speed signal chains between rated to 56 Gbps PAM4, in vertical, On January 2, 1976, Samtec opened Samtec successfully introduced lines of is focused on R&D and manufacturing of giants to small start-ups, and everyone in PCBs and through backplanes right angle and edge-mount orienta- for business. The business name was flexible two-piece board stacking inter- precision extruded micro coax and twinax between. By integrating specialized tech- tions, with power/signal combo pins, nology centers led by industry experts selected based on the acronym Sales and connects, micro-pitch and SMT connector • Engineer industry standard and custom- cable. Being vertically integrated allows results in over 108 trillion part number combinations. They and low-profile designs. working side-by-side, Samtec strives to Manufacturer of Technical Electronic systems, high-speed and high-bandwith ized copper and optical cable assem- Samtec to offer full system solutions, foster an environment conducive to true Components. That first year, a small connectors and cable assemblies, and blies at data rates up to 56 Gbps and HIGH SPEED CABLE ASSEMBLIES which creates design flexibility to devel- innovation and collaboration. space was rented in New Albany, Indi- more recently microelectronic intercon- beyond While Samtec has over 16 standard op products that meet strict performance ana with Sam and his wife the only two nect solutions and optical cable systems. high-speed cable assembly products, the requirements. The HSCG is aggressively HIGH SPEED BOARD-TO-BOARD majority of design challenges are solved pursuing next generation micro coax and eda 2 asic Consulting INTERCONNECTS by Samtec’s ability to mix-and-match twinax products that meet the challenges Herb Reiter Samtec is an industry leader in the either twinax or coax cables with a vari- for 56 Gbps and 112 Gbps. development and support of high speed, serve more than 23,000 customers, in at least 125 countries, high bandwidth, board-to-board interconnects. Key products include: • Mated strip connector sets on 0.50, 0.635, 0.80 mm pitch, with and without integral ground planes, in stack heights from 5 – 25 mm. Many of these products are rated at 56 Gbps PAM4, and are available in vertical, right-angle, ASE (US) Inc. spanning all industries, from global tech giants to small start-ups. and co-planar designs, in single-ended Rich Rice and differential pair designs. • High-density array connectors, in both 1.27 mm and 0.80 mm pitch grids. Samtec Microelectronics offers complete design and support for advanced packaging Samtec High-Speed Board-to-Board Interconnect Systems These products are popular because applications, including development, prototyping, and production. the open pin-field allows for maximum

12 MEPTEC REPORT SUMMER 2018 meptec.org meptec.org SUMMER 2018 MEPTEC REPORT 13 Scott Sikorski STATS ChipPAC SAMTEC

Jim Walker WLP Concepts PACKAGING PACKAGING – Copper clip interconnects have been Multichip Integrated Copper Clip Package Technology, Supports High Current DC-DC Converter Applications Special Advisors Michael-HyungMook-Choi, Kyaw Ko Lwin and Lee Smith; UTAC Group widely used in discrete MOSFET packaging from the late COPPER CLIP INTERCONNECT Figure 3, provides a forecast for the plays a critical role in DC-DC converter world-wide Power QFN market with Cop- 16 [3] power MOSFET package technology per clip interconnects . The market is Body Size [mm] Packages Area Driver to address: lower total device resistance forecasted to grow at a 17% CAGR from RDS(on), higher power density and 2016 to over 4 billion packages by 2021. Driver IC 3 x 3 8 72 mm2 high frequency switching requirements. Further market research indicates, the MOSFET 6 X 5 18 540 mm2 N-Able Group International [RDS(on) stands for “drain-source on main growth applications, require mul- 1990’s and now package assembly technology has advanced to Ron Jones resistance,” or the total resistance between tichip integration requiring more complex TOTAL PCB AREA 612 mm2 the drain and source in a Metal Oxide copper clip interconnect structures. Field Effect Transistor, or MOSFET] [1]. Figure 4a. GIGABYTE-GeForce-GTX-1080 VGA Card with Discrete MOSFET and driver IC. Potential New Applications of The copper clips replace traditional wire Integrated Copper Clip Technology bond interconnects for low voltage MOS- Figure 1. Side by side clip configuration example, 2 MOSFETs are soldered on 2 separate die FETs by providing lower interconnect attach paddles (left drawing has 1 copper clip (shaded blue) and right drawing has 2 copper Gallium nitride (GaN) is a wide band- resistance and inductance than multiple clips (shaded orange and red). gap semiconductor material with high heat wire bonds. Copper clip interconnects capacity and thermal conductivity widely have been widely used in discrete MOS- clip configuration packages. See Figure 1 used in high brightness LED applica- enable multichip integrated solutions like DrMOS (driver IC and FET packaging from the late 1990’s and (side by side clip configuration) and Fig- tions. GaN’s electrical properties of high now package assembly technology has ure 2 (stacked clip configuration). breakdown voltage and electron mobility, advanced to enable multichip integrated make it an ideal material for high power Gary Smith EDA [4] Mary Olsson solutions like DrMOS (driver IC and 2 DrMOS Application Markets: applications. Power semiconductor sup- MOSFETs). This copper clip based pack- DrMOS products are used in Synchro- pliers are developing GaN MOSFETs as age integration solution provides key nous Buck regulators which can be found a next generation power switching device to replace standard silicon MOSFETs advantages of small foot print and lower in various applications: Body Size [mm] Packages Area Driver parasitic inductance. especially for higher switching DC-DC • Desktop and Server VR buck- Figure 2. Stack clip configuration example converters. Driver IC 0 0 0 mm2 2 MOSFETs). This copper clip based package integration solution converter DrMOS (Stands for Driver + MOSFET) which has 2 MOSFETs and 2 clips (bottom One emerging GaN MOSFET applica- green and top yellow) are soldered on same • Single Phase and Multiphase point tions is for wireless charging, to enable DrMOS 6 X 5 12 360 mm2 The concept of DrMOS was suggested die attach paddle. by Intel over a decade ago [2], as CPU of load (POL) in fixed telecom the efficient transfer of power to devices TOTAL PCB AREA 360 mm2 power requirements were increasing with power supplies without the use of wires. Here an indepen- These DrMOS requirements have driv- every process generation. Intel suggested dent industry group called the Alliance for Figure 4b. GeForce-GTX-1080 EVGA card with 6 X 5 DrMOS MOSFETs (forums.evga.com). en technology advances in VR building • CPU/GPU voltage regulation in that voltage regulators (VR) that sup- Wireless Power (A4WP) was formed to blocks including the development of a low desktop and notebook Graphics port a CPU need to operate at very low Cards, DRAM DDR Memory, develop and maintain standards for a new cost, scalable multichip package platform. [5] need higher current DC-DC converters within the yellow boxed area there are18 voltages (~1V) and very high currents Graphics Memory etc. form of wireless power . The A4WP For the server market requirements, the standard differs from other wireless charg- which benefit from a larger body size MOSFETs packaged in 6 x 5mm Power provides key advantages of small foot print and lower parasitic (100+A) with fast dynamic response to package technology must enable integra- • High Power Density Voltage Regu- DrMOS 6 x 5mm QFN in the printed cir- QFN. This discrete solution consumes a meet transient voltage requirements. To ing approaches by using a relatively high tion of 2 different size MOSFETs and lator Modules (VRM) cuit board assembly (PCBA) to effectively total PCB area of 612 sq. mm for the 26 meet these new VR requirements, power frequency of 6.78 MHz. Power semi- their CMOS driver IC, into a small sur- handle the higher currents. packages. semiconductor suppliers needed to solve conductor supplies are considering GaN face mountable platform. Since PC market Figure 4a and 4b shows examples of Figure 4b shows the integrated DC-DC Honorary Advisors 3 technology challenges to meet CPU based FETs integrated with a driver IC growth had stalled, UTAC chose to focus Graphic Cards in the market with 2 dif- converter solution with 12 DrMOS in 6 X requirements in PC desktop and server and copper clip interconnects as a candi- on the DrMOS package requirements for ferent DC-DC converter solutions. Figure 5mm Power QFN, requiring only 360 sq. markets: date multichip package solution. the more challenging server market. For 4a is Geforce-GTX-1080 VGA card mm which is about 40% smaller PCB area 1. Increase power density of power servers, DrMOS packages need to enable Emerging DrMOS 6 x 5mm QFN PCBA with discrete packaged MOSFETs than the discrete solution of Fig4a requir- stages. both side by side and stacked MOSFET Electrical Spec Comparison for High and driver ICs and Figure 4b is Geforce- ing 14 less packages as the Driver IC is inductance. 2. Increase switching frequency to meet combinations which provide tool up and Current GPU Graphics Card GTX-1080 EVGA Card with DrMOS in 6 integrated in the DrMOS. faster dynamic response requirements. assembly challenges for copper clip inter- To date, the most popular DrMOS x 5mm power QFN packages. To demonstrate the electrical perfor- 3. Provide these performance advance- connects. UTAC has been qualified in Power QFN package size has been 5 x The discrete solution in Figure 4a has mance benefits of DrMOS in 6 x 5mm ments in a scalable low cost, high vol- high volume production of QFN with side Figure 3. Power QFN with Copper clip 5mm. However, emerging high-perfor- 8 Driver ICs packaged in 3 x 3mm QFN Power QFN, comparison of conventional Sunsil ume technology platform. by side clip configuration. Also with stack market. mance GPUs and bitcoin ASIC processors mounted within the red box area. Then wire bonding to copper clip interconnects Seth Alavi SUMMER 2018 meptec.org meptec.org SUMMER 2018 16 MEPTEC REPORT MEPTEC REPORT 17 UTAC GROUP Gary Catlin

Rob Cole TECHNOLOGY – The design of an ASIC is often the TECHNOLOGY Silicon Technology Selection for Implantable Medical Device ASICs

Skip Fehr Andy Kelly key to success for implantable medical device developers. IC/Systems Architect 20 Cactus Semiconductor Inc.

THE DESIGN OF AN APPLICATION g) Data converters, including analog to Specific Integrated Circuit (ASIC) is digital converters (ADCs) and digital ASICs provide the means to customize electrical designs to a often the key to success for implantable to analog converters (DACs), to Elle Technology medical device developers. ASICs pro- translate signals between the digital Anna Gualtieri vide the means to customize electrical electronics and the analog physical designs to a very specific set of require- and physiological interfaces. ments, rather than compromising those requirements based on readily available h) Data memory, including random- standard product ICs. access memory (RAM) and non- One of the most critical strategic volatile memory (NVM). decisions in the development of an ASIC very specific set of requirements. One of the most critical stra- is the selection of the silicon technology. i) Digital control logic, including Figure 1. For best results, this decision should con- a) A power source, consisting of a re- microprocessors, serial interfaces, sider multiple factors. chargeable battery, or a primary cell waveform generators, and sequenc- the features as possible into a single isolated low-voltage MOS devices to tion of a complementary pair of NMOS (non-rechargeable) battery. ers. ASIC. Based on the long list of features isolate digital control logic from sensi- and PMOS devices. For these devices, ICINTEK Implantable Medical Devices and diverging requirements included in tive analog circuits, medium-voltage the gate voltage breakdown is primarily Marc Papageorge So, what exactly is an Implantable b) A variety of power management In addition to the extensive list of typical IMDs, it is no surprise that the MOS devices for battery-voltage power a function of the gate oxide thickness Medical Device (IMD)? A condensed functions, including references, linear features, it is important to note that customization and integration of those management, and high voltage devices (between the Poly and WELL sections in version of the FDA’s definition is: “an regulators, charge pumps, and buck/ these features often have diverging features is a complex process. Figure 1 for wireless interfaces and output driv- the diagram). The drain voltage break- instrument, apparatus, or other similar boost converters. characteristics in terms of their voltages, above provides a high-level summary of ers. Not all silicon technologies support down is a function of the lateral dimen- tegic decisions in the development of an ASIC is the selection article, which is intended for use in the frequencies, and precision requirements. an example IMD system, with some of all these requirements on the same IC sions and the doping concentrations in diagnosis of diseases or conditions, or in c) Wireless interfaces that supports This makes the design of IMD electron- the ASIC details elaborated. because specialized wafer processing the WELLs and the N+ and P+ regions, the cure, mitigation, treatment, or preven- 2-way radio-frequency (RF) commu- ics very complicated, requiring a high As Figure 1 suggests, the ASIC steps are required to create the non-stan- and the threshold voltage is primarily tion of diseases”. Perhaps some examples nication and/or near-field (NF) com- degree of customization. For those rea- includes a mixture of digital and analog dard devices. Figures 2, 3 and 4 provide a function of the doping concentration might help to better describe the topic of munication between the device and sons, IMD designs often include at least functions, sensors and drivers, data con- a few common examples, based on an under the gate. this paper. Common examples of IMDs a programmer/charge device outside one application-specific integrated circuit verters, timing, and power management assumption that the reader has a basic include; Pacemakers & Defibrillators, the body, as well as wireless battery (ASIC). – with operating voltages ranging from understanding of semiconductor physics. Isolated Low-Voltage MOS Spinal Cord & Brain Stimulators, and re-charge. 1 volt to 30 volts – and all of that must Isolated low-voltage MOS devices Drug Infusion Pumps. Implantable Medical Device ASICs be integrated into a single silicon chip. Standard Low-Voltage MOS are typically based on the standard of the silicon technology. For best results, this decision should These devices typically consist of d) Timekeeping functions, which An ASIC is an integrated circuit This challenge makes the selection of the Standard low-voltage MOS devices devices but include an additional deeper a titanium enclosure containing a bat- include low-power crystal or current- (IC) that is designed specifically for the silicon technology for the ASIC a criti- are included in most CMOS technolo- n-well implant (DNWELL) to provide tery & electronic circuitry, a connector controlled oscillators, to keep track of requirements of one target application. cal decision for the overall IMD product gies. Figure 2 shows a typical cross-sec- electrical isolation of the PWELL2 from or “header” that connects the device to date and time, and provide timing ref- This is in sharp contrast to common development. In Memoriam electrical leads, and electrodes at the erences for internal functions. standard-product ICs, which are designed ends of the leads. The enclosure is typi- to fit as many different applications as Silicon Technology Selection cally implanted in the chest or abdomen, e) Multiple types of sensors to measure possible. While the features and perfor- the leads are tunneled from the device to temperature, pressure, motion, and mance of many standard-product ICs Technical Compatibility consider multiple factors. the heart, spine, or brain, and the elec- physiological signals such as electro- are impressive, they usually represent For technical compatibility, the trodes are attached to the part of the body cardiograms (EKGs) and electro- a compromise for any single applica- selected technology must include devices requiring the therapy. corticograms (ECoGs). tion. ASICs provide IMD designers with that support the various performance In terms of electronics features, most highly-integrated ICs that are customized requirements of the ASIC. For example, IMDs are characterized by a wide range f) Driver functions, such as cardiac to precisely meet their requirements. these often include standard low-voltage of diverging functions. For example, a pacing, nerve stimulation, or drug One of the primary goals for an MOS devices for low-power, high-preci- typical IMD may include: delivery. IMD ASIC is to integrate as many of sion analog sensing and data converters, Figure 2. (Courtesy of XFAB Silicon Foundries)

Bance Hom 20 MEPTEC REPORT SUMMER 2018 meptec.org meptec.org SUMMER 2018 MEPTEC REPORT 21 CACTUS SEMICONDUCTOR INC.

Contributors OPINION OPINION – Selling an infrastructure-rich manufacturing Top 4 Considerations When Disposing of an Operational Cleanroom Manufacturing Facility asset such as an operational semiconductor cleanroom SMART Microsystems Ltd. Stephen Rothrock William Boyce President & CEO ATREG, Inc. 34

SELLING AN INFRASTRUCTURE- • Assign a small, focused internal At the beginning of a fab or clean- team with a high level of authority to facility can be a difficult and time-intensive process. Over the rich manufacturing asset such as an room disposition process, companies UTAC Group operational semiconductor cleanroom manage the divestment project should have a solid understanding of Michael-HyungMook-Choi facility can be a difficult and time- current semiconductor manufacturing intensive process. Competing interests In order to further minimize the dynamics and the potential impact on from multiple stakeholders as well as potential for mixed messages, it is the demand and anticipated valuation transaction complexities can arise and important that the selling company for the manufacturing asset. In general, derail a successful divestment. Over the assigns a project team with the decision- second-hand semiconductor facilities last 17 years, ATREG has facilitated making power to control the disposition will always sell at a fraction of their many of these transactions for some of process both internally and externally. original investment. However, in a peri- last 17 years, ATREG has facilitated many of these transactions the world’s largest and most reputable od of constrained capacity, an attractive technology companies. Drawing from asset typically attains higher value than our extensive experience, we thought Carrying out a formal usual given a shortage of fab opportuni- Feldman Engineering Corp. we would share the top four critical ele- ties and multiple buyers. Conversely, Ira Feldman ments needed to ensure the successful in a down market when excess capac- disposition process sale of an operational semiconductor ity is an issue, lower fab values should manufacturing facility or cleanroom: and retaining advisors be expected. If sellers are not realistic in regard to fab value and other deal 1. GAIN CORPORATE ALIGNMENT considerations, a mutually beneficial for some of the world’s largest and most reputable technology sends a clear message transaction will be difficult to achieve. • Establish clear support within your to the market that the Prospective buyers don’t have the time BOOTH #5543 company for a particular disposition and money for belabored discussions Henkel Electronic Materials LLC strategy company is serious with unrealistic or reluctant sellers. Rose Guino It is not uncommon for various about completing a • Look at the Transaction Holistically stakeholders within a company to have differing views about the disposition transaction. The price paid for a manufacturing companies. strategy for a fab or cleanroom. The fab or cleanroom is just one component real estate group may consider the sale of the overall value of a transaction. of the site as a real estate asset, the pro- This team would be responsible for Other elements such as the supply curement team may have discussions making sure everyone within the com- agreement terms (e.g. duration, volume, with their contacts regarding the sale of pany adheres to the agreed-upon dispo- pricing), potential liabilities relieved in the tools, etc. However, if the plan is to sition strategy, while working shoulder the event of a fab shutdown, and non- N-Able Group International maximize transaction value by selling to shoulder with a trusted advisor to financial considerations such as grace- Ron Jones the semiconductor manufacturing facil- communicate a coherent message to the ful exit from the site (e.g. avoidance of ity operationally, all stakeholders must market. mass workforce layoffs) should all be be aligned. Operational buyers will be considered in calculating the overall wary about evaluating a fab opportu- 2. SET REALISTIC EXPECTATIONS value for the transaction. nity seriously if they hear rumors that • Be educated about the market and STEPHEN ROTHROCK the tools and/or real estate are being shopped separately. market dynamics continued on page 32  Andy Kelly Cactus Semiconductor Inc. 34 MEPTEC REPORT SUMMER 2018 meptec.org ATREG, INC. Kyaw Ko Lwin UTAC Group Dr. Gamal Rafai-Ahmed Xilinx 8 Coupling & Crosstalk 24 SMART Microsystems News 30 Henkel News Stephen Rothrock ATREG, Inc. DEPARTMENTS 10 Industry Insights 27 Technology Briefs 34 Opinion UTAC Group Lee Smith

MEPTEC Report Vol. 22, No. 2. Published quarterly by MEPCOM LLC, 315 Savannah River Dr., Summerville, SC 29485. Copyright 2018 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493, Fax Toll Free 1-866-424-0130.  MEMBER NEWS Infineon Prepares for Long-Term Growth with€ 1.6B  REITER NEWEST MEMBER OF MEPTEC Investment new 300-mm Chip Factory in Austria ADVISORY BOARD INFINEON TECHNOLOGIES AG IS TO ing digitization. Electric vehicles, connected build a new factory for power semiconduc- and battery-powered devices, data centers tors. The market and technology leader in or power generation from renewable sources this segment will thereby create the founda- require efficient and reliable power semicon- tion for long-term, profitable growth. A fully ductors. We recognized that trend early on and automated chip factory for manufacturing so are rapidly expanding production capacities 300-millimeter thin wafers will be constructed for 300-millimeter technology at our Dresden at the Villach location in Austria alongside the location. The new facility at Villach will help existing production facility. Austria’s Chancel- us cater for the growing demand that our cus- lor Sebastian Kurz, Dr. Reinhard Ploss, Chief tomers anticipate, and continue on our path Executive Officer of Infineon, and Dr. Sabine to success in the coming decade. Backed by Herlitschka, Chief Executive Officer of Infi- the unique expertise we have built at our loca- MEPTEC is pleased to neon Austria, presented the project in Vienna. tions in Europe, we as a global company can announce that Herb Reiter, Investments totaling around €1.6 billion are strengthen our position on the world market President of eda 2 asic planned over six years. Some 400 new jobs, long term.” Consulting, is joining the especially highly qualified ones, will be cre- Villach is the group’s competence center MEPTEC Advisory Board. ated by the new, highly efficient factory. Con- for power semiconductors and has long been After more than 20 struction is scheduled to start in the first half an important site for innovation in Infineon’s years in engineering and of 2019 and production is expected to com- production network. Manufacturing of power business development mence at the start of 2021. The additional sales semiconductors on 300-millimeter thin wafers roles at ASIC vendors and potential of the new factory, given full capacity was developed here and then expanded into EDA software companies, utilization, is put at around €1.8 billion a year. fully automated high-volume production at the Herb founded eda2asic “Global demand for power semiconductors Dresden location over the past years. Thanks Consulting, Inc. in 2002. is soaring. As the market and technology lead- to the larger diameter of the wafers, this tech- Initially he introduced er, Infineon is particularly sought-after by cus- nology delivers significant gains in productiv- tools and IP for simplifying tomers and is even growing more strongly than ity and reduces working capital. Dresden is single-die “2D-ICs” design the market,” said Dr. Reinhard Ploss, Chief Infineon’s largest site for wafer processing efforts. Executive Officer of Infineon. “Growth is (frontend) and 300-millimeter production As continued feature underpinned by global megatrends such as cli- capacities there are expected to be fully uti- ◆ size shrinking became mate change, demographic change and increas- lized by 2021. too difficult and costly for many applications, Herb started in 2008 to focus DYCONEX Opts for Automated Guided Vehicles on 2.5D and 3D-IC design, DYCONEX AG, AN MST robots have been adapted to manufacturing and test company and the world’s DYCONEX requirements and challenges. As consultant leading supplier of ultra- navigate by themselves, aided to industry organizations complex printed circuit board by a laser scanner. They react (GSA, SEMATECH, Si2, solutions, successfully tests to changes in the working ESD Alliance) Herb orga- the production use of self- environment, avoiding people nized conferences and driving transport robots with and obstacles on their own. workshops, to accelerate a view to automating internal Each vehicle calculates an building the EcoSystem goods flows between depart- optimal route to its destina- for multi-die ICs and ments and clean room zones. tion on the basis of a stored advanced packaging tech- Introduction of Automated map. The routing integrates nologies. Herb frequently Guided Vehicles (AGVs) at processes for opening doors blogs about innovation in DYCONEX marks a fur- as well as autonomous floor- this field on the 3D InCites ther step in the company’s for people to step away from to-floor transfers via goods media platform. methodical automation of operating machinery or exit lift. Vehicles communicate Herb earned an MSEE production processes. The beyond clean zones,” explains via WLAN and organize and MBA degree in Aus- AGV system’s primary task Stephan Messerli, VP of transport tasks among them- tria/EUROPE, an MBA is to transport materials Operations at DYCONEX. selves. Panels for entering from San Jose State Uni- between departments. “We The AGV system is transport orders complement versity and has attended aim to make good use of comprised of various com- the infrastructure. After a test more than 40 Continuing automation technology by ponents working closely phase lasting several months, Education Classes at relieving our staff of time- together to enable completely the AGV transport system has Stanford University. ◆ consuming transport tasks. autonomous transport from been in productive operation For example, there is no need shelf to shelf. The transport since last December. ◆

4 MEPTEC REPORT SUMMER 2018 meptec.org STATS ChipPAC Expands AEC- Q100 Qualification of eWLB for Automotive Applications Developing new STATS CHIPPAC PTE. LTD. cess in meeting the stringent medical devices? has announced the expanded AEC standards demonstrates qualification of its embed- our commitment to serve our Start with a FREE Promex ded Wafer Level Ball Grid customers across a wide range design review for reliability and Array (eWLB) technology for of automotive applications Grades 1 and 2 of the AEC- and operating conditions,” manufacturability. Q100 standards established said Cindy Palar, Managing by the Automotive Electron- Director of STATS Chip- ics Council (AEC). PAC’s Singapore operation. “Automotive devices oper- STATS ChipPAC Sin- ate in harsh environments that gapore’s qualification of require long-term, reliable AEC-Q100 Grade 1 and 2 for system operation over a wide eWLB expands the automo- temperature range. Our fac- tive capabilities for the JCET tory has been ISO/TS 16949 Group of companies. With certified for over 10 years, and automotive manufacturing we have been actively work- experience extending back ing with multiple automotive to 2005, Jiangsu Changjiang customers over the last 5 years Electronics Technology Co., to expand our eWLB quali- Ltd. (JCET) is qualified to fication. eWLB has passed the highest AEC-Q100 stan- 1000 cycles at -55/150°C for dards, Grades 0 and 1, for Unique devices often have equally unique Grade 1 qualification and met discrete and power packages. production requirements Grade 2 requirements of 1000 For more information visit cycles at -55/125°C. Our suc- www.statschippac.com. ◆ Such as not exceeding 85°C during assembly. Handling components that can’t be exposed to standard cleaning processes. Providing excellent ™ Delphon E-Film and Gel-Pak Products adhesion between surfaces for fluid processing for New Generation of Flexible Hybrid devices. Controlling voids or bubbles in organics. No matter how unique your requirements, we’ll Electronics specify the best materials and processes to ensure stable performance. DELPHON, AN INDUSTRY leader in polymer and adhe- Heterogenous assembly and packaging sive products for the elec- solutions our specialty tronics and medical indus- We understand the FDA requirements for materials tries, showcased its E-Film™ and processes needed to manufacture Class II and and Gel-Pak® device carriers Delphon provides innova- Class III devices. Along with providing complete at a special one day event on tive polymer and adhesive documentation packages. Even if all you have is Flexible Hybrid Electronics solutions to high-technology proof of concept, our engineering and materials presented by MEPTEC at the industries. For over 35 years, experience will get you to assembly of beta units, NEXTFLEX headquarters in the company has developed followed by scaling to high-volume production. Santa Clara, California. breakthrough products Delphon’s newly intro- that provide solutions for duced E-Film™ is a line of manufacturing processes If you’re responsible for fast-tracking medical polymer films that offer high in a wide range of markets. device development, designing microfluidic optical clarity, low hysteresis The company operates three devices, incorporating more sensors in a smaller and are compatible with divisions that are recognized package, or assembly in a Class 100 or Class today’s stretchable conduc- worldwide for their high- 1000 cleanroom environment: tive inks. These films are quality brands like Gel-Pak, ideal for FHE applications. UltraTape, and TouchMark. email [email protected] or call Delphon’s Gel-Pak prod- Customers from around the her at 1.408.496.0222 to ask about your free ucts protect ultra-thin die globe know that they can design review. during shipping handling and trust these brands even in the processing. These Gel-coated most critical environments. carriers are also used for die For more information promex-ind.com banking and storage. visit www.delphon.com. ◆

meptec.org SUMMER 2018 MEPTEC REPORT 5 Kyocera to Build New Plant in Kagoshima, Japan, for Ceramic Microelectronic Packages New facility will produce ceramic packages for electronic and semiconductor components, including SMD and CMOS devices, to support IoT growth 1-800-776-9888 total production capacity for ceramic packages used to house SMD electronic devices and CMOS image sensors. Kyocera’s heritage is rooted in ceramics - the company’s name is derived from Kyoto and ceramic. In 1959, Kyocera began manufacturing ceramic insulators for TV picture tubes and later became the world leader in fine (advanced) ceramics, producing electronic compo- KYOCERA CORPORATION HAS nents, semiconductor process compo- announced that it will construct a new nents, and parts for LCDs and LEDs, manufacturing plant on the premises among other applications. of its Kagoshima Sendai manufactur- The electronics industry is now expe- ing complex to increase production of riencing new growth fueled by big data, ceramic microelectronic packages. The artificial intelligence, and the Internet company entered into a site location of Things (IoT). The development of agreement with local governments, and advanced driver-assist systems (ADAS) a signing ceremony was held March and technology that supports minimally 16 at the Satsumasendai municipal invasive medical treatments will drive office in the presence of the governor of future growth as well. The new Sendai Kagoshima Prefecture and mayor of Sat- facility will significantly increase Kyo- sumasendai. Construction is scheduled cera’s production capacity for two key to begin in April 2018 for the new plant, enablers of these applications — SMD which will be the 22nd facility at Kyoc- ceramic packages and packages to house era’s Kagoshima Sendai manufacturing CMOS image sensors — as well as complex. ceramic packages for automotive and The new facility, which Kyocera medical devices. plans to open in August 2019, will bring Visit global.kyocera.com for more a 25 percent increase in the company’s information. ◆

ASE Breaks Ground on K25 Factory Building in Kaohsiung, Taiwan

automation, intelligent manufacturing processes and smart logistics. K25 will have a total of 355, 800 square feet of floor space that will be used to research, develop and manufacture advanced semiconductor chips in applications for IoT, robotics, data science, artificial intelligence, self driving vehicles, high end graphics and more. The design and The ASE Group broke ground April layout of building K25 has been care- 3rd on its latest factory building – K25, fully planned using local and global located in the Nantze Export Processing green standards, fulfilling the company’s Zone 2 in Kaohsiung, Taiwan. The build- commitment to corporate sustainability. ing is scheduled to be completed in the The ground breaking ceremony was year 2020 and is expected to create more officiated by Chen Chu, Mayor of Kaoh- than 1800 job opportunities. siung and Jason Chang, Chairman and The K25 building will be ASE’s state CEO of ASE. of the art facility with a high degree of Visit www.aseglobal.com for more. ◆

6 MEPTEC REPORT SUMMER 2018 meptec.org SCW18 MEPTEC_203x267mm_PQ.pdf 1 4/16/18 12:02 PM COLUMN

lot of work to be done in a short time: This logical and “simple” add more COUPLING & demolition of the existing kitchen, than doubled the scope of the overall assembling and installing a garage full project compared to a simple kitchen CROSSTALK of IKEA cabinets, In house staff - my remodel. The cost of the repipe was By Ira Feldman spouse and children, my parents, and my a contingency in the budget from the brother’s family - all pitched in. How- beginning since as a good project man- ever, we also needed to hire and sched- ager I knew not to confuse the headline Electronic coupling is the transfer of ener- ule professionals for floor refinishing, with the detailed project definition. And gy from one circuit or medium to another. drywall, plumbing, counter tops, and tile the need to repipe reminded me of the Sometimes it is intentional and sometimes setting. Of course, acting as the “Gen- importance of proper building and not (crosstalk). I hope that this column, by eral Contractor”, – i.e. project manager maintaining of infrastructure. mixing technology and general observa- – yours truly got involved in contracts, Plumbing, like many other types of tions, is thought-provoking and “couples” insurance, permits, inspections, and infrastructure, is out of sight and out of with your thinking. Most of the time I will (gasp) legal not to mention risk manage- mind until it no longer functions prop- stick to technology but occasional cross- ment, scheduling, and accounting. erly. More likely than not a catastrophic talk diversions may deliver a message event announces the failure of this criti- closer to home. • DOCUMENT AND PLAN THE cal infrastructure. And to make matters ENTIRE PROJECT BEFORE worse, I hate plumbing! What is more Project Management- STARTING. Building permits were the maddening than a confusing array of starting point and we knew that we had “(non-)standard” part types is that a What Me Worry? to purchase and install the cabinets and plumbing connection looks good now but appliances all at once rather than one at in hours or days may start leaking. Even  ALFRED E NEUMAN’S FAMOUS a time. Here is where it became interest- the work of experienced and licensed “What me worry?” quote should always ing... plumbers has needed after-the-fact be in your thoughts at the optimistic Our house is just over fifty-years old, “adjustments” due to leaks. beginning of any project. As reality kicks so planning the kitchen remodel was Infrastructure of all types has a cost to in and the project grinds on-and-on you a mix of architecture, archeology, and implement and maintain. And since infra- will finally start remembering Andy reverse engineering. As we poked and structure is often ignored – both profes- Rooney’s somber, pragmatic quotes. prodded during the planning and demoli- sionally and personally – maintenance is Project success will depend on your tion, we became archeologists when we not regularly performed and the cost to team’s ability to realistically control found remnants of prior improvement repair / replace is not often obvious. In enthusiasm and expectations while work. Everything from original linoleum the case of plumbing, the issues may not minimizing the disruptions to ongoing (still tough as nails fifty years later) to become obvious until the work is under- operations. layers-upon-layers of old wall paper (of way. Being a do-it-yourselfer humbly questionable taste even when originally The repiping was added to our offi- reminds me that many of life’s lessons installed). And, reverse engineering to cial plans and budget but we then were are applicable both personally and pro- figure out why things were done a certain exposed to a third sage: Murphy! The fessionally. On a bigger project like our way and the purpose of mysterious wires one whose law will mess up anyone’s currently underway kitchen remodel, the and fittings. project estimate. family team clearly started with Alfred’s We knew that our water main was “What me worry?” approach as we • DEFINE REALISTIC SCOPE OF also galvanized but we took steps to drooled over magazine pictures. Switch- PROJECT. We decided to dramati- avoid “touching it” during the repipe in ing to my consultant’s hat I started to cally expand the scope of this project for the hope of avoiding cracking it. Howev- address “reality” with the following suc- peace of mind and to avoid exorbitant er, to our surprise just the act of pressur- cess factors: future costs... Our house was plumbed izing / depressurizing the main was suf- with galvanized steel pipes and we have ficient to have it rupture under the drive- • DON’T DISRUPT ONGOING reached the upper end of the maximum way about sixty feet from the house. And OPERATIONS. Simply put, we needed service life of approximately fifty years. even though we knew the main valve at to have meals throughout the project: i.e., So, we decided that since the walls our house wasn’t closing fully we shortly refrigerator, stove, and sink had to be would be open it would be best (cost- discovered that the city shutoff was also operational at all times. effective) to replace our plumbing and broken. It was good that we chose to water heater at the same time. Especially repipe since we would have had no abil- • ESTABLISH PRELIMINARY since several of our neighbors have had ity to quickly shut off the water from BUDGET. We switched our reading to deal with similar-aged broken pipes in an unexpected burst pipe… Needless to from House Beautiful to the IKEA cata- the middle of the night requiring emer- say the broken water main was not only log. Even then, we had concerns that gency repairs followed by repiping the a mess, it doubled the cost and time for infrastructure costs (more on this later) entire house with copper supply lines. completing the infrastructure repairs. Not would dwarf the cost of cabinets. Our pipes had become occluded due to only did it tax my project management rust and sediment build up over time skills, it had me doing a very dour Andy • ASSEMBLE AND SUPERVISE A resulting in low water pressure… Think Rooney impersonation. COMPETENT TEAM. There was a rusty arteriosclerosis. When running over budget or encoun-

8 MEPTEC REPORT SUMMER 2018 meptec.org tering large surprises in scope, it is far One of the few areas to fully consider to keep things running is essential to easier to deal with corporate versus service life is in residential condomini- any business. And as always, my DIY personal projects. A well-managed com- ums where significant reserves to fund project has provided more insight into pany will redefine, delay, or simply the majority of the replacement cost project management and the importance cancel a project that no longer has the of infrastructure are required. In many of infrastructure. I hope “all’s well that proper return on investment (ROI). states, condo associations are required by ends well” and that we will be finished And if the ROI is still acceptable, the law to rate the service life of each major shortly. company typically has the wherewithal item and put a proportionate amount For more of my thoughts, please see to allocate additional funding. Individu- of money into the bank each month for my blog http://hightechbizdev.com. als are likely to succumb to the fallacy of the item’s upkeep. Yes, there may be As always, I look forward to hearing sunk costs, because there is a high degree other unexpected surprises when mak- your comments directly. Please contact of attachment to our homes and a high ing repairs or dealing with an issue, but me to discuss your thoughts or if I can be transactional cost to moving. In the end, the good news is if the association is run of any assistance. ◆ most home projects need to be completed correctly a significant amount of required once started and the homeowner borrows funding is available. Unfortunately, the money if not readily available. this mode of thinking is not typically IRA FELDMAN is the Principal Why our house and many others were employed by corporations, governments, Consultant of Feldman Engineering built in the 1940-60’s with galvanized or individuals. For me? Let’s discuss it Corp. which guides high technology pipes in the first place remains a mystery after I’m done paying for this project… since the issues we had were known So meanwhile let us add to the success products and services from concept shortcomings at that time. The only thing factor list: PREPARE FOR MURPHY! to high volume manufacturing. He we can attribute this to is greed on the As glamorous and fun new product engages on a wide range of projects part of the builders and lack of knowl- introduction (NPI) is with all the chal- including technical marketing, prod- edge or caring on the home buyers of lenges of ramping up new products, the uct-generation processes, supply- that era. And if any of the parties thought supporting or continuing engineers about it, they probably decided that who maintain the existing products chain management, and business deferring the problem 25 to 50 years was and factory infrastructure should development. fine since they were likely to be someone receive more recognition for their ([email protected]) else’s problem. contributions. Successfully managing

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meptec.org SUMMER 2018 MEPTEC REPORT 9 COLUMN

The primary goal of the Responsible • Metrics that are practical, objective, INDUSTRY Brands Initiative (RBI) is to establish a demonstrable and significant. framework for objectively communicat- INSIGHTS ing corporate social responsibility and • Metrics that encompass most tenets By Ron Jones sustainability information in a standard- of Corporate Social Responsibility ized fashion between companies and and Sustainability. consumers. RBI is a 501(c)(6) nonprofit and is independent of individual corpora- • A rubric that weights various aspects Simplifying tions, governments and non-government of CSR into a meaningful “overall Consumer Selection organizations. view.” Companies that fulfill the require- of Responsibly ments for “Responsible Brands” cer- • No requirement that a company be tification will be authorized to use the perfect and no blackballs that pre- Sourced Products “Responsible Brands Logo” to communi- clude certification. cate their CSR status and commitment to  FOR YEARS, MUCH HAS BEEN consumers, investors and others. • No criteria that are political or per- publicized about “sweat shop” working Consumers can be confident that sonal in nature e.g. support for or conditions in manufacturing environ- companies displaying the “Responsible against abortion. ments around the world. In recent years, Brands Logo” have met an objective set there has been significant press on “blood of criteria to qualify as a “Responsible • Criteria that reflects support for the diamonds” and “conflict minerals” Brands” company and are doing their “spirit” of responsible sourcing and which may be mined or sourced using part to make the world a better place. efforts that go “above and beyond” inhumane practices including slavery, The Responsible Brands Initiative minimum requirements. unsafe work environments, sexual abuse will: and child labor. These practices are not • Inertia and persistence of certification limited to Africa, but impact people on • Work with a broad range of corpora- that is minimally responsive to “cur- every inhabited continent. There are also tions and organizations to develop rent events.” widespread concerns about the impact of metrics and policies that define industrialization and over harvesting on the criteria for a company to receive • Recognition as being Responsible the environment of our planet. “Responsible Brands” certification. Brands compliant . . . not a ranking Over the past several decades, manu- like J.D. Powers. facturing supply chains have gone from • Establish an independent and respect- more local in nature (think Detroit) to ed board of directors to provide over- • Some level of detail about the certifi- global . . . driven by factors such as the sight and guidance to the initiative. cation scorecard. desire for lower cost labor, requirements for exotic materials and the increasing • Establish advisory boards to provide • A focus on corporate CSR environ- complexity of distributing finished prod- inputs in specific areas. ment, policies and actions, not indi- ucts to end markets. While this globaliza- vidual products or services. tion has raised the standard of living for • Develop a branding program that fea- many people, it has raised the possibility tures a recognizable “Responsible The success of the Responsible of abuse by unethical actors. Brands Logo” for use by companies Brands Initiative will require the involve- Companies around the globe are that are certified as “Responsible ment of myriad people and entities. If investing money, time and effort to Brands” compliant. you, your company or your organization assure their supply chains operate ethi- would like to get involved, please follow cally, humanely and with transparency. • Encourage participation by public and the link to http://responsiblebrands.org/ Many companies have teams of people private companies of all sizes. contact/ focused on myriad aspects of Corporate We hope to hear from you soon! ◆ Social Responsibility (CSR) and Sustain- • Instill confidence so that consumers ability. The breadth of topics covered can trust companies displaying the by the CSR umbrella continues to grow, “responsible brands logo” without RON JONES is CEO of N-Able Group driven in part by customer and inves- having to understand the underlying International; a semiconductor focused tor expectations as well as government details. consulting and recruiting company. N-Able requirements and regulations. Group utilizes deep semi supply chain For all this investment by industry, • Provide education that both informs knowledge and a powerful cloud based most consumers don’t know which consumers and motivates them to software application to provide Conflict brands have responsible supply chains improve the world through their Mineral Compliance support services to and corporate operating policies. Many responsible purchasing decisions. companies throughout the semiconductor consumers would like to make the supply chain including fabless, foundry, “right” choice of buying responsibly The criteria for certification as OSAT and materials suppliers. Email sourced products, yet obtaining informa- Responsible Brand compliant should [email protected] for more info. tion to make that decision can be elusive. include:

10 MEPTEC REPORT SUMMER 2018 meptec.org 2018

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Samtec’s Corporate Headquarters in New Albany, IN, USA

MICROELECTRONICS INTERCONNECT SOLUTIONS

QUICK HISTORY employees. FOUNDED IN 1976, Samtec is a privately In the mid-1970s, Sam Shine was The company’s business model was held, $713 million global manufacturer Vice President of Sales and Marketing for “Sudden Service.” Simply put, the goal of a broad line of electronic interconnect a mid-sized connector company that was was to deliver quality products with the solutions. Samtec is headquartered in New Albany, Indiana. Their global reach riding a wave of increased demand and best customer service in the industry. At includes over 5,000 employees with 33 had decided to become a major player the time, Sudden Service principals were: locations in 24 countries. Manufacturing in the market by going public. Pleasing • Quick turn-around of orders, large is performed in 12 different locations: stock holders with growth at any cost and small became the work of the day. As automat- New Albany, IN; Scottsburg, IN; Colo- • Quick delivery of samples rado Springs, CO; Wilsonville, OR; Costa ed production processes became increas- Rica; Huizhou China; Dongguan, China; ingly inflexible, Shine became increas- • Quick delivery of catalogs Johor, Malaysia; Penang, Malaysia; Tai- ingly frustrated, feeling the company was • Prompt, correct answers to technical wan, Singapore and Vietnam. losing its ability to service customers. and order status inquiries Samtec has more than 600 sepa- Large minimum order quantities, • Consistent follow-through on all rate product series which results in over long delivery lead times that sometimes shipments 108 trillion part number combinations. stretched into months, unexpected price They serve more than 23,000 customers, increases as gold was deregulated, and Sudden Service worked, and the in at least 125 countries, spanning all multiple week deliveries for samples, company began a period of sustained, industries, from well-known global tech were common in the industry at that time. substantial growth. In subsequent years giants to small start-ups, and everyone in On January 2, 1976, Samtec opened Samtec successfully introduced lines of between. By integrating specialized tech- for business. The business name was flexible two-piece board stacking inter- nology centers led by industry experts selected based on the acronym Sales and connects, micro-pitch and SMT connector working side-by-side, Samtec strives to Manufacturer of Technical Electronic systems, high-speed and high-bandwidth foster an environment conducive to true Components. That first year, a small connectors and cable assemblies, and innovation and collaboration. space was rented in New Albany, Indi- more recently microelectronic intercon- ana with Sam and his wife the only two nect solutions and optical cable systems.

Samtec High-Speed Board-to-Board Interconnect Systems

12 MEPTEC REPORT SUMMER 2018 meptec.org KEY PRODUCTS AND TECHNOLOGIES SILICON-TO-SILICON Samtec’s history is a manufacturer of high speed board-to-board interconnects and cable systems, and of having the industry’s largest variety of two-piece board stacking connector products. In the last decade Samtec’s Silicon- to-Silicon business model continues to distinguish and define Samtec. Simply put, Silicon-to-Silicon capabilities assist designers in optimizing the high-speed serial path from bare die, to IC package and assembly, to PCB, to connectors, to cable assemblies, and back again. These capabilities include: • Assisting IC layout designers to opti- mize power and signal integrity of the bare die during the IC design process • Developing complex, customized IC packaging and assembly solutions Samtec’s High-Speed Cable Assemblies enabling maximum IC density, precision and ruggedness grounding and routing flexibility. They ety of high-speed interconnects, in either • Enabling PCB designers to create dens- are available with up to 560 I/Os, with single ended 50 Ω or 100 Ω differential er, faster PCBs by providing factory stack heights up to 40 mm, with option- pairs, across a variety of centerlines and and field-based technical support to al power modules. configurations. ensure signal chain optimization • High speed edge card interconnects HIGH-SPEED CABLE • Providing the products, tools, design are available in a variety of centerlines, Samtec’s state-of-the-art High Speed expertise and consulting services to from 0.50 mm to 2.00 mm. Many are Cable Plant, located in Wilsonville, OR, link high-speed signal chains between rated to 56 Gbps PAM4, in vertical, is focused on R&D and manufacturing of PCBs and through backplanes right angle and edge-mount orienta- tions, with power/signal combo pins, precision extruded micro coax and twinax • Engineer industry standard and custom- and low-profile designs. cable. Being vertically integrated allows ized copper and optical cable assem- Samtec to offer full system solutions, blies at data rates up to 56 Gbps and HIGH SPEED CABLE ASSEMBLIES which creates design flexibility to devel- beyond While Samtec has over 16 standard op products that meet strict performance high-speed cable assembly products, the requirements. The HSCG is aggressively HIGH SPEED BOARD-TO-BOARD majority of design challenges are solved pursuing next generation micro coax and INTERCONNECTS by Samtec’s ability to mix-and-match twinax products that meet the challenges Samtec is an industry leader in the either twinax or coax cables with a vari- for 56 Gbps and 112 Gbps. development and support of high speed, high bandwidth, board-to-board interconnects. Key products include: • Mated strip connector sets on 0.50, 0.635, 0.80 mm pitch, with and without integral ground planes, in stack heights from 5 – 25 mm. Many of these products are rated at 56 Gbps PAM4, and are available in vertical, right-angle, and co-planar designs, in single-ended and differential pair designs. • High-density array connectors, in both 1.27 mm and 0.80 mm pitch grids. Samtec Microelectronics offers complete design and support for advanced packaging These products are popular because applications, including development, prototyping, and production. the open pin-field allows for maximum meptec.org SUMMER 2018 MEPTEC REPORT 13 PROFILE

SAMTEC MICROELECTRONICS - Solder ball attach for tight spaces create custom circuits on a glass sub- The Microelectronics Group, one downs to 0.4 mm strate. RDL’s unique thin-film process of Samtec’s six Technology Centers, is enables circuit formation on glass sub- - Lid attach with AuSn solder, glass located in Colorado Springs, CO. SME strates. This provides for low loss fan- frit, hermetic, fluidic, optical and offers complete design and support out of chip and package interconnects, custom materials for advanced packaging applications, and lower cost compared to traditional including development, prototyping, and Technologies currently in development silicon-based interposers. production. Core packaging capabilities include: Glass Core Technology has at its include: basis the capability to provide engineer- • Thermocompression die bonding (e.g., ing solutions for connectivity, biomedi- • Precision Die Placement: high-speed, flip chip, copper pillar, gold stud bump) cal, MEMS & Sensors, Optics & Photon- high accuracy die placement to +/- 3 ics, and hermetic packaging platforms. microns • Gold stud bumping Glass Core Technology uses borosilicate • Wire Bonding: Ultra-fine pitch, ultra- • Transfer molding – conventional and glass, fused silica, quartz, sapphire, and low profile ball bond, wedge bond, or optically clear mold compounds zirconia. ribbon bond • Silicon photonics and optics with Glass Core Technology is a strong candidate for use in RF applications • Fine Pitch Flip Chip & Jet Underfill: ultra-tight tolerances because of its excellent electrical insu- Ultra-high bump count; tight keep-out Glass Core Technology (GCT) is a lation, low dielectric constant, high regions between die new technology which is garnering tre- hermeticity, low warpage, and high resis- • Encapsulation: Encapsulating with dam mendous interest. Samtec’s proprietary tance to corrosion. and fill, glob top or transfer molding Glass Core Technology process lever- With today’s laser processing tech- ages the performance benefits of glass nology, GCT can address packaging • Advanced Packaging and Assembly: to enable performance optimized, ultra- solutions like high speed RF interpos- - Advanced substrates, inspection and miniaturized substrates for next genera- ers, microstructured glass substrates for metrology tion designs. biomedical applications, and electro- - Glass substrate manufacturing, fan GCT is a proprietary process that optical package integration. The pres- out technology leverages the performance benefits of ence of laser technologies is found in glass by creating small diameter, fine glass micromachining, room temperature - 2.5D / 3D TxV technology pitch Through-Glass Vias (TGV) that are bonding of glass to silicon and glass- - Wafer dicing with 2”– 8” capabilities, metalized and hermetically sealed. The to-glass, and formation of microfluidic subcontract 12” wafers, and thick- TGVs are linked via a unique thin film channels. nesses down to 25 µm Redistribution Layer (RDL) process to Glass has proven to be a key enabling

Glass substrates offer high structural integrity, resistance to vibration and temperature, environmental ruggedness, and low electrical loss.

14 MEPTEC REPORT SUMMER 2018 meptec.org SAMTEC OPTICAL GROUP 48 pairs (up to 84 differential pairs per The Samtec Optical Group designs, linear inch), with integrated power, develops, and provides application sup- guidance, keying and end walls avail- port of high-performance micro optical able. engines, active optical assemblies, and • ExaMAX® enables 56 Gbps electrical passive optical panel solutions. performance on 2.00 mm column pitch. The flagship optical product is the It meets industry specifications such FireFly™ cable system. Samtec’s FireFly™ as PCI Express®, Intel OPI and UPI, Micro Flyover™ System is the first inter- SAS, SATA, Fibre Channel, Infini connect system that gives designers the Band™ and Ethernet, and it meets and flexibility of using micro footprint optical exceeds OIF CEI-28G-LR specifica- Samtec has the industry’s only proven and copper interconnects interchangeably process for metallization and hermetic tion for 28 Gbps standards. A direct- with the same PCB connector system. sealing of ultra-high density Through mate orthogonal eliminates the need The FireFly system enables chip-to-chip, Glass Vias, which enables extreme for a backplane/midplane and shortens board-to-board, on-board and system-to- miniaturization, integration, and high- the signal path for improved signal performance. system connectivity at data rates up to 28 integrity. Gbps. FireFly™ is based on a high-performance interconnect system which allows FLEXIBLE STACKING BOARD-TO- the use of high performance active opti- BOARD cal engines or low-cost copper cables. Samtec is the industry leader in board The Optical Micro Flyover™ Cable stacking interconnect systems. Samtec assembly is available in x4 and x12 has the largest and most flexible product designs, in 14, 16, and 28 Gbps. The offering of two-piece board stacking ETUO Extended Temperature FireFly connector systems in the industry. Put achieves a rugged -40°C to +85°C another way, Samtec has more ways to range for more rugged applications. End stack two or more boards together than options include MPO (MTP), MT, MXC, any other connector company. and ARIB. A PCIe-over-fiber system Circuit patterning on glass. transmits PCIe signals at Gen 3 data MICRO RUGGED INTERCONNECTS transfer rates through optical cable up to Micro rugged systems include micro 100 meters. pitch board-to-board, cable-to-board, technology for advanced packaging plat- and cable-to-cable interconnect systems. forms. RF These products incorporate rugged fea- Glass interposers are beneficial for Samtec boasts a complete line of tures to increase the mating retention of connectivity products that have RF, RF interconnects and cable assemblies, the interconnect system, provide robust mmWave, Bluetooth Low Energy devices including: mechanical strength of the interconnect to and used by telecommunication, defense, • High-performance test systems to the PCB, being able to withstand extreme and Internet of Things companies. 50 GHz conditions and application environments, Microstructured glass substrates are and accommodating high cycles. beneficial as a platform for biomedical • Precision RF systems, with a roadmap Visit www.samtec.com for more about sensors, Lab-on-Chip, and microfluidic to 65 GHz Samtec products and services. ◆ devices used by the healthcare and medi- • 75 Ω cables and connectors, including cal technology industry. the industry’s largest variety of 12G Hermetic glass packages are extreme- QUALITY AND COMPLIANCE SDI product – BNC, HD-BNC, and ly important for moisture- and particle- Samtec is TS 16949, IATF 16949, DIN 1.0/2.3 sensitive technologies like CMOS ISO 9001 certified. Sampling proce- Image Sensors and are used by imaging, • 50 Ω cables and connectors dure is ANSI/ASQ Z1.4. Samtec machine vision, and camera companies. • Unmatched service and support maintains numerous UL recognitions. MEMS platforms are used in 2.5D All other certifications, reports, re- and heterogeneous integration, where HIGH-SPEED BACKPLANE source, general quality informa- different chip types are combined on a INTERCONNECTS single substrate and are used by Internet tion, environmental initiatives and High-speed backplane systems of Things and sensor companies. compliance, safety compliance and include: Finally, optical and photonics integra- documentation, and third party ICP tion with electronic devices can truly • XCede HD® is a small form-factor and test results, can be found on the benefit from incorporating glass elements modular design which provides sig- company’s website at www.samtec. within the light path of the resulting nificant space-savings and flexibility. com/support/compliance. package. On 1.80 mm column pitch, with up to meptec.org SUMMER 2018 MEPTEC REPORT 15 PACKAGING

Multichip Integrated Copper Clip Package Technology, Supports High Current DC-DC Converter Applications

Michael-HyungMook-Choi, Kyaw Ko Lwin and Lee Smith; UTAC Group

COPPER CLIP INTERCONNECT plays a critical role in DC-DC converter power MOSFET package technology to address: lower total device resistance RDS(on), higher power density and high frequency switching requirements. [RDS(on) stands for “drain-source on resistance,” or the total resistance between the drain and source in a Metal Oxide Field Effect Transistor, or MOSFET] [1]. The copper clips replace traditional wire bond interconnects for low voltage MOS- Figure 1. Side by side clip configuration example, 2 MOSFETs are soldered on 2 separate die FETs by providing lower interconnect attach paddles (left drawing has 1 copper clip (shaded blue) and right drawing has 2 copper resistance and inductance than multiple clips (shaded orange and red). wire bonds. Copper clip interconnects have been widely used in discrete MOS- clip configuration packages. See Figure 1 FET packaging from the late 1990’s and (side by side clip configuration) and Fig- now package assembly technology has ure 2 (stacked clip configuration). advanced to enable multichip integrated solutions like DrMOS (driver IC and 2 DrMOS Application Markets: MOSFETs). This copper clip based pack- DrMOS products are used in Synchro- age integration solution provides key nous Buck regulators which can be found advantages of small foot print and lower in various applications: parasitic inductance. • Desktop and Server VR buck- Figure 2. Stack clip configuration example converter DrMOS (Stands for Driver + MOSFET) which has 2 MOSFETs and 2 clips (bottom green and top yellow) are soldered on same • Single Phase and Multiphase point The concept of DrMOS was suggested die attach paddle. by Intel over a decade ago [2], as CPU of load (POL) in fixed telecom power requirements were increasing with power supplies These DrMOS requirements have driv- every process generation. Intel suggested en technology advances in VR building • CPU/GPU voltage regulation in that voltage regulators (VR) that sup- blocks including the development of a low desktop and notebook Graphics port a CPU need to operate at very low cost, scalable multichip package platform. Cards, DRAM DDR Memory, voltages (~1V) and very high currents For the server market requirements, the Graphics Memory etc. (100+A) with fast dynamic response to package technology must enable integra- • High Power Density Voltage Regu- meet transient voltage requirements. To tion of 2 different size MOSFETs and lator Modules (VRM) meet these new VR requirements, power their CMOS driver IC, into a small sur- semiconductor suppliers needed to solve face mountable platform. Since PC market 3 technology challenges to meet CPU growth had stalled, UTAC chose to focus requirements in PC desktop and server on the DrMOS package requirements for markets: the more challenging server market. For 1. Increase power density of power servers, DrMOS packages need to enable stages. both side by side and stacked MOSFET 2. Increase switching frequency to meet combinations which provide tool up and faster dynamic response requirements. assembly challenges for copper clip inter- 3. Provide these performance advance- connects. UTAC has been qualified in ments in a scalable low cost, high vol- high volume production of QFN with side Figure 3. Power QFN with Copper clip ume technology platform. by side clip configuration. Also with stack market.

16 MEPTEC REPORT SUMMER 2018 meptec.org Figure 3, provides a forecast for the world-wide Power QFN market with Cop- [3] per clip interconnects . The market is Body Size [mm] Packages Area Driver forecasted to grow at a 17% CAGR from 2016 to over 4 billion packages by 2021. Driver IC 3 x 3 8 72 mm2 Further market research indicates, the MOSFET 6 X 5 18 540 mm2 main growth applications, require multichip integration requiring more complex TOTAL PCB AREA 612 mm2 copper clip interconnect structures. Figure 4a. GIGABYTE-GeForce-GTX-1080 VGA Card with Discrete MOSFET and driver IC. Potential New Applications of Integrated Copper Clip Technology Gallium nitride (GaN) is a wide band- gap semiconductor material with high heat capacity and thermal conductivity widely used in high brightness LED applications. GaN’s electrical properties of high breakdown voltage and electron mobility, make it an ideal material for high power applications. [4] Power semiconductor suppliers are developing GaN MOSFETs as a next generation power switching device to replace standard silicon MOSFETs Body Size [mm] Packages Area Driver especially for higher switching DC-DC converters. Driver IC 0 0 0 mm2 One emerging GaN MOSFET applications is for wireless charging, to enable DrMOS 6 X 5 12 360 mm2 the efficient transfer of power to devices TOTAL PCB AREA 360 mm2 without the use of wires. Here an independent industry group called the Alliance for Figure 4b. GeForce-GTX-1080 EVGA card with 6 X 5 DrMOS MOSFETs (forums.evga.com). Wireless Power (A4WP) was formed to develop and maintain standards for a new form of wireless power [5]. The A4WP need higher current DC-DC converters within the yellow boxed area there are 18 standard differs from other wireless charg- which benefit from a larger body size MOSFETs packaged in 6 x 5mm Power ing approaches by using a relatively high DrMOS 6 x 5mm QFN in the printed cir- QFN. This discrete solution consumes a frequency of 6.78 MHz. Power semi- cuit board assembly (PCBA) to effectively total PCB area of 612 sq. mm for the 26 conductor supplies are considering GaN handle the higher currents. packages. based FETs integrated with a driver IC Figure 4a and 4b shows examples of Figure 4b shows the integrated DC-DC and copper clip interconnects as a candi- Graphic Cards in the market with 2 dif- converter solution with 12 DrMOS in 6 X date multichip package solution. ferent DC-DC converter solutions. Figure 5mm Power QFN, requiring only 360 sq. 4a is Geforce-GTX-1080 VGA card mm which is about 40% smaller PCB area Emerging DrMOS 6 x 5mm QFN PCBA with discrete packaged MOSFETs than the discrete solution of Figure 4a Electrical Spec Comparison for High and driver ICs and Figure 4b is Geforce- requiring 14 less packages as the Driver Current GPU Graphics Card GTX-1080 EVGA Card with DrMOS in 6 IC is integrated in the DrMOS. To date, the most popular DrMOS x 5mm power QFN packages. To demonstrate the electrical perfor- Power QFN package size has been 5 x The discrete solution in Figure 4a has mance benefits of DrMOS in 6 x 5mm 5mm. However, emerging high-perfor- 8 Driver ICs packaged in 3 x 3mm QFN Power QFN, comparison of conventional mance GPUs and bitcoin ASIC processors mounted within the red box area. Then wire bonding to copper clip interconnects meptec.org SUMMER 2018 MEPTEC REPORT 17 PACKAGING

is illustrated in the following figures and electrical parameter simulations table. For simulation purposes, a low side MOSFET die is fixed at 2.9 x 4.0mm which is close to the max die size of 6 x 5mm Power QFN MOSFET. Copper wire is 2mil (50µm diameter) and copper clip thickness is 10mil (250µm). Figure 5a shows MOSFET die (pink perimeter) is attached on top of the lead frame (gray) and 22 copper wire bonds Figure 5a. Copper wire interconnect and bonding diagram views. are required to connect the MOSFET die to package leads on the left side. The figure on the right is the top side view to better show MOSFET die pads and copper wire interconnects. The MOSFET die has 6 separate source pads (marked as S), the 2 small pads on the left side of the die require 3 wires each and 4 large pads require 4 wires each for total source copper wire count of 22 wires. Figure 5b shows that higher copper wire bond interconnect density is required to achieve the electrical performance for a MOSFET designed for higher switch- Figure 5b. Copper wire interconnect and bonding diagram view of fast switching MOSFET. ing speeds. Here 9 source pads (marked S) are required for faster switching, each pad requires 3 wires for a total of 27 eter simulation comparison between cop- nH and 0.076nH with wire bonding and wires. One can envision how 1 copper per wire bond interconnection shown in 0.044nH with copper clip technology, near- clip is a more efficient solution provid- Figure 5a and 5b, vs copper clip intercon- ly a 50% reduction in package inductance. ing improved cost and performance vs 27 nection shown in Figure 6. Resistance val- UTAC Copper Clip Based Power QFN wire bonds. ues of Figure 5a using copper wire bond Offerings Figure 6 shows the copper clip interconnects is 0.46m ohm and the faster As shown in Table 2, UTAC is in pro- interconnect structure for the standard switching design Figure 5b is 0.37m ohm duction with various Power QFN sizes MOSFET shown in Figure 5a. Here the which is around 20% lower due to use with copper clip interconnects. Both gold MOSFET die is fully covered by the inter- of 5 more source wires. However, with a (Au) and gold / palladium / copper (AuP- connect of a copper clip. The soldered copper clip interconnect, the resistance is dCu) wires are used for Driver IC interconnection of copper clip to the MOSFET 0.047m ohm which is about 90% lower connect based on the customer’s require- die provides reduced interconnect contact resistance than copper wire bond due to ments. These products support different resistance. The copper clip structure pro- the higher thickness of the copper clip and copper clip configurations including: vides a significant reduction for package larger areas of contact to the MOSFET die resistance and inductance compared with and Power QFN leads. • Stack clip structure (MOSFETs the copper wire bond shown in Figure 5a. The inductance values of the intercon- and copper clips are vertically Table 1 provides the electrical param- nect technology are simulated at 0.084 stacked together)

Figure 6. Copper clip MOSFET die on lead frame and copper clip attachment and clip bonding diagram.

18 MEPTEC REPORT SUMMER 2018 meptec.org • Side by side copper clip structure Resistance Inductance (MOSFETs are attached on 2 dif- Material Dimension (mΩ) (nH) Remarks ferent leadframe die attach pads Copper Parasitic value includes (DAP) with separate copper clips 50 µm x 22 wires 0.46 0.084 attached. This configuration iso- Wire (5a) wires and leads lates the low side MOSFET and Copper 0.37 0.076 Parasitic value includes 50 µm x 27 wires high side MOSFET on 2 separate Wire (5b) (20% lower) (10% lower) wires and leads DAPs. Copper 0.045 0.044 Parasitic value includes 0.254 mm thick • Single clip structure (MOSFET and Clip (6) (90% lower) (48% lower) solder, clip and leads copper clip on 1 DAP). Table 1. Electrical parameter simulation comparison. For more information about UTAC please visit www.utacgroup.com. ◆ UTAC: Integrated Cu Clip Products References [1] 2017 May 5, Scott Thornton Body Size 6x4 5x5 5x6 6x5 5x4 6x5 5x5 https://www.microcontrollertips.com/mosfets- what-is-rdson-faq Lead 36 31 41 12 18 16 32 [2] 2004 Nov Intel DrMOS rev 1.0 release https://www.intel.com/assets/pdf/refmanual/ IC 1 1 1 1 1 1 1 drmos.pdf [3] TechSearch International, Advanced Packaging MOSFETS 2 2 2 2 2 2 1 Update. Market and Technology Trends, Volume 3 Nov. 2017 # of Clip 2 2 2 2 2 2 1 [4] Wikipedia; Gallium nitride https://en.wikipedia.org/wiki/Gallium_nitride config Stack side by side stack stack stack side by side single [5] A4WP Wireless Charging https://www.electronics-notes.com/articles/ Wire Au 1.3 Au 1.3 AuPdCu 1.0 AuPdCu 1.0 AuPdCu 1.0 AuPdCu 1.0 Au 1.3 equipment-items-gadgets/wireless-battery-charging/a4wp-wireless-charging.php Table 2. UTAC copper clip product body size and configuration examples. ONE COMPONENT SILVER FILLED EPOXY NASA Low Outgassing Approved EP3HTS-LO ELECTRICALLY CONDUCTIVE Volume resistivity: <0.001 ohm-cm

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Silicon Technology Selection for Implantable Medical Device ASICs

Andy Kelly IC/Systems Architect Cactus Semiconductor Inc.

THE DESIGN OF AN APPLICATION g) Data converters, including analog to Specific Integrated Circuit (ASIC) is digital converters (ADCs) and digital often the key to success for implantable to analog converters (DACs), to medical device developers. ASICs pro- translate signals between the digital vide the means to customize electrical electronics and the analog physical designs to a very specific set of require- and physiological interfaces. ments, rather than compromising those requirements based on readily available h) Data memory, including random- standard product ICs. access memory (RAM) and non- One of the most critical strategic volatile memory (NVM). decisions in the development of an ASIC is the selection of the silicon technology. i) Digital control logic, including For best results, this decision should con- a) A power source, consisting of a re- microprocessors, serial interfaces, sider multiple factors. chargeable battery, or a primary cell waveform generators, and sequenc- (non-rechargeable) battery. ers. Implantable Medical Devices So, what exactly is an Implantable b) A variety of power management In addition to the extensive list of Medical Device (IMD)? A condensed functions, including references, linear features, it is important to note that version of the FDA’s definition is: “an regulators, charge pumps, and buck/ these features often have diverging instrument, apparatus, or other similar boost converters. characteristics in terms of their voltages, article, which is intended for use in the frequencies, and precision requirements. diagnosis of diseases or conditions, or in c) Wireless interfaces that supports This makes the design of IMD electron- the cure, mitigation, treatment, or preven- 2-way radio-frequency (RF) commu- ics very complicated, requiring a high tion of diseases”. Perhaps some examples nication and/or near-field (NF) com- degree of customization. For those rea- might help to better describe the topic of munication between the device and sons, IMD designs often include at least this paper. Common examples of IMDs a programmer/charge device outside one application-specific integrated circuit include; Pacemakers & Defibrillators, the body, as well as wireless battery (ASIC). Spinal Cord & Brain Stimulators, and re-charge. Drug Infusion Pumps. Implantable Medical Device ASICs These devices typically consist of d) Timekeeping functions, which An ASIC is an integrated circuit a titanium enclosure containing a bat- include low-power crystal or current- (IC) that is designed specifically for the tery & electronic circuitry, a connector controlled oscillators, to keep track of requirements of one target application. or “header” that connects the device to date and time, and provide timing ref- This is in sharp contrast to common electrical leads, and electrodes at the erences for internal functions. standard-product ICs, which are designed ends of the leads. The enclosure is typi- to fit as many different applications as cally implanted in the chest or abdomen, e) Multiple types of sensors to measure possible. While the features and perfor- the leads are tunneled from the device to temperature, pressure, motion, and mance of many standard-product ICs the heart, spine, or brain, and the elec- physiological signals such as electro- are impressive, they usually represent trodes are attached to the part of the body cardiograms (EKGs) and electro- a compromise for any single applica- requiring the therapy. corticograms (ECoGs). tion. ASICs provide IMD designers with In terms of electronics features, most highly-integrated ICs that are customized IMDs are characterized by a wide range f) Driver functions, such as cardiac to precisely meet their requirements. of diverging functions. For example, a pacing, nerve stimulation, or drug One of the primary goals for an typical IMD may include: delivery. IMD ASIC is to integrate as many of

20 MEPTEC REPORT SUMMER 2018 meptec.org Figure 1. the features as possible into a single isolated low-voltage MOS devices to tion of a complementary pair of NMOS ASIC. Based on the long list of features isolate digital control logic from sensi- and PMOS devices. For these devices, and diverging requirements included in tive analog circuits, medium-voltage the gate voltage breakdown is primarily typical IMDs, it is no surprise that the MOS devices for battery-voltage power a function of the gate oxide thickness customization and integration of those management, and high voltage devices (between the Poly and WELL sections in features is a complex process. Figure 1 for wireless interfaces and output driv- the diagram). The drain voltage break- above provides a high-level summary of ers. Not all silicon technologies support down is a function of the lateral dimen- an example IMD system, with some of all these requirements on the same IC sions and the doping concentrations in the ASIC details elaborated. because specialized wafer processing the WELLs and the N+ and P+ regions, As Figure 1 suggests, the ASIC steps are required to create the non-stan- and the threshold voltage is primarily includes a mixture of digital and analog dard devices. Figures 2, 3 and 4 provide a function of the doping concentration functions, sensors and drivers, data con- a few common examples, based on an under the gate. verters, timing, and power management assumption that the reader has a basic – with operating voltages ranging from understanding of semiconductor physics. Isolated Low-Voltage MOS 1 volt to 30 volts – and all of that must Isolated low-voltage MOS devices be integrated into a single silicon chip. Standard Low-Voltage MOS are typically based on the standard This challenge makes the selection of the Standard low-voltage MOS devices devices but include an additional deeper silicon technology for the ASIC a criti- are included in most CMOS technolo- n-well implant (DNWELL) to provide cal decision for the overall IMD product gies. Figure 2 shows a typical cross-sec- electrical isolation of the PWELL2 from development.

Silicon Technology Selection

Technical Compatibility For technical compatibility, the selected technology must include devices that support the various performance requirements of the ASIC. For example, these often include standard low-voltage MOS devices for low-power, high-precision analog sensing and data converters, Figure 2. (Courtesy of XFAB Silicon Foundries) meptec.org SUMMER 2018 MEPTEC REPORT 21 TECHNOLOGY

the p- Epi Layer. This typically requires an extra mask layer and processing step to selectively apply the isolation to only the appropriate devices. Figure 3 shows the cross section including the DNWELL region.

Medium-Voltage MOS Medium-voltage MOS devices are typically based on the standard devices Figure 3. (Courtesy of XFAB Silicon Foundries) but include a thicker gate oxide to provide a higher gate voltage breakdown. This typically requires an extra mask layer and processing step to selectively apply the thicker oxide to only the appropriate devices. Figure 4 shows the cross section including a thicker gate oxide. The three examples presented here are just a small subset of the device types included in a typical IMD ASIC. In most cases, other device types are created by Figure 4. (Courtesy of XFAB Silicon Foundries) combinations of optional oxide thick- nesses, implant layers, and doping concentrations. Before deciding on a silicon technology for an ASIC, designers must review the various requirements, map the requirements to available device types, and confirm that all the requirements are met. If the technology compatibility is not established, then a specific silicon technology cannot be used for that ASIC design.

Business and Risk Management Factors In addition to the technical compatibility, there are several risk factors that should be considered before selecting a silicon technology. One important factor for mitigating IC design risk is the availability of a good process design kit (PDK). A PDK is the design infrastructure used to support the schematic design of a new circuit, simulate its functions and electrical performance, and translate it to physical layout. This infrastructure includes schematic, symbol, and layout representations of every silicon device, backed up by detailed and accurate electrical models – as well as gate-level representations of digital functions that are compatible with automated design synthesis and layout tools. All silicon technologies require unique PDKs, and the quality of the PDK directly influences the quality of an ASIC design. Even with excellent PDKs, IC designers depend on effective technical Table 1.

22 MEPTEC REPORT SUMMER 2018 meptec.org support, due to the complex nature of many IMD ASIC designs. This support comes in the form of data sheets and specifications describing the devices, models, and design rules – generally accessible through the wafer fab’s website. It also may include educational materials that provide guidelines for best design practices, and ideally includes a technical support hotline for designers to call for urgent issues. Risk management strategies should also apply to the prototyping phase of an ASIC development. Due to the complexity of these designs and the uncertainty of the final application conditions, it is not uncommon for an ASIC to require a minor design revision after initial prototypes are thoroughly evaluated. As such, it is important to have options to reduce initial prototype costs and ease the cost and schedule burden of potential design revisions. Many wafer foundries offer reduced wafer lot sizes for initial prototype runs, and split lots that allow some wafers to be paused midway through the process. These offerings help the design team to react quickly and inexpensively to minor design change requests. Ideally, the wafer foundries also offer options Table 2. for reducing mask costs for prototypes. These options include multi-project is close to $1M. For high density digital and red represents a disconnect. In most wafers – for which mask sets and wafers and memory ICs, this cost is justified cases, the decisions are obvious after are shared between multiple parties, and because those circuits shrink dramati- that simple analysis. For less obvious multi-layer mask sets – for which mul- cally as the process geometry shrinks. choices, the decision matrix is expanded tiple lithography layers are constructed In contrast, many of the analog-centric to include numerical weights and scores on each mask plate, resulting in some functions in most IMD ASICs are not for each item. cost reduction for prototypes. dependent on the minimum dimensions, Table 2 incudes a partial list of ASIC After prototypes are approved, and and therefore do not shrink enough to designs completed by Cactus Semicon- ASIC designs are ready for production, justify the extra costs associated with ductor, arranged by technology process it is important to ensure continuity of the deep sub-micron technologies. node. The 600nm design were all started supply. For IMD ASICs, silicon tech- before 2010, and we don’t anticipate nologies should be available for at least 7 Project Examples much more demand in those technologies years before obsolescence. Over the past decade, Cactus Semi- in the future. All the industrial applica- Quality and reliability are of utmost conductor has designed & produced tions have been in the 180nm node, and importance for implantable devices, so dozens of full-custom ASICs, and about most implantable ASICs have been in it is critical to choose a foundry with a 75% of them are for medical device 350nm. complete quality management system, applications. In the initial stages of every all appropriate certifications, and wafer project, we complete a review of all the Conclusion traceability. factors mentioned in this report, and then As Table 2 suggests, Cactus Semi- Last, but not least, the final produc- select a silicon technology based on a conductor has found that the best silicon tion mask and wafer costs are always balanced assessment. Table 1 is an exam- technologies for IMD ASICS are in the important, as they often represent more ple of a decision matrix used to compare 180nm to 350nm range, from foundries than 25% of an ASIC development the merits of two different technologies with excellent PDKs, design support, and budget. Generally, smaller geometry pro- at two different foundries. This example quality systems. ◆ cesses have higher mask and wafer costs. has a simple red, yellow, green assess- For example, a 180nm mask set cost is in ment, for which green represents a good the $100k range, while a 55nm mask set fit, yellow represents a manageable fit, meptec.org SUMMER 2018 MEPTEC REPORT 23 Your Microelectronic Package Assembly Solution for MEMS Sensors

Product Design for Wire-Bondability

William Boyce SMART Microsystems Ltd.

WIRE BONDING IS A COMMONLY used process to create low-cost and reliable electrical interconnects between semiconductor components and mechanical assemblies. Wire bonding is generally considered the most cost-effective and flexible interconnect technology for microelectronic assembly. It is used to manufacture the vast majority of fully packaged semiconductor products. In fact, over 15 trillion interconnects are formed by wire bonding each year. Dif- ferent types of wire bonding processes include gold ball bonding, fine gauge aluminum wedge bonding, heavy gauge aluminum wedge bonding, and ribbon bonding. In order to be successful, wire bonding must be properly designed into the microelectronic assembly from the start. The assembly must be designed to accommodate the wire bond process tooling, the wire bond interconnect pads Figure 1. Process tooling – end effector, cutter, and clamp. must be properly sized to accommodate the wire bonds, the metallization of the the assembly is not typically a big issue, wire bond pad needs to be designed to be but the overall assembly envelope can compatible with the chosen interconnect be large, particularly with battery packs. bond wire that can withstand the environ- (See Figure 2) If the assembly design mental and mechanical conditions of the does not fit into standard production end application, and the assembly must bonders, then a custom bonder designed be designed to fully support the structure specifically for the assembly may be beneath the wire bonds. required. This would add considerable Wire bond tooling includes all of the cost. process and assembly tooling as well as Figure 2. Large battery pack. The wire bond interconnect pads on the equipment required to perform the the part must be properly sized to accom- wire bonding operation on the device, bonding. It is also important not to forget modate the wire bonds. Because today’s assembly, or sub-assembly. Process tool- about the tolerance stack in those compo- production wire bonders have positional ing refers to all of the tooling on the wire nent locations. If any portion of the bond tolerances in the sub-micron range, this bond head. This includes the wire bond- head, other than the bond tool, comes seems like a fairly simple and straight ing end effector tool, cutters, clamps, into contact with any portion of the part, forward requirement. However, it is ultrasonic transducers, etc. (See Figure 1) other than the bond pad, the wire bond often overlooked. Sometimes, in the case There must be adequate clearance around will be compromised due to the shunting of a PCB or flex circuit, the immediate the wire bond pad to fit the tool and all of ultrasonic energy to ground. It may design focus is on layout and assembly of its peripheral parts into the assembly seem simplistic, but it is important to envelope. The bond pads are sized to to perform the wire bond. High aspect mention that the part being bonded must whatever room is left on the board at ratio components, like passive compo- fit into the wire bonding process equip- the very end of the design process. Wire nents in close proximity to the wire bond ment. In the case of heavy gauge wire bond pads designed to three times the locations, can cause interference with and ribbon bonding, the space inside overall size of the wire bond envelope

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SMART Microsystems provides custom assembly services for microelectronics, sensors, and MEMS. Our customers are producers, manufacturers, and suppliers who need microelectronic sub-assemblies for products in high- value, low-volume market applications. These customers are developing innovative products for a wide variety of markets, including aerospace, automotive, defense, biomedical, and industrial controls. SMART Microsystems has an experienced technical team, state-of-the-art equipment, and brand new facilities that provide contract services for prototype development, environmental life testing, and manufacturing. Call us today at 440-366-4203 or visit our website for more information about our capabilities and services.

Innovative Microelectronic Solutions.

141 Innovation Drive, Elyria, Ohio 44035 ISO9001:2015 Telephone: 440.366.4203 [email protected] CERTIFIE

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are preferred. The wire bond envelope includes the bond footprint, the tail, and the transition heel of the bond. (See Figure 3) Creating a pad that is three times the size of the wire bond envelope ensures adequate room with the potential for rework. In cases where the overall dollar value of the assembly is low, and rework is unnecessary or not required, two times the envelope can be an acceptable pad size. Allowing for adequate bond pad size can greatly increase the manufacturability of the assembly and reduce the cost. The metallization of the wire bond pad needs to be designed to be compatible with the chosen interconnect bond wire. Not only does the bond pad need to be compatible with the bond wire but it also needs to be compatible with the assembly design for product life. In the case of plating systems, nickel, gold, and aluminum are the most popu- Figure 3. Close up of wire bond envelope – initiating first bond. lar bond metals. The most robust wire bonding metal systems are gold wire pads. Air voids in the adhesive layer will on a gold pad or aluminum wire on an absorb the ultrasonic energy and weaken aluminum pad. (See Figure 4) However, the wire bond due to lack of structural due to product assembly considerations support. like cost, it is seldom possible to have When developing a wire bond inter- an ideal metal interconnect system. As connect it is important to begin the an example, soft electroless nickel is a design with the end in mind. The best common and well established plating outcomes can be achieved when the metal. Nickel oxides are particularly dif- design team includes the process engi- ficult to bond through, so for aluminum neering team in the design reviews and wire it is common to use a gold flash to product decisions as early in the cycle as protect the nickel plating from oxidation. possible. Whether the effort is internal Conversely, when bonding gold wire on to a single organization or is based on an nickel plating, the gold finish needs to be outsourced supplier relationship, early thicker. Also, gold wire bonding requires collaboration in the spirit of concurrent an elevated temperature of 150˚C for the Figure 4. Aluminum wire on aluminum and engineering in “product design with the bonding process, so the assembly needs nickel finishes. end in mind” can save considerable time to be designed to withstand this thermal and money overall. ◆ exposure. Since a bond metal compro- support beneath the bond pads to accom- mise is likely to occur somewhere in the modate the compressive forces of the William Boyce is the Engineering Manager at design, typically regarding pad metal- bonding process. Ideally, the space on SMART Microsystems. He has served in senior lization, it is best to make that decision the back side of the bond pads is free engineering roles over the last 19 years with sooner rather than later in the design of components and has adequate room accomplishments that include manufactured cycle. for tooling to provide a mechanical sup- automotive sensors. He is certified in EIT and Six Sigma Green Belt and is an industry recog- The final important consideration for port beneath each bond bad. This can nized expert in Al wire bonding. Additionally, he wire bond pad design is structural sup- be accomplished with an adhesive or designed and led the metrology lab and machine port for the wire bonding process. Effec- mechanical bond to a substructure and/or shop at Sensata. Mr. Boyce earned a Bachelor tive and robust wire bonding is accom- custom tooling that provides the support. of Science in Engineering degree from the Uni- plished by the application of ultrasonic If the mechanical support is provided by versity of Rhode Island and has been a member energy with compressive force over time. an adhesive bond, it is important that the of the IMAPS New England Chapter for over There needs to be enough unobstructed adhesive is void free beneath the bond 10 years.

26 MEPTEC REPORT SUMMER 2018 meptec.org TECH BRIEFS

State-of-the-Art Technology Briefs A special feature courtesy of Binghamton University

We are pleased to continue this fea- Cornell University collaborating with in low-power electronics, medical electronics ture in the MEPTEC Report, brought Honeywell Aerospace, have demonstrated a devices and multifunctional shape-memory to us by new Advisory Board member method for remotely vaporizing electronics materials. (IEEC file #10455, Science Daily, Dr. Gamal Rafai-Ahmed from Xilinx. into thin air, giving devices the ability to van- 1/25/18) The State-of-the-Art Technology Briefs ish along with their valuable data if they were contains articles from the Binghamton to get into the wrong hands. This unique abil- North Carolina State University University S3IP “Flashes.” Full text ity to self-destruct is at the heart of an emerg- researchers have developed a technique that is available upon request through the ing technology known as “transient electron- uses silver nanowires to print circuits on IEEC Site at: http://www.binghamton. ics”, in which key portions of a circuit, or the stretchable substrates. The advance makes it edu/s3ip/index.html. whole circuit itself, can discreetly disintegrate possible to integrate the material into a wide or dissolve. And because no harmful byprod- array of electronic devices. Silver nanowires ucts are released upon vaporization, engineers have drawn significant interest in recent years envision biomedical and environmental appli- for use in many applications, ranging from cations along with data protection. (IEEC file prosthetic devices to wearable health sensors, #10452, ECN, 1/25/18) due to their flexibility, stretchability and conductive properties. (IEEC file #104978, EIN University of Alberta researchers have 007, 2/27/18) developed a hybrid nanocomposite material consisting of colloidal nanocrystalline molybdenum oxide (MoO3) dispersed within a W0.71Mo0.29O3 capable of simultaneously modulating light transmission and University of Illinois researchers have storing electrochemical energy. The research- developed a new technology for switching ers essentially turned a smart window into a heat flows ‘on’ or ‘off’. Engineers have long high-capacity rechargeable battery. This is desired a switch for heat flows, especially in invaluable for new display technologies and electronics systems where controlling heat green “smart” window platforms. (IEEC file flows can significantly improve system per- #10593, Laser Focus World, 4/24/18) CST Global, a III-V photonic devices formance and reliability. This technology is manufacturer, has proven the feasibility of based on the motion of a liquid metal droplet. A team from Northwestern University 60-GHz radio over fiber (ROF) transmission The metal droplet can be positioned to con- have developed a “memtransistor,” having the at a 1,270-nm wavelength, paving the way nect a heat flow path or moved away from the characteristics of both a memristor and a tran- to potential solutions for 5G networks. ROF heat flow path to limit the heat flow. (IEEC sistor. The memtransistor encompasses mul- networks are emerging as a completely new file #10520, Science Daily, 3/8/18) tiple terminals that operate more similarly to a and promising communication paradigm for neural network. Neural networks can achieve delivering broadband wireless access services Iowa State University researchers are complicated computation with significantly and fronthaul at 60 GHz, relying on the syn- developing a graphene printing technology lower energy consumption compared to a digi- ergy between fixed optical and millimeter- that can produce electronic circuits that are tal computer. Researchers have searched for wave technologies. ROF technology enables low-cost, flexible, highly conductive and water ways to make computers more neuromorphic, RF signals to be transported over fiber across repellent. They used inkjet printing technology to perform increasingly complicated tasks kilometers and can be engineered for unity with an ink made of graphene flakes to create with high efficiency. (IEEC file #10495, Solid gain RF links. (IEEC file #10573, EE Times, electric circuits on flexible materials, and a State Technology, 2/21/18) 4/12/18) rapid-pulse laser process that treats the graphene without damaging the printing surface. Researchers at the University of Researchers from Japan’s National Among applications of their laser processing Illinois have developed a mechanism that Institute for Materials Science have fabricated technology are graphene-printed circuits that triggers shape-memory phenomena in organic a key circuit using hydrogenated diamond repel water. The energy density of the laser crystals for plastic electronics. The shape- that can function at temperatures as high processing can be adjusted to tune the degree shifting structural materials are made with as 300˚C. The new circuits can be used in of hydrophobicity and conductivity of the metal alloys. Shape-memory materials sci- diamond-based electronic devices that are printed graphene circuits. (IEEC file #10456, ence and plastic electronics technology, when smaller, lighter and more efficient than their Iowa State University, 1/25/18) merged, could open the door to advancements silicon-based counterparts. For the high-power meptec.org SUMMER 2018 MEPTEC REPORT 27 TECH BRIEFS

generators, diamond is more suitable for fabri- The Silicon photonics is still a small The point-of-care (PoC) biosensors cating power conversion systems with a small market today, with sales at die level estimated testing market will grow to $33 billion by size and low power loss. (IEEC file #10568, at $30 million in 2016. However, it has big 2027, with molecular diagnostic devices R&D, 4/10/18) promise, with an estimated 2025 market value the main driver for this growth. Biosensors of $560 million at chip level and almost $4 are used to detect and quantify biological billion at transceiver level. Silicon photonics material associated with a disease state or technology will grow from a few percent of health condition (biomarkers). Biosensors are total optical transceiver market value in 2016 powerful tools for diagnosis and monitoring. to 35% of the market in 2025, mostly for (IEEC file #10490, Sensors, 2/22/18) intra-data center communication. Strongest demand is for 400G. The next evolution is to develop a 400G optical port over a single fiber across 500m at less than $1 per giga- bit and with power <5mW/Gb. (IEEC file #10461, Sensors, 1/19/18) Researchers from MIT, University of California, Boston University, and the Uni- versity of Colorado have developed a method to fabricate silicon chips that can communicate with light and are no more expensive than current chip technology. The technique uses existing manufacturing processes. Mov- Goodbye passport, so long boarding ing from electrical communication to optical pass as entry at airports could soon just be communication is attractive to chip manufac- your face. Biometrics for international travel- turers because it could significantly increase ers, which allow passengers to board a flight chips’ speed and reduce power consumption, or clear passport control via a photo, is right an advantage that will grow in importance around the corner says U.S. Customs and as chips’ transistor count continues to rise. Researchers at the University of Tokyo Border Protection Agency. The goal is to have (IEEC file #10578, Science Daily, 4/19/18) have developed a hypoallergenic electronic this in place over the next four years. The sensor can be worn on the skin continu- plan is to begin with international flights then ously for a week without discomfort. The expand to domestic. On inbound international MARKETMARKET TRENDS TRENDS elastic electrode is constructed of breathable travel, you’ll be able to leave the passport in nanoscale meshes and holds promise for the your pocket. Biometrics at the airport works development of noninvasive e-skin devices by matching the picture the government has, that can monitor a person’s health continu- i.e. your passport photo, with a new image ously over a long period. Wearable electronics generated at the airport. (IEEC file #10484, that monitor heart rate and other vital health USA Today, 2/6/18) signals have made headway in recent years, with next-generation gadgets employing lightweight, highly elastic materials attached RECENTRECENT PATENTS PATENTS directly onto the skin. (IEEC file #10487, EIN007, 2/5/18) Polygon Die Packaging (Assignee: IBM Corp.) Patent No.- 14/609,237. A lidded or Revenues from quantum computing is lidless flip-chip package includes two or more Nissan has unveiled an ambitious projected at $1.9 billion in 2023, increasing polygon shaped dies. The polygon dies may automotive research project that could rede- to $8.0 billion by 2027. Applications and end be interconnected to a substrate or to an inter- fine the future of driving. Nissan has dubbed user communities include Web search, materi- poser interconnected to a substrate. The inter- its research “Brain-to-Vehicle,” or B2V, tech- als/drug design, financial services, general poser may be similarly shaped with respect to nology. By studying how vehicles can inter- business planning, healthcare, transportation the polygon die(s). For the lidless or lidded pret electrical signals from a driver’s brain and the energy industry. In 2018, quantum package, the package may include underfill and using these thought patterns, they are able computing users, other than will account for under the polygon dies surrounding associat- to develop faster reaction times and make just 6% of quantum computer revenues. By ed interconnects. For the lidded package, the driving more enjoyable. The company says 2024 their share will be around 30%. The package may also include thermal interface it is the latest development in its Intelligent biggest commercial expenditures on quantum materials, seal bands, and a lid. The polygon Mobility vision for transforming how cars are computing will come from defense, aero- die package reduces shear stress between driven, powered, and integrated into society. space, pharmaceuticals, specialty chemical, the polygon die/interposer and associated (IEEC file #10465, Automotive Electronics, banking, and finance (IEEC file #10482, underfill as compared to square or rectangular 1/30/18) Globe Newswire, 12/5/18) shaped die/interposer.

28 MEPTEC REPORT SUMMER 2018 meptec.org PCB that provides a direct thermal base PCB and arranged transversally to the facilitate access by industry to the university’s path between components and a ther- base PCB and forms an angle alpha. there- research capabilities and provides staff to mal layer (Assignee: Adura Sol.) Pub. No.- with. As a result, a slanted stack of IC pack- perform technical investigations on behalf of US9883580. A method of assembling a com- ages is obtained, wherein the IC packages are industrial clients. www.binghamton.edu/s3ip ponent to a printed circuit board that includes essentially parallel to each other. a thermal layer and a circuit layer separated Integrated Electronics Engineering by a dielectric layer. The circuit layer includes Semiconductor interposer integra- Center (IEEC) circuit pads that correspond to terminal sur- tion (Assignee: BroadPak Corp.) Pub. No.- The IEEC is a New York State Center of faces on the component. The dielectric layer US9893004. Integrated circuits are described Advanced Technology (CAT) responsible for includes an aperture that exposes a portion of which directly connect a semiconductor inter- the advancement of electronics packaging, its the thermal layer that correspond to a thermal poser to a motherboard or printed circuit board mission is to provide research into electronics pad on the component. Solder paste is applied by way of large pitch connections. A stack packaging to enhance our partner’s products, to the circuit pads and the exposed thermal of semiconductor interposers may be con- improve reliability and understand why parts layer. Lower surfaces of the solder paste are in nected directly to one another by a variety of fail. More information is available at www. contact with the circuit pads and the thermal means and connected to a printed circuit board binghamton.edu/ieec layer and upper surfaces of the solder paste through only a ball grid array of solder bumps. are substantially coplanar. The component is The stack of semiconductor interposers may Center for Autonomous Solar Power placed on the solder paste. include one or more semiconductor interpos- (CASP) The CASP center focusses on thin ers which are shifted laterally to enable direct- film solar cells and supercapacitors. The System for improving isolation in ly electrical connections to intermediate semi- recent progress includes 7.5% efficiency pure high-density laminated printed circuit conductor interposers. The top semiconductor sulfide CZTS solar cell without an antireflec- boards (Assignee: Lockheed Martin) Patent interposer may have no electrical connections tion coating, and nano-structured transition No.- 13/716,726. A system and method of iso- on the top to increase security by making elec- metal oxide supercapacitor with specific lating a layer-to-layer transition between con- trical “taps” much more difficult. capacitance of 760 F/g, maximum energy ductors in a multilayer printed circuit board density of 8 Wh/kg, and a power density of 13 includes formation of a first ground via at least Semiconductor die backside devices KW/kg. The CASP team has been invited to partially surrounding a first signal conduc- (Assignee: General Electric) Patent No.- take part in the Cohort 5 NEXUS-NY program tor in at least one layer of the printed circuit 201744022512. A die for a semiconductor to explore market opportunity of a dielectric board and formation of a second ground via chip package includes a first surface including capacitor technology (patent currently drafted) at least partially surrounding a second signal an integrated circuit formed therein. The die that recently came out of CASP center. More conductor in another layer of the printed cir- also includes a backside surface opposite the information about CASP can be found at cuit board. The first and second ground vias first surface. The backside surface has a total https://www.binghamton.edu/casp are plated with a conductive material. surface area defining a substantially planar region of the backside surface. The die further NorthEast Center for Chemical Energy Embedded printed circuit board includes at least one device formed on the Storage (NECCES) (Assignee: LG Innotek) Patent No.- backside surface. The one device includes at NECCES is working on the limitations to KR20160120892. This invention relates to least one extension extending from the at least batteries reaching their ultimate potential. an embedded printed circuit board, which one device beyond the total surface area. Recently they have placed emphasis on a new includes: an insulating substrate; an insulating cathode and a new anode. The LixVOPO4 layer disposed on one surface of the insulating cathode can attain over 300 Ah/kg compared substrate; and a device embedded in the insu- BINGHAMTONBINGHAMTON UNIVERSITY UNIVERSITY with around 160 Ah/kg for the commercial lating substrate. A through hole is formed in LiFePO4 cathode. The SnyFe/C composite the insulating substrate, and a cavity is formed BINGHAMTON UNIVERSITY currently anode has a more than 50% higher capacity by the one surface of the insulating surface. has research thrusts in healthcare / medical than today’s graphite-based anodes. More electronics; 2.5D/3D packaging; power elec- information about CASP can be found at Integrated circuit package assem- tronics; cybersecure hw/sw systems; photon- www.binghamton.edu/necces bly comprising a stack of slanted IC ics; MEMS; and next generation networks, package (Assignee: IBM Corp.) Patent. computers and communications. Analytical and Diagnostic Laboratory No.- 15/223621. Embodiments of the present (ADL) The ADL provides an array of analyti- invention are directed to an integrated cir- The S3IP Center of Excellence is fund- cal and diagnostic tools located in a single cuit (IC) package assembly. The IC package ed by New York State to foster collaboration facility to address the needs of faculty and assembly includes a base printed circuit board between the academic research community industry in understanding materials, structures (PCB), and a set of IC packages. Each of the and the business sector to commercialize and failures that are found in electronics IC packages includes at least one IC chip, new products and technologies. The S3IP packaging. The ADL supports the 5 research mounted on or partly in a support component, is an umbrella organization comprising five centers previously mentioned. The facilities of which mechanically supports and electrically constituent research centers, their labs, and its the ADL are available to our industry partners. connects to the IC chip. In addition, each of own Analytical and Diagnostic Lab (ADL). More information can be found at www.bing- the IC packages is laterally soldered to the The S3IP coordinates across these entities to hamton.edu/adl ◆ meptec.org SUMMER 2018 MEPTEC REPORT 29 Advanced Packaging Technologies Get Reliability Boost from NCF Material

Rose Guino, Henkel Electronic Materials LLC

THE PAST DECADE HAS WITNESSED vias (TSVs) are thinner to accommodate Because of these realities, non-con- dramatic growth in mobile and comput- 3D stacking and thinner substrates are ductive paste (NCP) and non-conductive ing technology, a market dynamic that has already available, making handling and film (NCF) – also referred to as wafer- driven the development and adoption of warpage control more challenging. Achiev- applied underfill (WAUF) – materials have various interconnect solutions. Tradition- ing higher functionality for a given die size emerged as the most reliable underfill ally, transistor scaling has been the tech- has also given rise to copper (Cu) pillar solutions for Cu pillar and TSV packaging nique used to advance form and function, technology. This technique allows design- approaches. Both NCP and NCF materials but this method has become increasingly ers to place Cu pillar bumps in higher den- offer excellent bump-pad alignment accu- challenging and costly. Therefore, many sity, enabling increased I/O and utilizing racy through thermal compression bonding, device designers are considering new wafer functionality. But, like other chal- as shown in the process diagram below. advanced packaging techniques to address lenging designs, Cu pillar bump pitches In the memory market, however, the continued requirement for high perfor- of less than 50 μm and narrow sub-40 μm where 3D TSV stacking applications have mance and increased functionality. Modern bondline gaps make conventional bump evolved into the dominant packaging package designs include increased I/O, protection methods increasingly problemat- technique, TSV die applications less than system-in-package and higher interconnect ic. Traditional capillary underfills (CUFs), 100 μm thick are challenging for thermal densities, among others. for example, are hard-pressed to flow in compression bonding of paste materials. As newer packages become thinner and and around the tight dimensions. Because Because of the potential for die top and smaller with more I/O for greater func- flux cleaning under the tight spaces is also bonding tool contamination with NCPs, tion, ensuring the reliability of the designs challenging, underfill compatibility with packaging specialists have moved toward becomes essential to long-term perfor- flux residues is a growing concern. In addi- the use of NCF for die structures – includ- mance. Stress management and structural tion, new substrate solder mask designs ing TSV and Cu pillar – where more bump protection are critical factors, as such as partial or full solder mask openings controlled flow and fillet formation are chips are more fragile than ever with lower (SMOs) are making the underfill process required. As illustrated in the diagram on silicon nodes and ultra-low dielectric lay- more complex and void-prone due to the page 32, the NCF is applied via lamina- ers. Wafers and dies with through silicon added substrate topography. tion and not only protects the bumps on

30 MEPTEC REPORT SUMMER 2018 meptec.org NON CONDUCTIVE FILM Advanced Packaging Technologies Get Reliability Boost From NCF Material

Today’s smaller footprint, greater I/O package designs dictate use of emerging technologies like through-silicon via (TSV) and copper pillar to address form factor requirements. With this come thinner dies for 3D stacking and higher-density bump, driving the need for greater protection to ensure reliability. In the memory market, where TSV applications with die less than 100 μm thick are common, Henkel’s new non-conductive film (NCF) technology provides controlled flow, stability and protection without the concerns associated with paste-based underfill materials and challenges posed by thermal compression bonding.

For more information, contact 1-800-562-8483 or visit us online at henkel-adhesives.com/electronics

All marks used are trademarks and/or registered trademarks of Henkel and its affiliates in the U.S., Germany and elsewhere. © 2017 Henkel Corporation. All rights reserved. (5/17) the wafer, but also serves as additional support for wafer handling and successive processing. Bump protection is achieved immediately following thermal compression bonding, and die stacking of TSV dies is highly viable. The latest NCF material to be introduced to market is a 2-in-1 wafer-applied underfill film from Henkel. Henkel’s NCF has been developed to facilitate die processing for die that are less than 60 μm thick and, as compared to previous generation materials, the new NCF has a long work life of 8 weeks; 6 weeks with the backgrinding tape and an additional 2 weeks once the backgrinding tape is removed. Not only does the backgrinding tape facilitate wafer thinning when kinetics to achieve good joints without is not achievable with paste-based materi- required, it also delivers handling stability entrapment or solder extrusion, provide als. As the industry moves toward more and enables complete NCF gap filling and good fillet coverage and complete gap fill- challenging designs and 3D integration, coverage for maximum bump protection. ing. advanced materials such as Henkel’s new The material has lower melt viscosity In addition to all of the performance non-conductive film will be essential for which allows for lower bond force process- and reliability benefits afforded by NCF, robust wafer processing and long-term ing, exceptionally fast three-second cure, film-based materials are ideal for the package reliability. a four-month shelf life and no outgassing requirements of memory chip processing Email [email protected] for during processing. Henkel’s NCF has been and, even for non-memory applications, more about NCF benefits. For Henkel info designed to balance flow behavior and cure enable the close placement of die, which visit www.henkel.com/electronics. ◆

customer and employee sensitivities. However, whenever possible, running STEPHEN ROTHROCK founded ATREG OPINION in 2000 with the vision to help global a public marketing campaign helps advanced technology companies in the increase awareness of the opportu- semiconductor, assembly & test, display,  continued from page 34 nity and typically compresses the time and electronics sectors divest and acquire required to fully expose the offering infrastructure-rich manufacturing assets 3. CARRY OUT A FORMAL PROCESS to the market. The market typically and cleanrooms. Since ATREG’s inception, responds more favorably to fab offerings Stephen has led complex transactions for • Demonstrate that you are a com- from established, well-respected com- such reputable companies as Atmel, Fre- mitted seller and create a sense of panies, so revealing the identity of the escale, Fujitsu, IBM, Infineon, Matsushita urgency seller from the outset can be advanta- (Panasonic), Maxim, Micron, NXP, Qual- geous. comm, Renesas, Sony, and Texas Instru- Carrying out a formal disposition ments among many others in the USA, process and retaining advisors sends • Don’t limit the marketing effort to Europe, and Asia. a clear message to the market that the only a small set of logical buyers In 2012-2013, he spent 20 months in company is serious about completing a Japan to oversee the firm’s Asian opera- transaction. Additionally, a formal pro- Although it makes sense to concen- tions. Prior to founding ATREG, Stephen cess allows the company to solicit and trate on the most realistic set of buyers established Colliers International’s Global Corporate Services initiative and headed compare multiple offers simultaneously, (particularly in the scenario of an opera- the company’s U.S. division based in thereby providing sellers with pricing tional sale), given the limited number of transactions that occur in a typical year, Seattle, Wash. leverage and options with regards to deal Before that, he worked as Director terms (e.g. terms, counter-party, timing, it is wise to contact a broader set of pros- pects, including IDMs, foundries, OEMs, for Savills International commercial real etc.) estate brokerage in London, UK, also serv- and even fabless companies. In cases 4. LEAVE NO STONE UNTURNED ing on the UK-listed property company’s where a manufacturing fab or cleanroom international board. Stephen holds an • When possible, institute a public cannot be sold operationally, this is even MA degree in Political Theology from the campaign for maximum exposure more relevant as the cleanroom asset can University of Hull, UK and a BA degree in potentially be utilized by a much broader Business Commerce from the University of Manufacturing fab or cleanroom set of companies and industry sectors, Washington in Seattle, USA. offerings are typically confidential given including data center, solar, etc. ◆

32 MEPTEC REPORT SUMMER 2018 meptec.org 2018

15th International Wafer-Level Packaging Conference Driving an Interconnected World San Jose, California, USA October 23-25, 2018

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Exhibit & Sponsorships: Conference Questions: Kim Newman www.iwlpc.com Jenny Ng [email protected] [email protected] OPINION

Top 4 Considerations When Disposing of an Operational Cleanroom Manufacturing Facility

Stephen Rothrock President & CEO ATREG, Inc.

SELLING AN INFRASTRUCTURE- • Assign a small, focused internal At the beginning of a fab or clean- rich manufacturing asset such as an team with a high level of authority to room disposition process, companies operational semiconductor cleanroom manage the divestment project should have a solid understanding of facility can be a difficult and time- current semiconductor manufacturing intensive process. Competing interests In order to further minimize the dynamics and the potential impact on from multiple stakeholders as well as potential for mixed messages, it is the demand and anticipated valuation transaction complexities can arise and important that the selling company for the manufacturing asset. In general, derail a successful divestment. Over the assigns a project team with the decision- second-hand semiconductor facilities last 17 years, ATREG has facilitated making power to control the disposition will always sell at a fraction of their many of these transactions for some of process both internally and externally. original investment. However, in a peri- the world’s largest and most reputable od of constrained capacity, an attractive technology companies. Drawing from asset typically attains higher value than our extensive experience, we thought Carrying out a formal usual given a shortage of fab opportuni- we would share the top four critical ele- ties and multiple buyers. Conversely, ments needed to ensure the successful disposition process in a down market when excess capac- sale of an operational semiconductor ity is an issue, lower fab values should manufacturing facility or cleanroom: and retaining advisors be expected. If sellers are not realistic in regard to fab value and other deal 1. GAIN CORPORATE ALIGNMENT sends a clear message considerations, a mutually beneficial transaction will be difficult to achieve. • Establish clear support within your to the market that the Prospective buyers don’t have the time company for a particular disposition and money for belabored discussions strategy company is serious with unrealistic or reluctant sellers. It is not uncommon for various about completing a • Look at the Transaction Holistically stakeholders within a company to have differing views about the disposition transaction. The price paid for a manufacturing strategy for a fab or cleanroom. The fab or cleanroom is just one component real estate group may consider the sale of the overall value of a transaction. of the site as a real estate asset, the pro- This team would be responsible for Other elements such as the supply curement team may have discussions making sure everyone within the com- agreement terms (e.g. duration, volume, with their contacts regarding the sale of pany adheres to the agreed-upon dispo- pricing), potential liabilities relieved in the tools, etc. However, if the plan is to sition strategy, while working shoulder the event of a fab shutdown, and non- maximize transaction value by selling to shoulder with a trusted advisor to financial considerations such as grace- the semiconductor manufacturing facil- communicate a coherent message to the ful exit from the site (e.g. avoidance of ity operationally, all stakeholders must market. mass workforce layoffs) should all be be aligned. Operational buyers will be considered in calculating the overall wary about evaluating a fab opportu- 2. SET REALISTIC EXPECTATIONS value for the transaction. nity seriously if they hear rumors that the tools and/or real estate are being • Be educated about the market and shopped separately. market dynamics continued on page 32 

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