Gigaplane-XB: Extending the Ultra Enterprise Family Alan Charlesworth (
[email protected]), Andy Phelps, Ricki Williams, Gary Gilbert Sun Microsystems, Inc. Abstract The Gigaplane-XB interconnect of the Starfire system extends the range of Sun’s Ultra Enterprise SMP server family by 4x. It uses multi-level address and data routers to provide 167 million global snoops per second, and 10,667 MBps of uniform-memory-access band- width. The use of point-to-point routers allows the system to be dynamically reconfigured into multiple hardware-protected operating system domains, with hot-swappable boards. Comparisons are made with the bus-based technology of the smaller family members. 1. Introduction Table 1 compares the memory-port architectures of cur- rent microprocessors. A combination of a 16-byte wide When a new processor debuts, we hear mostly about its data path, a 100 MHz system clock, and separate address SPECint95 and SPECfp95 performance. It is probably and data paths has made Sun’s Ultra Port Architecture more important to know how well a processor’s power is (UPA) among the highest-bandwidth memory ports. The balanced its memory bandwidth and latency. From a sys- UPA is used across all Sun’s UltraSPARC systems: from tem designer’s perspective, the main reason to have an desktop workstations to the 64-processor Starfire instruction set architecture is to get the opportunity to (UltraEnterprise/High Performance Computing 10000) engineer into the processor chip a good interconnect server. architecture. Table 1. Memory-port characteristics. Max Data Separate Data Peak data Instruction set Interconnect Current CPU Port width address duty bandwidth architecture architecture model MHz (bytes) and data? factor (MBps) SPARC UPA [9] UltraSPARC-II 100 16 Yes 100% 1,600 Alpha See [3] 21164 88 16 Yes 100% 1,408 Mips Avalanche [18] R10000 100 8 No 84% 840 PA-RISC Runway [1] PA-8000 120 8 No 80% 768 PowerPC See [2] PPC 604 67 8 Yes 100% 533 Pentium Pro/II See [5] Pentium Pro/II 67 8 Yes 100% 533 2.