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Chapter 4 Let’s build a processor! 1 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine three MIPS implementations A simplified version (single cycle and multi-cycle) A more realistic pipelined version Simple subset, shows most aspects Memory reference: lw, sw Arith meti c/l ogi cal : add, sub, and, or, slt Control transfer: beq, j 2 Instruction Execution PC instruction memory, fetch instruction Register numbers register file, read registers Depending on instruction class Use ALU to calculate Arithmetic result Memory address for load/store Branchddh target address Access data memory for load/store PC target address or PC + 4 3 CPU Overview 4 Multiplexers Can’t just join wires together Use multiplexers 5 Control 6 Logic Design Basics Information encoded in binary Low voltage = 0, High voltage = 1 OiOne wire per bit Multi-bit data encoded on multi-wire buses Combinational element Operate on data Output is a function of input State ((qsequential) elements Store information 7 Combinational Elements AND-gate Adder A + Y Y = A & B Y = A + B B A Y B Arithmetic/Logic Unit Multiplexer Y = F(A, B) Y = S ? I1 : I0 A M I0 Y u Y ALU I1 x B S F 8 SSaetate Elem ent s Unclocked vs . Clocked Clocks used in synchronous logic when should an element that contains state be updated? falling edge cycle time riiising ed ge Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 9 An un cl ock ed st at e el em ent The set -reset latch output depends on present inputs and also on past inputs Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 10 Laactch es aadnd Flip-flops Output is equal to the stored value inside the element (don't need to ask for permission to look at the value) Change of st a te (va lue ) i s b ased on th e clock Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 11 Laactch es aadnd Flip-flops Latches: whenever the inputs change, and the clock is asserted "logically true" , — could mean electrically low Flip-flop: state changes only on a clock edge (edge-triggered methodology) A clocking methodology defines when signals can be read and written — wouldn't want to read a signal at the same time it was being written Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 12 D-laactch Two inputs: the data value to be stored (D) the c lock sig inal (C) i ndi cati ng wh en t o read & store D TttTwo outputs: the value of the internal state (Q) and it's compltlement C D Q C _ Q D Q Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 13 D flip-flop Output changes only on the clock edge D D Q D Q Q D D latch latch _ _ C C Q Q C D C Q Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 14 Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1 D Q Clk D Clk Q 15 Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later Clk D Q Write Write D Clk Q 16 Clocking Methodology Combinational logggic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest tdl delay d dtetermi nes cl ock peri idod 17 Regi st er File Built using D flip -flops Read register number 1 Register 0 Register 1 M Read register u number 1 Read Read data 1 data 1 Register n – 1 x Read register Register n number 2 Register file Write Read register register number 2 Read Write data 2 data Write M u Read data 2 x Do you understand? What is the “Mux” above? Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 18 Abstraction Make sure you understand the abstractions! Sometimes it is easy to think you do, when Select you d’tdon’t A31 M Select u C31 x B31 32 A M 32 u C A30 M 32 x B u C30 x . B30 . A0 M u C0 x B0 Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 19 Regi st er File Note: we still use the real clock to determine when to write Write C 0 Register 0 1 D n-to-1 C Register number decoder Register 1 D n – 1 n C Register n – 1 D C Register n Register data D Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 20 SSpeimple Impeeaoplementation Include the functional units we need for each instruction Instruction MemWrite address PC Instruction Add Sum Address Read Instruction data 16 32 Sign memory extend Write Data data memory a. Instruction memory b. Program counter c. Adder ALU control MemRead 5 Read 3 register 1 Read a. Data memory unit b. Sign-extension unit data 1 Register 5 Read numbers register 2 Zero Registers Data ALU ALU 5 Write result register Read Write data 2 Why do we need this stuff? Data data RegWrite a. Registers b. ALU Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 21 Building a Datapath Datapath Elements that process data and addresses in the CPU Registers, ALUs, mux’s, memories, … We will build a MIPS datapath incrementally RfiiRefining th e overvi ew d esig in 22 Instruction Fetch Increment by 4 for next 32-bit instruction register 23 R-Format Instructions Read two reggpister operands Perform arithmetic/logical operation Write register result 24 Load/Store Instructions Read register operands Calculate address using 16-bit offset Use ALU, but sign-extend offset Loaddd: Read memory and dd update register Store: Write register value to memory 25 Branch Instructions Read register operands Compare operands Use ALU, subtract and check Zero output Calculate target address Sign-extend displacement Shift left 2 pp(laces (word disp lacement) Add to PC + 4 Already calculated by instruction fetch 26 Branch Instructions Just re-routes wires Sign-bit wire replicated 27 Composing the Elements First-cut data path does an instruction in one clock cycle Eac hdtpthelementh datapath element ca nonldoonen only do one function at a time Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions 28 R-Type/Load/Store Datapath 29 Full Datapath 30 Contr ol Selecting the operations to perform (ALU, read/write, etc.) Controlling the flow of data (multiplexer inputs) Information comes from the 32 bits of the instruction Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 31 Contr ol Example: add $8, $17, $18 Instruction Format: 000000 10001 10010 01000 00000 100000 op rs rt rd shamt funct ALU's operation based on instruction type and function code Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 32 Contr ol e. g., what should the ALU do with this instruction Example: lw $1, 100($2) 35 2 1 100 op rs rt 16 bit number Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 33 ALU Control ALU used for Load/Store: F = add Branch: F = subtract R-type: F depends on funct field ALU control Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR 34 ALU Control Assume 2 -bit ALUOp derived from opcode Combination al logi c de ri ve s ALU cont rol opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 R-type 10 add 100000 add 0010 subtract 100010 subtract 0110 AND 100100 AND 0000 OR 100101 OR 0001 set-on-less-than 101010 set-on-less-than 0111 35 The Main Control Unit Control signals derived from instruction R-type 0 rs rt rd shamt funct 31:2625:21 20:16 15:11 10:6 5:0 Load/ 35 or 43 rs rt address Store 31:26 25:21 20:16 15:0 Branch 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read, write for sign-extend read except R-type and add fldfor load andld load 36 Contr ol 0 M u x Add ALU 1 result Add Shift RegDst left 2 4 Branch MemRead Instruction [31– 26] MemtoReg Control ALUOp MemWrite ALUSrc RegWrite Instruction [25– 21] Read Read register 1 PC address Read Instruction [20– 16] Read data 1 Zero Instruction register 2 0 Registers ALU [31– 0] Read 0 ALU M Write data 2 result Address Read 1 Instruction register M data u M memory x u Instruction [15– 11] Write x u 1 Data x data 1 memory 0 Write data 16 32 Instruction [15– 0] Sign extend ALU control Instruction [5– 0] Memto- Reg Mem Mem Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0 R-format1 0 0 100 0 1 0 lw 0 1 1 110 0 0 0 sw X 1 X 001 0 0 0 beq X 0 XElectrical & 000 Computer Engineering 1 0 1 School of Engineering THE COLLEGE OF NEW JERSEY 37 Contr ol Simple combinational logic (truth tables) Instruction Inputs Op5 Op4 Op3 Decoding ALUOp Op2 Op1 ALU control block Op0 ALUOp0 ALUOp1 Outputs Operation2 R-format Iw sw beq F3 RegDst Operation F2 Operation1 ALUSrc F (5– 0) F1 MemtoReg Operation0 RegWrite F0 MemRead MemWrite Branch ALUOp1 ALUOpO Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 38 Our Simp le Contr ol Struc tu r e All of the logic is combinational We wait for everything to settle down, and the right thing to be done ALU might not produce “right answer ” right away we use wriillite signals along wi ihlkth clock to determine when to write Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY 39 Our Simp
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