Logic in Knowledge Representation And
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Vol. 47, No. 2 June 2018 a New Star Appears in Europe Page 14 Journal
Online PDF: ISSN 233333-9063 Vol. 47, No. 2 June 2018 Journal of the International Planetarium Society A New Star Appears in Europe Page 14 Reach for the stars... and beyond. ZEISS powerdome IV // INSPIRATION MADE BY ZEISS True Hybrid with brilliant stars and perfect renderings from a single source ZEISS powerdome IV brings many new features to your star theater: an integrated planetarium for earthbound and extraterrestrial astronomy with seamless transitions between optical and digital star fields (True Hybrid) | The universe from Earth via the solar system and Milky Way galaxy to the very edge of the observable space | Stereo projection | 8k performance | 10 bit color depth for smooth gradients | HEVC codec for efficient video renderings free of artifacts | All constellation figures, individually and in groups without any mutual overlapping | Telescope function for deep-sky imagery applying Astronomy Visualization Metadata | Complete image set of all Messier objects | Customizable polar lights, comets with gas and dust tails, and shooting stars with a great variety of parameters for location, brightness, colors and appearance | Simulation of day and night with dusk and dawn coloring of sky and panorama images | Customizable weather effects such as clouds, rain, fog, snow, rainbow, halos, air and light pollution effects | Digital rights management to secure your productions | Remote service for quick help, and much more from the only company serving planetariums for nearly a century. www.zeiss.com/planetariums zeiss-ad_pdIV_letter_x3.indd -
Live Distributed Objects
LIVE DISTRIBUTED OBJECTS A Dissertation Presented to the Faculty of the Graduate School of Cornell University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Krzysztof Jan Ostrowski August 2008 c 2008 Krzysztof Jan Ostrowski ALL RIGHTS RESERVED LIVE DISTRIBUTED OBJECTS Krzysztof Jan Ostrowski, Ph.D. Cornell University 2008 Distributed multiparty protocols such as multicast, atomic commit, or gossip are currently underutilized, but we envision that they could be used pervasively, and that developers could work with such protocols similarly to how they work with CORBA/COM/.NET/Java objects. We have created a new programming model and a platform in which protocol instances are represented as objects of a new type called live distributed objects: strongly-typed building blocks that can be composed in a type-safe manner through a drag and drop interface. Unlike most prior object-oriented distributed protocol embeddings, our model appears to be flexible enough to accommodate most popular protocols, and to be applied uniformly to any part of a distributed system, to build not only front-end, but also back-end components, such as multicast channels, naming, or membership services. While the platform is not limited to applications based on multicast, it is replication- centric, and reliable multicast protocols are important building blocks that can be used to create a variety of scalable components, from shared documents to fault-tolerant storage or scalable role delegation. We propose a new multicast architecture compatible with the model and designed in accordance with object-oriented principles such as modu- larity and encapsulation. -
Control and Cybernetics
Control and Cybernetics. VOL. 1 (1 972) No. 1/2 Finding an optimum dynamic spatial structure of information systems by LEON SLOMINSKI Polish Academy of Sciences Institute of Applied Cybernetics Warszawa In the present paper questions connected with the formulation of problems of finding optimum dynamic spatial structures of information systems are discussed in the form of integer programming problems. Possibilities of linearization of a non linear problem are indicated and the computational algorithm ARO for reduction of the original set of linear constraints is given. 1. Introduction We shall call an information system (SI) [1], a complex of technical equipment together with connecting lines and operating personnel designed for the purposes. of receiving, storing, processing, transmitting, diffusion and delivery of information. Radio-television broadcasting systems, postal and telecommunicational systems,. systems of elaboration and diffusion of scientific and technical information, systems. of computer centers, etc. may be regarded as examples of the SI. The spatial structure of systems of this type is, as a rule, clearly determined,. that is the allocation of devices and links between them are given. We shall introduce a certain classification of spatial structures of the SI. We shall call a spatial structure static if the allocation of its stations and links: between them do not change within the time interval under consideration. If we consider a developing information system in which, for example, new stations and links are built, then we say that its spatial structure is dynamic. Among all dynamic structures we distinguish those that are subject to rapid changes (reorganization, displacement) due to changes in the environment from which information is collected or to which information is delivered. -
Formal Specification and Runtime Verification of Parallel
Formal Specification and Runtime Verification of Parallel Systems using Interval Temporal Logic (ITL) PhD Thesis Nayef Hmoud Alshammari This thesis is submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Software Technology Research Laboratory De Montfort University Leicester - United Kingdom 2018 Declaration of Authorship I declare that the work described in this thesis is original work undertaken by me for the degree of Doctor of Philosophy at the Software Technology Research Laboratory (STRL), at De Montfort University, United Kingdom. No part of the material described in this thesis has been submitted for any award of any other degree or qualification in this or any other university or college of advanced education. This thesis is written by me and produced using LATEX. I To my mother’s soul, Helalah bint Hujailan Alshammari (April 21st, 2016). May she rest in peace ... II Acknowledgement Firstly, I would like to express my sincere gratitude to my first supervisor Dr. Francois Seiwe and second supervisor Dr. Antonio Cau for their continuous support of my PhD study and related research, and for their patience, motivation, and immense knowledge. Their guidance helped me during the time of my research and writing of this thesis. I could not have had more qualified supervisors for my PhD study. Also, I would like to express my great appreciation to Dr. Antonio Cau for the remarkable theoretical and practical support which he offered during the study of my PhD. I would also like to thank my former supervisors Dr. Ben Moszkowski and Dr. Jordan Dimitrov for their roles during my PhD. -
Novel Logic Synthesis Techniques for Asymmetric Logic Functions Based
NOVEL LOGIC SYNTHESIS TECHNIQUES FOR ASYMMETRIC LOGIC FUNCTIONS BASED ON SPINTRONIC AND MEMRISTIVE DEVICES by Vaibhav Vyas APPROVED BY SUPERVISORY COMMITTEE: Joseph S. Friedman, Chair Mehrdad Nourani Carl Sechen William Swartz Copyright c 2018 Vaibhav Vyas All Rights Reserved This thesis document is dedicated to my parents, Ruchi and Rakesh Vyas. NOVEL LOGIC SYNTHESIS TECHNIQUES FOR ASYMMETRIC LOGIC FUNCTIONS BASED ON SPINTRONIC AND MEMRISTIVE DEVICES by VAIBHAV VYAS, BS THESIS Presented to the Faculty of The University of Texas at Dallas in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING THE UNIVERSITY OF TEXAS AT DALLAS May 2018 ACKNOWLEDGMENTS It has been a privilege to be a part of a highly creative, intellectual and productive research group at the NanoSpinCompute Lab. Not only has it contributed to polishing my technical skills and understanding, it has helped me to harness my creativity and problem solving capabilities to their fullest extent. Undoubtedly, I owe gratitude to the people who have made this possible. I am highly grateful to my teacher, research advisor and mentor Dr. Joseph S. Friedman, for without him, none of this would have been possible. I couldn't have worked with a more intellectual, vibrant and understanding supervisor than him. He was quick to spot my interests and channelize my efforts in the most productive way possible. I am thankful to him for his encouragement and support in times of uncertainty, and for constantly making me realize my research's worth. Finally, I am grateful for his honest feedbacks that helped me stay on course. -
Interval Temporal Logic
Interval Temporal Logic Antonio Cau and Ben Moszkowski 2021-04-09 HTML version of the ITL home page Abstract Interval Temporal Logic (ITL) is a flexible notation for both propositional and first-order reasoning about periods of time found in descriptions of hardware and software systems. Unlike most temporal logics, ITL can handle both sequential and parallel composition and offers powerful and extensible specification and proof techniques for reasoning about properties involving safety, liveness and pro- jected time [134]. Timing constraints are expressible and furthermore most imperative programming constructs can be viewed as formulas in a slightly modified version of ITL [125]. Tempura provides an executable framework for developing and experimenting with suitable ITL specifications. In addi- tion, ITL and its mature executable subset Tempura [157] have been extensively used to specify the properties of real-time systems where the primitive circuits can directly be represented by a set of simple temporal formulae. In addition, Tempura has been applied to hardware simulation and other areas where timing is important. 1 Contents 1 Finite Interval Temporal Logic3 1.1 Syntax............................................3 1.2 Semantics..........................................3 1.3 Derived Constructs......................................5 1.4 Propositional proof system..................................7 1.5 First order proof system...................................7 2 Finite and Infinite Interval Temporal Logic8 2.1 Syntax............................................8 -
Lecture 3 Today's Topic: Basics of Algorithms and Complexity 1
CSE 513T Theory of Artificial Intelligence & Machine Learning Jan 20, 2015 Lecture 3 Lecturer: Brendan Juba Scribe: Tzai-Shuen Chen Today's topic: Basics of algorithms and complexity 1 Relative power of representations (Cont'd) 2 Efficient Computation: algorithms and Circuits 3 Computation Problems and NP-completeness 1 Relative power of representations (Cont'd) 1.1 recap Last time we saw the elimination algorithm for learning conjunctions (ANDs of literals, where literals are variables or negations). By using the same algorithm as a subroutine, we can also learn disjunctions (ORs of literals), i.e., given access to examples x(1); :::; x(m) drawn from a common D, and labeled by some c 2 C, c(x(1); :::; c(x(m))), the elimination algorithm would return a representation h such that Pr[c(x) = h(x)] ≥ 1 − with probability 1 − δ. The idea is to apply De Morgan's Law: l1 ^ l2 ^ ::: ^ (i) (i) (i) ln = :(:l1 _:l2 _ ::: _:ln). For each given example (x1 ; :::; xn ; b ), we give the bitwise negation (i) (i) (i) (1) (1) (:x1 ; :::; :xn ; :b ). Since there's a disjunction c such that c(x ) = b , the negated examples are labeled by a conjunction. When the conjunction h is returned from the algorithm, we flip all of the labels' polarity to get a disjunction. Since there is a 1-1 correspondence between the negated examples and the original examples, errors in the resulting disjunction are made with the same probability as they would for the conjunction. Therefore, the bound on the error made by the conjunction of negated examples translates directly into a bound on the error of the disjunction. -
Interval Temporal Logic
Interval Temporal Logic Antonio Cau, Ben Moszkowski and Hussein Zedan Software Technology Research Laboratory December 6, 2007 HTML version of the ITL home page ITL-course: A not so short introduction to ITL Abstract Interval Temporal Logic (ITL) is a flexible notation for both propositional and first-order reasoning about periods of time found in descriptions of hardware and software systems. Unlike most temporal logics, ITL can handle both sequential and parallel composition and offers powerful and extensible specification and proof techniques for reasoning about properties involving safety, liveness and projected time[15]. Timing constraints are expressible and furthermore most imperative pro- gramming constructs can be viewed as formulas in a slightly modified version of ITL [25]. Tempura provides an executable framework for developing and experimenting with suitable ITL specifications. In addition, ITL and its mature executable subset Tempura [9] have been extensively used to specify the properties of real-time systems where the primitive circuits can directly be represented by a set of simple tempo- ral formulae. In addition, various researchers have applied Tempura to hardware simulation and other areas where timing is important. 1 Syntax The key notion of ITL is an interval. An interval σ is considered to be a (in)finite sequence of states σ0; σ1 :::, where a state σi is a mapping from the set of variables Var to the set of values V al. The length jσj of an interval σ0 : : : σn is equal to n (one less than the number of states in the interval (this has always been a convention in ITL), i.e., a one state interval has length 0). -
Asynchronous Genetic Circuit Design
ASYNCHRONOUS GENETIC CIRCUIT DESIGN by Tramy T Nguyen A dissertation submitted to the faculty of The University of Utah in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical and Computer Engineering The University of Utah December 2019 Copyright c Tramy T Nguyen 2019 All Rights Reserved The University of Utah Graduate School STATEMENT OF DISSERTATION APPROVAL The dissertation of Tramy T Nguyen has been approved by the following supervisory committee members: Chris J. Myers , Chair(s) August 29, 2019 Date Approved Kenneth Stevens , Member August 29, 2019 Date Approved Priyank Kalla , Member August 29, 2019 Date Approved Tara Deans , Member August 29, 2019 Date Approved Nicholas Roehner , Member September 04, 2019 Date Approved by Florian Solzbacher , Chair/Dean of the Department/College/School of Electrical and Computer Engineering and by David B. Kieda , Dean of The Graduate School. ABSTRACT Synthetic biology is applying engineering concepts to biological processes to enable genetic circuit designs, among other applications. As more biological parts are being discovered, it is vital to have an automated procedure to allow complex circuit designs to be built. Technology mapping is a set of procedures that maps biological components to a design specification. Current technology mapping frameworks for genetic circuits are used to design combinational circuits. This dissertation illustrates the process of building an automated workflow for a technology mapping framework to design asynchronous sequential genetic circuits. An automated process to create a library of gates for logic and memory circuits is described to construct gates from DNA parts retrieved from a standardize data repository. -
Examining Surprise Billing: Protecting Patients from Financial Pain Hearing
EXAMINING SURPRISE BILLING: PROTECTING PATIENTS FROM FINANCIAL PAIN HEARING BEFORE THE SUBCOMMITTEE ON HEALTH, EMPLOYMENT, LABOR, AND PENSIONS COMMITTEE ON EDUCATION AND LABOR U.S. HOUSE OF REPRESENTATIVES ONE HUNDRED SIXTEENTH CONGRESS FIRST SESSION HEARING HELD IN WASHINGTON, DC, APRIL 2, 2019 Serial No. 116–14 Printed for the use of the Committee on Education and Labor ( Available via the World Wide Web: www.govinfo.gov or Committee address: https://edlabor.house.gov U.S. GOVERNMENT PUBLISHING OFFICE 36–589PDF WASHINGTON : 2019 VerDate Mar 15 2010 11:59 Nov 19, 2019 Jkt 000000 PO 00000 Frm 00001 Fmt 5011 Sfmt 5011 C:\USERS\NWILLIAMS\ONEDRIVE - US HOUSE OF REPRESENTATIVES\DESKTOP\3658 EDL-011-D with DISTILLER COMMITTEE ON EDUCATION AND LABOR ROBERT C. ‘‘BOBBY’’ SCOTT, Virginia, Chairman Susan A. Davis, California Virginia Foxx, North Carolina, Rau´ l M. Grijalva, Arizona Ranking Member Joe Courtney, Connecticut David P. Roe, Tennessee Marcia L. Fudge, Ohio Glenn Thompson, Pennsylvania Gregorio Kilili Camacho Sablan, Tim Walberg, Michigan Northern Mariana Islands Brett Guthrie, Kentucky Frederica S. Wilson, Florida Bradley Byrne, Alabama Suzanne Bonamici, Oregon Glenn Grothman, Wisconsin Mark Takano, California Elise M. Stefanik, New York Alma S. Adams, North Carolina Rick W. Allen, Georgia Mark DeSaulnier, California Francis Rooney, Florida Donald Norcross, New Jersey Lloyd Smucker, Pennsylvania Pramila Jayapal, Washington Jim Banks, Indiana Joseph D. Morelle, New York Mark Walker, North Carolina Susan Wild, Pennsylvania James Comer, Kentucky Josh Harder, California Ben Cline, Virginia Lucy McBath, Georgia Russ Fulcher, Idaho Kim Schrier, Washington Van Taylor, Texas Lauren Underwood, Illinois Steve Watkins, Kansas Jahana Hayes, Connecticut Ron Wright, Texas Donna E. -
Formal Requirement Elicitation and Debugging for Testing and Verification of Cyber-Physical Systems
Formal Requirement Elicitation and Debugging for Testing and Verification of Cyber-Physical Systems Adel Dokhanchi∗, Bardh Hoxhay, and Georgios Fainekos∗ ∗School of Computing, Informatics and Decision Systems Arizona State University, Tempe, AZ, U.S.A. Email: fadokhanc,[email protected] yDepartment of Computer Science, Southern Illinois University, Carbondale, IL, U.S.A. Email: [email protected] Abstract A framework for the elicitation and debugging of formal specifications for Cyber-Physical Systems is presented. The elicitation of specifications is handled through a graphical interface. Two debugging algorithms are presented. The first checks for erroneous or incomplete temporal logic specifications without considering the system. The second can be utilized for the analysis of reactive requirements with respect to system test traces. The specification debugging framework is applied on a number of formal specifications collected through a user study. The user study establishes that requirement errors are common and that the debugging framework can resolve many insidious specification errors1. I. INTRODUCTION Testing and verification of Cyber-Physical Systems (CPS) is important due to the safety critical applications of CPS such as medical devices and transportation systems. It has been shown that utilizing formal specifications can lead to improved testing and verification [24], [32], [45], [33]. However, developing formal specifications using logics is a challenging and error prone task even for experts who have formal mathematical training. Therefore, in practice, system engineers usually define specifications in natural language. Natural language is convenient to use in many stages of system development, but its inherent ambiguity, inaccuracy and inconsistency make it unsuitable for use in defining specifications. -
Reversibility of Executable Interval Temporal Logic Specifications
REVERSIBILITY OF EXECUTABLE INTERVAL TEMPORAL LOGIC SPECIFICATIONS ∗ APREPRINT Antonio Cau Stefan Kuhn Cyber Technology Institute, Cyber Technology Institute, School of Computer Science and Informatics, School of Computer Science and Informatics, Faculty of Computing, Engineering and Media Faculty of Computing, Engineering and Media De Montfort University, Leicester, UK De Montfort University, Leicester, UK [email protected] [email protected] James Hoey School of Informatics, University of Leicester, Leicester, UK [email protected] May 10, 2021 ABSTRACT In this paper the reversibility of executable Interval Temporal Logic (ITL) specifications is investi- gated. ITL allows for the reasoning about systems in terms of behaviours which are represented as non-empty sequences of states. It allows for the specification of systems at different levels of ab- straction. At a high level this specification is in terms of properties, for instance safety and liveness properties. At concrete level one can specify a system in terms of programming constructs. One can execute these concrete specification, i.e., test and simulate the behaviour of the system. In this paper we will formalise this notion of executability of ITL specifications. ITL also has a reflection operator which allows for the reasoning about reversed behaviours. We will investigate the reversibility of executable ITL specifications, i.e., how one can use this reflection operator to reverse the concrete behaviour of a particular system. Keywords Interval Temporal Logic · Time Reversion · Program Reversion · Reversible Computing. 1 Introduction Formal methods have been used in computer science to verify desirable and undesirable properties of programs. One arXiv:2105.03375v1 [cs.FL] 7 May 2021 type of formalism introduced is temporal logic.