Formal Specification and Runtime Verification of Parallel
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Formal Specification and Runtime Verification of Parallel Systems using Interval Temporal Logic (ITL) PhD Thesis Nayef Hmoud Alshammari This thesis is submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Software Technology Research Laboratory De Montfort University Leicester - United Kingdom 2018 Declaration of Authorship I declare that the work described in this thesis is original work undertaken by me for the degree of Doctor of Philosophy at the Software Technology Research Laboratory (STRL), at De Montfort University, United Kingdom. No part of the material described in this thesis has been submitted for any award of any other degree or qualification in this or any other university or college of advanced education. This thesis is written by me and produced using LATEX. I To my mother’s soul, Helalah bint Hujailan Alshammari (April 21st, 2016). May she rest in peace ... II Acknowledgement Firstly, I would like to express my sincere gratitude to my first supervisor Dr. Francois Seiwe and second supervisor Dr. Antonio Cau for their continuous support of my PhD study and related research, and for their patience, motivation, and immense knowledge. Their guidance helped me during the time of my research and writing of this thesis. I could not have had more qualified supervisors for my PhD study. Also, I would like to express my great appreciation to Dr. Antonio Cau for the remarkable theoretical and practical support which he offered during the study of my PhD. I would also like to thank my former supervisors Dr. Ben Moszkowski and Dr. Jordan Dimitrov for their roles during my PhD. Special deep thanks and appreciation to those who have endlessly and continuously believed in me and supported me especially my great sisters, Loulouah and Khaznah, and my best friend Dr. Dheidan Alshammari. Big thanks to my family, my friends and all those who have been relentlessly supportive during my PhD journey. III Abstract Runtime Verification (RV) is the discipline that allows monitoring systems at runtime in order to check the satisfaction or violation of a given correctness property. Parallel systems are more complicated than sequential systems. Therefore, systems that run in parallel need a parallel runtime verification framework to monitor their behaviour and guarantee correctness properties. Parallel systems have correctness properties different from correctness properties of sequential systems. For instance, as a correctness property of parallel systems, absence of deadlock has to be guaranteed and mutual exclusion mechanism has to be applied in case a resource is shared be- tween more than one system and the parallelism form is true concurrency. Therefore, sequential runtime verification framework can not handle systems that run in parallel due to the singularity issue of this kind of framework as they are built to handle a single system at a time, whereas for parallel systems a framework has to handle many systems at a time. AnaTempura is a runtime verification tool which can handle single systems at a time. To solve this problem, I evolved AnaTempura to be able to handle parallel systems. In this thesis, I propose a Parallel Runtime Verification Framework (PRVF) that can handle systems which use architectures of parallelism in their design such as multi-core processor architecture. The proposed model can check system behaviour at runtime in order to either guarantee satisfaction or detect violations of correctness properties. My technique is based on Interval Temporal Logic (ITL) and its executable subset Tempura to verify properties at runtime using the AnaTempura tool. I use, as a demonstration, the case study of private L2 cache memory of multi-core proces- sor architecture. My objectives are to i) design MSI protocol compliant with cache memory IV coherence and ii) fulfil main memory consistency model at runtime. I achieve this via a for- mal Tempura specification of the cache controller which is then verified at runtime against my objectives for memory consistency and cache coherence using AnaTempura. The presented spec- ifications allow to extend it allow to extend it to not only capture correctness but also monitor the performance of a cache memory controller. The case study is then evaluated via integrating AnaTempura with MATLAB in order to check correctness properties such as memory consis- tency and cache coherence. V Contents Declaration of AuthorshipI Acknowledgments III AbstractIV List of Figures XII List of Tables XVII List of Abbreviations XVIII 1 Introduction1 1.1 Background.....................................2 1.2 Problem Statement and Research Motivation....................3 1.3 Research Questions.................................6 1.4 Research Methodology...............................6 1.5 Success Criteria...................................8 1.6 Thesis Outline....................................9 2 Verification Techniques for Parallel Systems: a Review 11 2.1 Introduction..................................... 12 2.2 Basic Concepts and Related Topics......................... 12 VI CONTENTS 2.2.1 Concurrency versus Parallelism...................... 12 2.2.2 Parallel-Concurrent Programming Models in Java............. 13 2.2.3 Modern Central Processing Units (CPUs)................. 15 2.2.4 Petri Net.................................. 16 2.2.5 Global State Construction......................... 17 2.2.6 Parallel Programming Models....................... 18 2.2.6.1 Shared Memory......................... 19 2.2.6.2 Message Passing......................... 19 2.2.6.3 Shared Memory versus Message Passing............ 20 2.3 Verification Techniques............................... 20 2.4 Runtime Verification................................ 21 2.4.1 Monitors.................................. 23 2.4.2 Taxonomy................................. 23 2.4.3 Runtime Verification versus Model Checking............... 26 2.4.4 Runtime Verification versus Testing.................... 26 2.4.5 The Use of Runtime Verification...................... 27 2.4.6 Existing Runtime Verification Frameworks................ 28 2.4.6.1 EAGLE............................. 28 2.4.6.2 J-LO............................... 28 2.4.6.3 LARVA............................. 29 2.4.6.4 LogScope............................ 29 2.4.6.5 LoLa............................... 30 2.5 Formal Methods-Based Tools for Parallel Systems................. 30 2.6 Temporal Logic................................... 31 2.6.1 Point-Based versus Interval-Based Structure of Temporal Logics..... 32 2.6.2 Interval Temporal Logic (ITL)....................... 33 VII CONTENTS 2.6.2.1 Syntax.............................. 34 2.6.2.2 Informal Semantics....................... 35 2.6.2.3 Justification for Choosing Interval Temporal Logic (ITL)... 36 2.7 Related Work.................................... 37 2.7.1 Memory Models for Interval Temporal Logic (ITL)............ 37 2.7.1.1 Framing Variables........................ 37 2.7.1.2 Transactional Memory...................... 38 2.7.2 Meltdown and Spectre........................... 40 2.8 Summary...................................... 41 3 Computational Model 42 3.1 Introduction..................................... 43 3.2 Computational Model................................ 43 3.2.1 Message-Passing based Communication.................. 43 3.2.1.1 Related Work.......................... 44 3.2.1.2 Execution Modes........................ 45 3.2.1.3 Channel Communication.................... 45 3.2.1.4 Shunt Communication...................... 47 3.2.1.5 Delay and Timeout....................... 48 3.2.1.6 Resource Allocation....................... 48 3.2.1.7 The Funnel............................ 48 3.2.2 Shared-Variable based Communication.................. 49 3.2.3 True Concurrency............................. 50 3.2.4 Interleaving Concurrency.......................... 51 3.3 Architecture Framework.............................. 53 3.3.1 Generation Phase.............................. 53 VIII CONTENTS 3.3.1.1 Communication Models..................... 54 3.3.1.2 Concurrency Forms....................... 54 3.3.1.3 Execution Modes........................ 54 3.3.2 Locals Verification & Assertion Phase................... 56 3.3.2.1 Interleaving Concurrency and Shared-Variable......... 56 3.3.2.2 True Concurrency and Shared-Variable............. 58 3.3.2.3 Synchronous Execution and Message-Passing (Channels)... 60 3.3.2.4 Asynchronous Execution and Message-Passing (Shunts).... 62 3.3.3 Global Verification Phase.......................... 65 3.4 Parallel Runtime Verification Framework (PRVF) Model............. 66 3.5 Summary...................................... 66 4 Design and Implementation of a Parallel Runtime Verification Framework (PRVF) 68 4.1 Introduction..................................... 69 4.2 (Ana)Tempura.................................... 69 4.2.1 Assertion Points.............................. 71 4.2.2 The Monitor................................ 76 4.2.3 Tempura Interpreter............................ 77 4.3 Evolutionary Improvements of AnaTempura.................... 77 4.3.1 Realisation of Assertion Points Techniques................ 80 4.4 Benchmarking Applications............................ 90 4.4.1 Producer-Consumer............................ 90 4.4.2 Dining Philosophers Problem....................... 92 4.5 Summary...................................... 93 5 Case Study: Cache Controller 94 5.1 Cache Memory Controller: A Case Study..................... 95 IX CONTENTS 5.2 The Basics of Cache Memory............................ 95 5.2.1