DOCSLIB.ORG

Linking Mixed-Signal Design and Test

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Linking Mixed-Signal Design and Test Linking Mixed-Signal Design and Test Generation and Evaluation of Specification-Based Tests Nur Engin Samenstelling promotiecommissie: Voorzitter: Prof.dr. W.E. van der Linden, Universiteit Twente Secretaris: Prof.dr. W.E. van der Linden, Universiteit Twente Promotor: Prof.dr. H. Wallinga, Universiteit Twente Ass. Promotor: Dr.ir. H.G. Kerkhoff, Universiteit Twente Referent: Dr.-Ing. M.J. Ohletz, Alcatel Microelectronics Leden: Prof.dr.ir. B. Nauta, Universiteit Twente Prof.dr.ir. T. Krol, Universiteit Twente Prof.dr.ir. W.M.G. van Bokhoven, TU Eindhoven Prof.dr.ir. J.L. Huertas Diaz, University of Sevilla Title: Linking Mixed-Signal Design and Test Generation and Evaluation of Specification-Based Tests Author: Nur Engin ISBN: 90-3651494-0 Printed by Febodruk B.V., Enschede c N. Engin 2000 LINKING MIXED-SIGNAL DESIGN AND TEST GENERATION AND EVALUATION OF SPECIFICATION-BASED TESTS PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof. dr. F.A. van Vught, volgens besluit van het College van Promoties in het openbaar te verdedigen op vrijdag 29 september 2000 te 16.45 uur. door Nur Engin geboren op 16 september 1970 te Ankara (Turkije) Dit proefschrift is goedgekeurd door de promotor, Prof. dr. H. Wallinga, en de assistent promotor, Dr. ir. H.G. Kerkhoff. Was man nicht versteht, besitzt man nicht. GOETHE Contents Summary vii Acknowledgments ix Symbols xi Abbreviations xiii 1 Introduction 1 1.1 Testing: The Hidden Challenge ................ 2 1.2 Analog and Mixed-Signal Testing ............... 3 1.2.1 Analog vs Digital Testing ............... 3 1.2.2 Analog/Mixed-Signal Challenges ........... 5 1.3 Motivation and Problem Definition .............. 9 1.4 Outline ............................. 11 1.5 Bibliography .......................... 13 2 The Mixed-Signal Test Problem 15 2.1 Introduction ........................... 15 2.2 Mixed-Signal IC Architectures ................ 16 2.3 Current Design and Test Practice ............... 18 2.3.1 Prototype Test ..................... 18 2.3.2 Production Test .................... 20 2.4 Market Requirements ..................... 24 2.4.1 Quality ......................... 24 i 2.4.2 Cost ........................... 28 2.4.3 Time-to-Market ..................... 30 2.5 Mixed-Signal Test: Current Issues and Challenges ..... 31 2.5.1 Test and Measurement Environments ........ 31 2.5.2 Design for Testability (DfT) .............. 32 2.5.3 Built-in Self-Test (BIST) ............... 33 2.5.4 Automatic Test Program Generation (ATPG) .... 35 2.5.5 Test Program Evaluation ............... 37 2.6 Trends in Mixed-Signal IC Design .............. 38 2.7 Trends in IC Technology .................... 40 2.8 Design-Test Link ........................ 40 2.9 Conclusions ........................... 42 2.10 Bibliography .......................... 42 3 A General Framework for Mixed-Signal Test Generation and Testing 49 3.1 Introduction ........................... 49 3.2 Design and Test Flow: The Current Status ......... 50 3.3 High-Level Considerations ................... 51 3.4 Macro-Level Considerations .................. 56 3.5 Simulation Support for Test .................. 58 3.5.1 Simulation-Based Test Generation .......... 58 3.5.2 Virtual Testing ..................... 60 3.6 Reuse Issues in Design and Test ................ 63 3.7 State of the Art in Design-Test Link ............. 63 3.7.1 Virtual Test Software ................. 64 3.7.2 Test Plan Generation Tools .............. 65 3.7.3 Test Program Evaluation Tools ............ 66 3.8 A General Framework for Design-Test Link ......... 66 3.8.1 Definitions ....................... 68 3.8.2 Design and Test Methodology ............. 69 3.9 Conclusions ........................... 71 3.10 Bibliography .......................... 71 ii 4 MISMATCH: A Framework for Design-Test Link 75 4.1 System Overview ........................ 75 4.2 Integrated Design and Test Flow ............... 77 4.3 Test Database .......................... 77 4.4 Design for Testability ..................... 80 4.5 Design Database ........................ 81 4.6 MISMATCH CAD Data Flow ................. 82 4.6.1 Usage of Simulation Results .............. 83 4.6.2 Test Set Selection ................... 86 4.7 MISMATCH CAT Data Flow ................. 88 4.7.1 Test Control Signal Generation ............ 90 4.7.2 Automatic Routing for the Test Set ......... 90 4.7.3 Test Generation for Mixed-Signal Macros ...... 92 4.7.4 Test Generation for Digital Macros .......... 93 4.8 An Example: Design and Test of a Compass Watch ..... 94 4.8.1 IC Overview ...................... 94 4.8.2 Analog Functionality and the Test Library ..... 96 4.9 Test Results ........................... 105 4.9.1 Digital Parts ...................... 105 4.9.2 Analog Parts ...................... 107 4.10 Discussion of Experiences ................... 108 4.11 Conclusions ........................... 110 4.12 Bibliography .......................... 112 5 Defect-Oriented Test Evaluation for Analog Blocks 115 5.1 Introduction ........................... 115 5.2 General Test Selection Criteria ................ 116 5.3 Specification Coverage vs. Fault Coverage .......... 116 5.4 Manufacturing Defects and IC Faults ............. 118 5.5 Layout Based Fault List Extraction .............. 121 5.5.1 Critical Area ...................... 121 5.5.2 Fault Probability Calculations ............ 122 5.6 Analog Fault Simulation as a Test Evaluation Method ... 124 5.7 Problem Definition ....................... 125 iii 5.8 Standard Methods in Circuit Simulation ........... 127 5.9 Simulation Complexity ..................... 132 5.9.1 Evaluation of Device Models ............. 134 5.9.2 Solution of Linear Equations ............. 135 5.9.3 Number of NR Iterations ............... 135 5.10 Fault Simulation: Overview of Existing Methods ...... 137 5.10.1 Methods for Linear Circuits .............. 139 5.10.2 Methods for Solving Sets of Linear Equations... ... 139 5.10.3 Other Methods ..................... 148 5.11 Conclusion ........................... 149 5.12 Bibliography .......................... 151 6 A New Approach Towards Analog Fault Simulation 155 6.1 Introduction ........................... 155 6.2 Simulator Requirements .................... 156 6.3 DC-Bias Grouping ....................... 157 6.4 One-Step Relaxation Method ................. 163 6.5 Grouping Methods ....................... 165 6.6 Partial LU Update ....................... 166 6.7 Parallel Simulation ....................... 170 6.8 Implementation and Results .................. 170 6.9 Conclusions and Future Research ............... 178 6.10 Bibliography .......................... 180 7 Conclusions and Recommendations 185 7.1 Summary of Results ...................... 185 7.2 Original Contributions of This Thesis ............ 187 7.3 Recommendations ....................... 187 Appendices 189 A Example of a Virtual Instrument 191 A.1 Front Panel ........................... 191 A.2 Diagram ............................. 192 iv B Mixed-Signal Test System: An Overview 195 B.1 Digital Tester Part ....................... 195 B.2 Analogue Tester Part ...................... 196 B.3 Bibliography .......................... 197 C Verification Test Results for the Compass Watch Buffer Macro 199 Samenvatting 201 About the Author 203 v vi Summary The work described in this thesis is aimed at the exploration of new methods for the integration of design and test development procedures for mixed- signal integrated circuits (IC's). Mixed-signal IC's are currently found in many electronic systems, including telecommunications, audio and video instruments, automotive parts, etc. The testing of these IC's presents problems due to the complex nature of analog functionality and the non- automated analog design process. Automatic generation of test programs for analog parts is a problem which is not yet fully solved. Once a test is generated, formal methods to ensure the quality of developed tests do not exist or have a large overhead. Systematic links between design and test development processes of analog and mixed-signal circuits are required to improve these points and to ensure high quality and low time-to-market (TTM) for mixed-signal IC's. The various aspects of the mixed-signal test problem are discussed in chap- ter 2 of this thesis. A general discussion of the present mixed-signal design and test practice, the implications of market requirements on the test methodology, and the future challenges for mixed-signal testing is pre- sented. It has been concluded that long test development and debugging time and lack of methods for realistic test evaluation are the main chal- lenges in mixed-signal testing at present. The discussions in chapter 3 are aimed at defining a general framework for the integration of mixed-signal design and test activities along the IC development traject. For this, the test considerations at various levels of abstraction are given, and the present state of the art and possibilities in virtual testing and design-test link tools are presented. At the end of this chapter, a general framework for linking mixed-signal design and test is presented. In chapter 4, an environment for the integration of design and test flows for the prototype test of mixed-signal IC's is introduced and implemented. The described environment (MISMATCH) is based on the sharing of de- sign data with the test environment for generation of specification-based vii prototype tests during the design steps. The functionality consists of the selection of test methods
Load more

Recommended publications
  • Fund Commentary (PDF)
    SECOND QUARTER 2021 INVESTMENT COMMENTARY Share Class A Advisor C Institutional Institutional 2 Institutional 3 R Symbol SLMCX SCIOX SCICX CCIZX SCMIX CCOYX SCIRX Overall Morningstar RatingTM Columbia Seligman Technology and Class A Institutional Class Information Fund The Morningstar Rating is for the indicated Effective June 9, 2021, Columbia Seligman Communications and Information Fund was renamed the share classes only as of 06/30/21; other classes Columbia Seligman Technology and Information Fund to better represent the universe in which the fund may have different performance characteristics. The Morningstar ratings for the overall, invests. three-, five- and 10-year periods for Class A shares are 4 stars, 5 stars, 4 stars and 3 Fund performance stars and for Institutional Class shares are 4 ▪ Institutional Class shares of Columbia Seligman Technology and Information Fund stars, 5 stars, 4 stars and 4 stars among 215, 215, 182 and 157 Technology funds returned 9.62% for the second quarter. respectively, and are based on a Morningstar Risk-Adjusted Return measure. ▪ The fund’s benchmark, the S&P North American Technology Sector Index, returned 12.29% for the quarter. With a return to work focus ▪ For monthly performance, please visit columbiathreadneedle.com. prompting increases in office IT spending, we think our Market overview companies are well The U.S. stock market gained 8.54% in the second quarter, as gauged by the Russell 1000 Index, bringing its year-to-date return to 14.95%. This marked the fifth consecutive positioned for the coming calendar quarter of positive returns for the index, underscoring the strength in market earnings deluge.
    [Show full text]
  • Sunday, April 27, 2014 - Teradyne Users Group
    Sunday, April 27, 2014 - Teradyne Users Group 4:00-6:00 p.m. Conference Check-In / Welcome Reception Monday, April 28, 2014 - Teradyne Users Group 7:30-8:30 a.m. Breakfast 8:30-9:00 a.m. Welcome 9:00-10:00 a.m. Keynote Address 10:00-10:30 a.m. Break TEST INFRASTRUCTURE POWER MANAGEMENT 10:30 a.m.–12:00 p.m. MIXED SIGNAL RF WIRELESS DIGITAL ILO TRAINING AND PRODUCTION AND AUTOMOTIVE IG-Link: Stop Merging and Keeping All the Cores Busy – Dynamic Error Vector Measuring Switching Need more time? Follow the Pin Margin Tool & IG-XL Start Linking - Roy Chorev & How to Multithread with IG-XL - Magnitude (DEVM) Test for RF Characteristics With or fat rabbit! A Way to Spot and V8.20.00 - Paul Picarski & Keith Mike Patnode Teradyne; Stephen Hlotyak, Teradyne (3) Power Amplifiers (PA) and Without QTMU? - Maciej Miler, Eliminate Time-Wasting Code Thomas, Teradyne (170) Michael Back, Qualcomm (1) Front-End-Modules (FEM) on Texas Instruments; Jozef in Eagle EV & MST Test the ETS-88 RF - Stephen Molnar, Teradyne (38) Programs - Ingo Wahl, 10:30-11:00 a.m. Lyons, Aik-Moh Ng & Guillermo Teradyne (96) Pidal, Teradyne; Paul Chen, Aeroflex (19) IG-Diff - You changed what? - Implementing Concurrent Test Reducing EVM Error Through Tips for Successful Pattern High Accuracy Wafer Level Roy Chorev, Holly Wang & Ying- on a Mixed Signal Device - Traditional Device Calibration Conversion to Eagle DPU16 - RDS(on) Measurement Can Wei, Teradyne (2) Xiaorong Song, Freescale (136) and Error Correction by ESA Chiau-Woon Yeo, Teradyne Techniques - Jack Weimer, 11:00-11:30 a.m.
    [Show full text]
  • The Semiconductor Supply Chain: Assessing National Competitiveness
    January 2021 The Semiconductor Supply Chain: Assessing National Competitiveness CSET Issue Brief AUTHOR Saif M. Khan Alexander Mann Dahlia Peterson Table of Contents Executive Summary ............................................................................................... 3 Introduction and Overview .................................................................................. 5 Research and Development ............................................................................... 12 Production ............................................................................................................ 14 Design ........................................................................................................................ 15 Fabrication ................................................................................................................. 19 Assembly, Testing, and Packaging .......................................................................... 23 Semiconductor Manufacturing Equipment ....................................................... 25 Wafer Manufacturing, Wafer Marking, and Handling ......................................... 26 Ion Implanters ............................................................................................................ 28 Lithography ................................................................................................................ 30 Deposition .................................................................................................................
    [Show full text]
  • All About No Failures Systems and Test Solutions
    13th May 2019 ‘HARDMAN PREPARED THIS DOCUMENT PURSUANT TO AN ENGAGEMENT LETTER ENTERED INTO WITH BPER’ Description ELES is an Italian Innovative SME that ELES operates in the Microelectronics Testing systems sector, providing the semiconductor industry with reliability All about no failures systems and test solutions. With reliabi ELES is well positioned within the semiconductor testing market, proposing an innovative Company information test approach, with a good competitive position, long-term client relationships and a CEO Francesca Zaffarami solid financial standing. The Group is seeking to raise around €10m: €5-€6m through new CFO To be appointed primary shares, €0.9m through potential secondary shares and around €3m from existing Chairman Antonio Zaffarami shareholder (Gepafin) sales – to accelerate its growth process. +39 075 89800166 www.eles.com ► Competitive position: ELES, serving clients in the semiconductor industry, is a leading player in its market segment, has long-term relationships with its principal customers, and is present in the Silicon Valleys of America, Asia and Israel. The ELES offer is composed of Test System (machines) and Test Application (Boards & Value-Added Services). ► Strategy: ELES offers an innovative design level test approach, based on DFT and BiST, and supports its clients in improving the reliability of its products via early co-engineering (at design phase) in order to achieve the primary goal for the semiconductor industry, to then achieve Zero Defect Results and excellence. ► Financials/valuation: ELES compares favourably with its closest competitive peer group in terms of the most common financial metrics. Our medium-term financial forecasts suggest sales growth of around 12% p.a.
    [Show full text]
  • Vanguard Russell 1000 Index Funds Annual Report August 31, 2020
    Annual Report | August 31, 2020 Vanguard Russell 1000 Index Funds Vanguard Russell 1000 Index Fund Vanguard Russell 1000 Value Index Fund Vanguard Russell 1000 Growth Index Fund See the inside front cover for important information about access to your fund’s annual and semiannual shareholder reports. Important information about access to shareholder reports Beginning on January 1, 2021, as permitted by regulations adopted by the Securities and Exchange Commission, paper copies of your fund’s annual and semiannual shareholder reports will no longer be sent to you by mail, unless you specifically request them. Instead, you will be notified by mail each time a report is posted on the website and will be provided with a link to access the report. If you have already elected to receive shareholder reports electronically, you will not be affected by this change and do not need to take any action. You may elect to receive shareholder reports and other communications from the fund electronically by contacting your financial intermediary (such as a broker-dealer or bank) or, if you invest directly with the fund, by calling Vanguard at one of the phone numbers on the back cover of this report or by logging on to vanguard.com. You may elect to receive paper copies of all future shareholder reports free of charge. If you invest through a financial intermediary, you can contact the intermediary to request that you continue to receive paper copies. If you invest directly with the fund, you can call Vanguard at one of the phone numbers on the back cover of this report or log on to vanguard.com.
    [Show full text]
  • Insights on Teradyne's Forecasting and System Dynamics
    Forecasting ATE sales at Teradyne, Inc. May 13, 2004 Kapil Dev Singh, Torben Thurow, and Truman Bradley 1 Agenda • Teradyne’s business • Problem statement • Process comparison and analysis – Teradyne’s forecasting process – System Dynamics process • Conclusions and insights •Next steps 2 Teradyne • Manufactures and sells equipment that automatically tests semiconductors – Used in wafer sort operations and – Final testing after packaging • Major customers include Intel, Motorola, Texas Instruments, Analog Devices, TSMC Semiconductor Capex 2 1.5 1 0.5 0 3 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 Problem Statement • Teradyne sees dramatic cyclicality in its orders and struggles to efficiently adjust production to meet demand. 4 Teradyne’s forecasting process • Size of ATE market correlated with total semiconductor market size • Historically, Constant buy rate – ATE market = 2.5% * semi market – Size of semiconductor market based on external forecasts • Recent data departs from historical trends • Sales team provides input for market share estimates and short term forecasting based on customer input 5 Reference Mode Breakdown • Growth in market t e Hope k size Mar r o ct u d con i • Oscillation in m e Fear S market size 1990 now 2020 • Increasing t e k amplitude of r a Hope oscillation in market tor M nduc o mic Se size Fear 1990 now 2020 6 Momentum Policies •Internal – Temporary employment – Expandable and contractable capacity – Long customer lead times (order to receipt) – Surge capacity – Shorten component lead times • External
    [Show full text]
  • 2021 Annual Report
    MARCH 31, 2021 2021 Annual Report iShares Trust • iShares Russell Top 200 ETF | IWL | NYSE Arca • iShares Russell Top 200 Growth ETF | IWY | NYSE Arca • iShares Russell Top 200 Value ETF | IWX | NYSE Arca • iShares Russell 1000 ETF | IWB | NYSE Arca • iShares Russell 1000 Growth ETF | IWF | NYSE Arca • iShares Russell 1000 Value ETF | IWD | NYSE Arca • iShares Russell 2000 ETF | IWM | NYSE Arca • iShares Russell 2000 Growth ETF | IWO | NYSE Arca • iShares Russell 2000 Value ETF | IWN | NYSE Arca The Markets in Review Dear Shareholder, The 12-month reporting period as of March 31, 2021 reflected a remarkable period of disruption and adaptation, as the global economy dealt with the implications of the coronavirus (or “COVID-19”) pandemic. As the period began, the response to the virus’s spread was well underway, and countries around the world instituted economically disruptive countermeasures. Stay-at-home orders and closures of non-essential businesses became widespread, many workers were laid off, and unemployment claims spiked, causing a global recession and a sharp fall in equity prices. As April 2020 began, stocks were near their lowest point since the beginning of the pandemic. However, a steady recovery began, as businesses started re-opening and governments learned to adapt to life with the virus. Equity prices continued to rise throughout the summer, fed by strong fiscal and monetary Rob Kapito support and improving economic indicators. Many equity indices neared or surpassed all-time highs late President, BlackRock, Inc. in the reporting period following the implementation of mass vaccination campaigns and passage of an additional $1.9 trillion of fiscal stimulus.
    [Show full text]
  • LASAR Models Catalog
    ASTER - LASAR models catalog ASTER - LASAR models catalog....................................................................................................................................1 SSI-MSI Devices Library.................................................................................................................................................2 RAM Devices library .......................................................................................................................................................3 MSI-LSI Devices Library.................................................................................................................................................4 Hardware models..............................................................................................................................................................5 PROM-MAKER – LASAR models from PROM devices..............................................................................................10 XILLAS – LASAR models for XILINX devices ...........................................................................................................11 ACT2LAS – LASAR models for ACTEL devices.........................................................................................................11 LSI2LAS – LASAR models for LSI Logic devices .......................................................................................................11 The ASTER models library and modeling tools are designed to be compatible with TERADYNE LASAR
    [Show full text]
  • ST Template WORD
    CURRICULUM VITAE Personal information Name Filippo La Vecchia Photo Permanent Address Phone E-mail [email protected] Nationality Italian Date of birth Employee for Italian government as “IT public official”. I’m currently in charge for the “Agency of Territorial Cohesion”, a new agency of the Italian government whose Oct 2016 - today activity is oriented to the implementation and actuation of UE programs. So my duty and responsibility is to represent the Italian state as national authority and check and verify that the resources coming from the UE are well allocated in all the projects related to the European International Cooperation . I’m involved in the following CTE Programs inside the Monitoring Commitees and the National Committees: Interreg Central Europe, Interreg Alpine Space, Interreg Italy-Slovenija, Espon Employee at ST Microelectronics C a t a n ia as Product Engineer. Jul 2000 – Sep 2016 In charge as Product Engineer in MCD, Microcontroller division. I’m following STM32 devices already in production to improve their yield and also I’m trying to bring to mass production new products. I’m in charge for test program/flow development and optimization, test simulation (simvision), hw testing on Verigy HP93k–SOC and Advantest T2000 platforms. I work, using UNIX, on svn database to manage testing programs that will be used in production. My previous experience in ST I was in charge as Product Engineer for IGBT power modules. I qualified a new family of devices, the IPM (intelligent power modules) products. They are used to drive the three-phases motors for the following applications: air conditioning, washing machines and dishing machines.
    [Show full text]
  • Jul 2 0 2004
    PRODUCT STRATEGY IN RESPONSE TO TECHNOLOGICAL INNOVATION IN THE SEMICONDUCTOR TEST INDUSTRY by ROBERT W. LIN Bachelor of Science in Mechanical Engineering Massachusetts Institute of Technology, 2000 Submitted to the Sloan School of Management and the Department of Mechanical Engineering in Partial Fulfillment of the Requirements for the Degrees of Master of Science in Mechanical Engineering and Master of Science in Management In Conjunction with the Leaders for Manufacturing Program at the Massachusetts Institute of Technology June 2004 02004 Massachusetts Institute of Technology All rights reserved Signature of Author.............. ...................... Department of Mechanical Engineering Sloan School of Management May 7, 2004 Certified by..... .................................................. Charles H. Fine, Thesis Supervisor Chrysler LFM Professor of Management C ertified by....................... ................................. anieli. Whitney, Thesis Supervisor Center for Technology, Policy, and Industrial Development Senior Research Scientist A ccepted by......................... .......................... Margaret Andrews, Executive Director of Master Program #eSVrr-,chool of Management Accepted by................. ............ ............... Ain Sonin, Chairman, Graduate Committee MASSACHUSETTS INSTITE Department of Mechanical Engineering OF TECHNOLOGY JUL 2 0 2004 LIBRARIES BARKER 2 PRODUCT STRATEGY IN RESPONSE TO TECHNOLOGICAL INNOVATION IN THE SEMICONDUCTOR TEST INDUSTRY by ROBERT W. LIN Submitted to the Sloan School
    [Show full text]
  • An Analysis of Revenue and Product Planning for Automatic Test Equipment Manufacturers
    An Analysis of Revenue and Product Planning for Automatic Test Equipment Manufacturers By Paul D. DeCosta B.S. Electrical Engineering, Worcester Polytechnic Institute, 1990 M.S. Biomedical Engineering, Rutgers University, 1992 Submitted to the Sloan School of Management and the Department of Electrical Engineering and Computer Science In partial fulfillment of the requirement for the degrees of Master of Science in Management and Master of Science in Electrical Engineering and Computer Science At the Massachusetts Institute of Technology May 1998 © 1998 Massachusetts Institute of Technology, All rights reserved Signature of Author Sloan School of Management Depaqment of Electricp.L Engineering and Computer Science Certified by Associate Professor Duan Boning, Thesis Advisor Department of Electrical Engineering and Computer Science Certified by Professorawrence WeiThesis Advisor .aiiSchoolb f Manaement Accepted by Arthur C. Smith, Chairman EECS Department Committee on Graduates FTECHNOLOGY ECOLOGYeffry 4ef A. Barks, Associate I 9. 1qqR Sloan Master's and Bachelor's Programs An Analysis of Revenue and Product Planning for Automatic Test Equipment Manufacturers By Paul D. Deposta Submitted to the Sloan School of Management and the Department of Electrical Engineering and Computer Science on May 8. 1998 in Partial Fulfillment of the Requirement for the Degrees of Master of Science in Management and Master of Science in Electrical Engineering and Computer Science Abstract Revenue and product planning for automatic test equipment (ATE) manufacturers has been difficult due to the cyclical nature of the semiconductor industry. Any insight into this area can provide a significant competitive advantage through tighter controls on cost and improved customer service. This work reviews possible improvements in revenue planning and introduces tools to help better understand the market.
    [Show full text]