Linking Mixed-Signal Design and Test Generation and Evaluation of Specification-Based Tests Nur Engin Samenstelling promotiecommissie: Voorzitter: Prof.dr. W.E. van der Linden, Universiteit Twente Secretaris: Prof.dr. W.E. van der Linden, Universiteit Twente Promotor: Prof.dr. H. Wallinga, Universiteit Twente Ass. Promotor: Dr.ir. H.G. Kerkhoff, Universiteit Twente Referent: Dr.-Ing. M.J. Ohletz, Alcatel Microelectronics Leden: Prof.dr.ir. B. Nauta, Universiteit Twente Prof.dr.ir. T. Krol, Universiteit Twente Prof.dr.ir. W.M.G. van Bokhoven, TU Eindhoven Prof.dr.ir. J.L. Huertas Diaz, University of Sevilla Title: Linking Mixed-Signal Design and Test Generation and Evaluation of Specification-Based Tests Author: Nur Engin ISBN: 90-3651494-0 Printed by Febodruk B.V., Enschede c N. Engin 2000 LINKING MIXED-SIGNAL DESIGN AND TEST GENERATION AND EVALUATION OF SPECIFICATION-BASED TESTS PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof. dr. F.A. van Vught, volgens besluit van het College van Promoties in het openbaar te verdedigen op vrijdag 29 september 2000 te 16.45 uur. door Nur Engin geboren op 16 september 1970 te Ankara (Turkije) Dit proefschrift is goedgekeurd door de promotor, Prof. dr. H. Wallinga, en de assistent promotor, Dr. ir. H.G. Kerkhoff. Was man nicht versteht, besitzt man nicht. GOETHE Contents Summary vii Acknowledgments ix Symbols xi Abbreviations xiii 1 Introduction 1 1.1 Testing: The Hidden Challenge ................ 2 1.2 Analog and Mixed-Signal Testing ............... 3 1.2.1 Analog vs Digital Testing ............... 3 1.2.2 Analog/Mixed-Signal Challenges ........... 5 1.3 Motivation and Problem Definition .............. 9 1.4 Outline ............................. 11 1.5 Bibliography .......................... 13 2 The Mixed-Signal Test Problem 15 2.1 Introduction ........................... 15 2.2 Mixed-Signal IC Architectures ................ 16 2.3 Current Design and Test Practice ............... 18 2.3.1 Prototype Test ..................... 18 2.3.2 Production Test .................... 20 2.4 Market Requirements ..................... 24 2.4.1 Quality ......................... 24 i 2.4.2 Cost ........................... 28 2.4.3 Time-to-Market ..................... 30 2.5 Mixed-Signal Test: Current Issues and Challenges ..... 31 2.5.1 Test and Measurement Environments ........ 31 2.5.2 Design for Testability (DfT) .............. 32 2.5.3 Built-in Self-Test (BIST) ............... 33 2.5.4 Automatic Test Program Generation (ATPG) .... 35 2.5.5 Test Program Evaluation ............... 37 2.6 Trends in Mixed-Signal IC Design .............. 38 2.7 Trends in IC Technology .................... 40 2.8 Design-Test Link ........................ 40 2.9 Conclusions ........................... 42 2.10 Bibliography .......................... 42 3 A General Framework for Mixed-Signal Test Generation and Testing 49 3.1 Introduction ........................... 49 3.2 Design and Test Flow: The Current Status ......... 50 3.3 High-Level Considerations ................... 51 3.4 Macro-Level Considerations .................. 56 3.5 Simulation Support for Test .................. 58 3.5.1 Simulation-Based Test Generation .......... 58 3.5.2 Virtual Testing ..................... 60 3.6 Reuse Issues in Design and Test ................ 63 3.7 State of the Art in Design-Test Link ............. 63 3.7.1 Virtual Test Software ................. 64 3.7.2 Test Plan Generation Tools .............. 65 3.7.3 Test Program Evaluation Tools ............ 66 3.8 A General Framework for Design-Test Link ......... 66 3.8.1 Definitions ....................... 68 3.8.2 Design and Test Methodology ............. 69 3.9 Conclusions ........................... 71 3.10 Bibliography .......................... 71 ii 4 MISMATCH: A Framework for Design-Test Link 75 4.1 System Overview ........................ 75 4.2 Integrated Design and Test Flow ............... 77 4.3 Test Database .......................... 77 4.4 Design for Testability ..................... 80 4.5 Design Database ........................ 81 4.6 MISMATCH CAD Data Flow ................. 82 4.6.1 Usage of Simulation Results .............. 83 4.6.2 Test Set Selection ................... 86 4.7 MISMATCH CAT Data Flow ................. 88 4.7.1 Test Control Signal Generation ............ 90 4.7.2 Automatic Routing for the Test Set ......... 90 4.7.3 Test Generation for Mixed-Signal Macros ...... 92 4.7.4 Test Generation for Digital Macros .......... 93 4.8 An Example: Design and Test of a Compass Watch ..... 94 4.8.1 IC Overview ...................... 94 4.8.2 Analog Functionality and the Test Library ..... 96 4.9 Test Results ........................... 105 4.9.1 Digital Parts ...................... 105 4.9.2 Analog Parts ...................... 107 4.10 Discussion of Experiences ................... 108 4.11 Conclusions ........................... 110 4.12 Bibliography .......................... 112 5 Defect-Oriented Test Evaluation for Analog Blocks 115 5.1 Introduction ........................... 115 5.2 General Test Selection Criteria ................ 116 5.3 Specification Coverage vs. Fault Coverage .......... 116 5.4 Manufacturing Defects and IC Faults ............. 118 5.5 Layout Based Fault List Extraction .............. 121 5.5.1 Critical Area ...................... 121 5.5.2 Fault Probability Calculations ............ 122 5.6 Analog Fault Simulation as a Test Evaluation Method ... 124 5.7 Problem Definition ....................... 125 iii 5.8 Standard Methods in Circuit Simulation ........... 127 5.9 Simulation Complexity ..................... 132 5.9.1 Evaluation of Device Models ............. 134 5.9.2 Solution of Linear Equations ............. 135 5.9.3 Number of NR Iterations ............... 135 5.10 Fault Simulation: Overview of Existing Methods ...... 137 5.10.1 Methods for Linear Circuits .............. 139 5.10.2 Methods for Solving Sets of Linear Equations... ... 139 5.10.3 Other Methods ..................... 148 5.11 Conclusion ........................... 149 5.12 Bibliography .......................... 151 6 A New Approach Towards Analog Fault Simulation 155 6.1 Introduction ........................... 155 6.2 Simulator Requirements .................... 156 6.3 DC-Bias Grouping ....................... 157 6.4 One-Step Relaxation Method ................. 163 6.5 Grouping Methods ....................... 165 6.6 Partial LU Update ....................... 166 6.7 Parallel Simulation ....................... 170 6.8 Implementation and Results .................. 170 6.9 Conclusions and Future Research ............... 178 6.10 Bibliography .......................... 180 7 Conclusions and Recommendations 185 7.1 Summary of Results ...................... 185 7.2 Original Contributions of This Thesis ............ 187 7.3 Recommendations ....................... 187 Appendices 189 A Example of a Virtual Instrument 191 A.1 Front Panel ........................... 191 A.2 Diagram ............................. 192 iv B Mixed-Signal Test System: An Overview 195 B.1 Digital Tester Part ....................... 195 B.2 Analogue Tester Part ...................... 196 B.3 Bibliography .......................... 197 C Verification Test Results for the Compass Watch Buffer Macro 199 Samenvatting 201 About the Author 203 v vi Summary The work described in this thesis is aimed at the exploration of new methods for the integration of design and test development procedures for mixed- signal integrated circuits (IC's). Mixed-signal IC's are currently found in many electronic systems, including telecommunications, audio and video instruments, automotive parts, etc. The testing of these IC's presents problems due to the complex nature of analog functionality and the non- automated analog design process. Automatic generation of test programs for analog parts is a problem which is not yet fully solved. Once a test is generated, formal methods to ensure the quality of developed tests do not exist or have a large overhead. Systematic links between design and test development processes of analog and mixed-signal circuits are required to improve these points and to ensure high quality and low time-to-market (TTM) for mixed-signal IC's. The various aspects of the mixed-signal test problem are discussed in chap- ter 2 of this thesis. A general discussion of the present mixed-signal design and test practice, the implications of market requirements on the test methodology, and the future challenges for mixed-signal testing is pre- sented. It has been concluded that long test development and debugging time and lack of methods for realistic test evaluation are the main chal- lenges in mixed-signal testing at present. The discussions in chapter 3 are aimed at defining a general framework for the integration of mixed-signal design and test activities along the IC development traject. For this, the test considerations at various levels of abstraction are given, and the present state of the art and possibilities in virtual testing and design-test link tools are presented. At the end of this chapter, a general framework for linking mixed-signal design and test is presented. In chapter 4, an environment for the integration of design and test flows for the prototype test of mixed-signal IC's is introduced and implemented. The described environment (MISMATCH) is based on the sharing of de- sign data with the test environment for generation of specification-based vii prototype tests during the design steps. The functionality consists of the selection of test methods