Class D Audio Design

• Class D Amplifier Introduction Theory of Class D operation, topology comparison • Gate Driver How to drive the gate, key parameters in gate drive stage • MOSFET How to choose, tradeoff relationships, loss calculation

• Package Importance of layout and package, new packaging technology • Design Example 200W+200W stereo Class D amplifier www.irf.com Prepared Oct.8 2003 by Jun Honda and Jorge Cerezo Trend in Class D

• Make it smaller! - higher efficiency - smaller package - Half Bridge

• Make it sound better! - THD improvement - fully digitally processed modulator

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Traditional Linear Amplifier

Feed back • Vcc

• • Error amp Bias •

• Vcc

Class AB amplifier uses linear regulating to modulate output voltage. η = 30% at temp rise test condition. www.irf.com System Î Gate Drive Î MOSFET Î Design Example How a Class D Amplifier Works

Feed back

Triangle +V C C Nch Level Shift

Dead Time • • COMP Nch Error Amp •

-V C C

Class D amplifier uses that are either ON or OFF. PWM technique is used to express analog audio signals with ON or OFF states in output devices.www.irf.com Basic PWM Operation

The output signal of comparator goes high when the sine wave is higher than the sawtooth.

Class D COMP LPF switching stage

Using f =400KHz to modulate 25KHz sinusoidal waveform PWM www.irf.com System Î Gate Drive Î MOSFET Î Design Example Topology Comparison: Class AB vs Class D

ηηTemp rise test condition

Efficiency

Output Output

Constant over Vbus Gain Proportional to Vbus

Good PSRR 0 dB

Both way Always from Direction of Creates Vbus pumping supply to load energy flow phenomena www.irf.com System Î Gate Drive Î MOSFET Î Design Example Analogy to Buck DC-DC Converter

Buck Converter Class D Amplifier

Fc of LPF is above

Gate Driver Gate Driver 20KHz

Q1 MOSFET Q1 MOSFET U1A 8 U1A L1

8 3 + L1 1 3 2 + 1 - 2 - ERROR AMP INDUCTOR 4 R1 ERROR AMP 4 C1 LOAD R1 C1 LOAD Q2 CAPACITOR MOSFET Q2 Vref MOSFET Audio signal input as a reference voltage

Load Current Direction Both current directions Î Influence of dead time is different Î Dead time needs to be very tight

Duty ratio is fixed Duty varies but average is 50% ÎIndependent optimization for HS/LS ÎSame optimization for both MOSFETs

ÎSame RDS(ON) required for both sides ÎLow RDS(ON) for longer duty, low Qg for shorter duty www.irf.com System Î Gate Drive Î MOSFET Î Design Example

Loss in Power Device Loss

V 2 Pc = 0.2⋅ CC 8⋅ R Loss in class AB L

1 π Vcc Vcc P = ⋅ ()1− K sinω ⋅t K sinω ⋅t • dω ⋅t C ∫ 2⋅π 0 2 2⋅ RL 2 2 Vcc  2K K  Regardless of output = ⋅ −  8π ⋅ RL  π 2  device parameters. K=2/π K=1 Loss Loss in Class D Efficiency can be improved further! PTOTAL = Psw + Pcond + Pgd

RDS (ON ) Pcond = ⋅ Po Pgd = 2⋅Qg ⋅Vgs ⋅ f PWM RL K=1 2 Psw = COSS ⋅VBUS ⋅ f PWM + I D ⋅VDS ⋅t f ⋅ f PWM K is a ratio of Vbus and output voltage. www.irf.com System Î Gate Drive Î MOSFET Î Design Example Half Bridge vs Full Bridge Supply voltage 0.5 x 2ch 1 Current ratings 1 2 MOSFET 2 MOSFETs/CH 4 MOSFETs/CH Gate Driver 1 Gate Driver/CH 2 Gate Drivers/CH Linearity Superior (No even order HD) DC Offset Adjustment is needed Can be cancelled out

PWM pattern 2 level 3 level PWM can be implemented Notes Pumping effect Suitable for open loop design Need a help of feed back

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Major Cause of Imperfection

Perturbation Zo Pulse width error Non linear inductance / Bus Pumping +V C C Quantization error Capacitance DCR

Audio source PWM Gate Driver

-V C C Dead time Delay time Finite RDS(on) Vth and Qg Body recovery

R DS(ON)

ON delay OFF delay

Finite dV/dt www.irf.com System Î Gate Drive Î MOSFET Î Design Example THD and Dead Time High Side Dead Time Low Side Dead Time ON

High Side OFF

ON Low Side OFF

40 34 Dead Time 40nS Dead Time 15nS 30

20 High Side edges

10

Vout() t 0 Falling edges

10 THD=2.1% THD=0.18%

20 Note: THD (Total Harmonic Distortion) is a means to 30 measure linearity with sinusoidal signal. 2 2 V2 +V3 + ⋅⋅⋅ − 34 40 4 THD = 05.10 Low0.001 Side edges 0.0015 0.002 0 t 0.0021 V fundamental www.irf.com System Î Gate Drive Î MOSFET Î Design Example Shoot Through and Dead Time

Q st as a function of Overlap Time & R g Vbus = 60V, Id = 2A, Vgs = 12V (Overlap time m easured from 50% Vgs high side fall to 10% Vgs low side rise) High side Vgs Rg=10 ohm Low side Vgs

Rg=1Ohms

120 Rg=5Ohms

100 rg=10O hm s

80

Shoot through current 60

40 2A/div 20

0 -10-50 5101520

O verlap time (ns)

-Shoot through charge increases rapidly as dead time gets shorter. -Need to consider manufacturing tolerances and temperature characteristics.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Power Supply Pumping

Supply voltage Pumping effect Load Current +Vcc

Vo

-Vcc Commutation V ∆V max = BUS current BUS 8⋅π ⋅ f PWM ⋅ RLOAD ⋅CBUS Half Bridge Full Bridge Load Current

-Significant at low frequency output -Significant at low load impedance -Significant at small bus -Largest at duty = 25%, and 75% Commutation current www.irf.com System Î Gate Drive Î MOSFET Î Design Example EMI consideration: Qrr in Body Diode

1 • 23•

1. Low side drains inductor current 2. During dead time body diode of low side conducts and keep inductor current flow 3. At the moment high side is turned ON after dead time, the body diode is still conducting to wipe away minority carrier charge stored in the duration of forward conduction. ÎThis current generates large high frequency current waveform and causes EMI noises. www.irf.com System Î Gate Drive Î MOSFET Î Design Example Gate Driver: Why is it Needed?

• Gate of MOSFET is a capacitor to be charged and discharged. Typical effective capacitance is 2nF.

• High side needs to have a gate voltage referenced to it’s Source.

• Gate voltage must be 10-15V higher than the drain voltage.

• Need to control HS and LS independently to have dead time.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Functional Block Diagram Inside Gate Driver

International Rectifier's family of MOS gate drivers integrate most of the functions required to drive one high side and one low side power MOSFET in a compact package. With the addition of few components, they provide very fast switching speeds and low power dissipation.

Input Logic High side well

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Boot Strap High Side Power Supply

Charge Discharge ON

ON

When Vs is pulled down to ground through the low side FET, the bootstrap capacitor (CBOOT) charges through the bootstrap diode (Dbs) from the Vcc supply, thus providing a supply to Vbs.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Boot Strap High Side Power Supply (Cont’d)

• Boot Strap Capacitor Selection

To minimize the risk of overcharging and further reduce ripple on the Vbs voltage the Cbs value obtained from the above equation should be should be multiplied by a factor of 15 (rule of thumb).

• Boot Strap Diode Selection The bootstrap diode (Dbs) needs to be able to block the full power rail voltage, which is seen when the high side device is switched on. It must be a fast recovery device to minimize the amount of charge fed back from the bootstrap capacitor into the Vcc supply. VRRM = Power rail voltage, max trr = 100ns, IF > Qbs x f For more details on boot strap refer to DT98-2 www.irf.com System Î Gate Drive Î MOSFET Î Design Example Power Dissipation in Gate Driver

• Whenever a capacitor is charged or discharged through a , half of energy that goes into the capacitance is dissipated in the resistor. Thus, the losses in the gate drive resistance, internal and external to the MGD, for one complete cycle is the following:

PG = V ⋅ fSW ⋅QG

For two IRF540 HEXFET® MOSFETs operated at 400kHz with Vgs = 12V, we have: PG = 2 • 12 • 37 • 10-9 • 400 • 103 = 0.36W

R3 R3 High Side High Side SW1

SW1 R2 C1 R2 C1 Low Side Ciss Low Side Ciss

For more details on gate driver ICs, refer to AN978 www.irf.com System Î Gate Drive Î MOSFET Î Design Example Power Dissipation in Gate Driver (Cont’d)

•The use of gate reduces the amount of gate drive power 200 100 that is dissipated inside the MGD by the ratio of the respective 10 resistances. 150.00

125.00

100.00 •These losses are not 75.00 temperature dependent. 50.00

Junction Tem perature (C) Tem perature Junction 25.00

0.00

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

Figure 32: IR2010S Tj vs Frequency R = 10 O hm , V cc = 15V w ith IRFP E50 G ATE

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Layout Considerations

• Stray inductance LD1+LS1 contribute to undershoot of the Vs node beyond the ground

IR2011

As with any CMOS device, driving any of parasitic into forward conduction or reverse breakdown may cause parasitic www.irf.com SCR latch up. System Î Gate Drive Î MOSFET Î Design Example Gate Driver for Class D Applications IR2011(S) Key Specs

• Fully operational up to +200V • Low power dissipation at high switching frequency • 3.3V and 5V input logic compatible • Matched propagation delay for both channels • Tolerant to negative transient voltage, dV/dt immune SO-8 • SO-8/DIP-8 Package

www.irf.com System Î Gate Drive Î MOSFET Î Design Example How MOSFETs Work • A MOSFET is a voltage-controlled power . A voltage must be applied between Gate and Source terminals to produce a flow of current in the Drain.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example MOSFET Technologies (1) • IR is striving to continuously improve the power MOSFET to enhance the performance, quality and reliability.

• Hexagonal Cell Technology

• Planar Stripe Technology

• Trench Technology

www.irf.com System Î Gate Drive Î MOSFET Î Design Example MOSFET Technologies (2) • Power MOSFET FOMs (R*Qg) have significantly improved between the released IR MOSFET technologies

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Key Parameters of MOSFETs (1)

• Voltage Rating, BVDSS

This is the drain-source breakdown voltage (with VGS = 0). BVDSS should be greater than or equal to the rated voltage of the device, at the specified leakage current, normally measured at Id=250uA. This parameter is temperature-dependent and ∆ ∆ frequently BVDSS/ Tj (V/°C) is specified on datasheets.

BVDSS MOSFET voltages are available from tens to thousand volts.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Key Parameters of MOSFETs (2) • Gate Charge, Qg This parameter is directly related to the MOSFET speed and is temperature- independent. Lower Qg results in faster switching speeds and consequently lower switching losses. The total gate charge has two main components: the gate- Basic Gate Charge Waveform source charge, Qgs and, the gate-drain charge, Qgd (often called the Miller charge). www.irf.com System Î Gate Drive Î MOSFET Î Design Example Key Parameters of MOSFETs (3)

• Static Drain-to-Source On-Resistance, RDS(ON) This is the drain-source resistance, typically specified on data sheet at 25°C with VGS = 10V.

RDS(ON) parameter is temperature-dependent, and is directly related to the MOSFET conduction losses. lower RDS(ON) results in lower conduction losses. Normalized On-Resistance vs. Temperature

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Key Parameters of MOSFETs (4) • Body Diode Reverse Recovery Characteristics, Qrr, trr, Irr and S factor. Power MOSFETs inherently have an integral reverse body-drain diode. This body diode exhibits reverse recovery characteristics. Reverse Recovery Charge Qrr, Reverse Recovery Time trr, Reverse Recovery Current Irr and Softness factor (S = tb/ta), are typically specified on data sheets at 25°C and di/dt = 100A/us. Reverse recovery characteristics are temperature-dependent and lower trr, Irr and Qrr improves THD, EMI and Efficiency η. Typical Voltage –Current Waveforms for a MOSFET Body Diode www.irf.com System Î Gate Drive Î MOSFET Î Design Example Key Parameters of MOSFETs (5) • Package MOSFET devices are available in several packages as SO-8,TO-220, D-Pak, I-Pak, TO- 262, DirectFET™, etc. The selection of a MOSFET package for a specific application depends on the package characteristics such as dimensions, power dissipation capability, current capability, internal inductance, internal resistance, electrical isolation and mounting process.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Choosing the MOSFET Voltage Rating for Class D applications (1) • MOSFET voltage rating for a Class D amplifier is determined by: Ω – Desired POUT and load impedance (i.e. 250W on 4 ) – Topology (Full Bridge or Half Bridge) – Modulation Factor M (80-90%)

2 * POUT * RLOAD VBDSS min = * 1.5 M

Typical additional factor due to stray resistance, power supply fluctuations and MOSFET Turn-Off peak voltage www.irf.com System Î Gate Drive Î MOSFET Î Design Example Choosing the MOSFET Voltage Rating for Class D Applications (2) • Full-Bridge Topology Class D amplifier

• Half-Bridge Configuration Class D amplifier

www.irf.com Note 1. Modulation Factor M = 85% System Î Gate Drive Î MOSFET Î Design Example Calculation of Switching Loss (1)

• Switching Losses are the result of turn-on and turn-off switching times

MOSFET Turn-On MOSFET Turn-Off

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Calculation of Switching Loss (2)

• Gate resistance Rg, and gate charge Qg, have a significant influence on turn-on and turn-off switching times

↑ ⇒ ↓ ⇒ ↑ ⇒ ↑ Rg Ig tSWITCHING PSWITCHING

RG ↑ ⇒ ↑ ⇒ ↑ Qg tSWITCHING PSWITCHING

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Estimation of Switching Losses (1)

• Switching losses can be obtained by calculating the switching energy dissipated in the MOSFET

t

Esw = ∫ VDS(t) * ID(t) dt 0 Where t is the length of the switching pulse.

• Switching losses can be obtained by multiplying switching energy with switching frequency.

PSWITCHING = ESW * FSW

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Estimation of Conduction Loss (2)

• Conduction losses can be calculated using RDS(ON) @ Tj max and IDRMS current of MOSFET

2 PCONDUCTION = (ID RMS) * RDS(ON)

ID RMS is determined using amplifier specifications:

POUT ID RMS =

RLOAD

RDS(ON) data can be obtained from the MOSFET data sheet.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Thermal Design • Maximum allowed power dissipation for a MOSFET mounted on a heat sink:

∆ Pmax = Tj / Rthja max

Pmax = (Tamb –Tjmax ) / (Rthjc max +Rthcs max +Rths max +Rthsa max)

Where: Tamb = Ambient Temperature

Tjmax = Max. Junction Temperature

Rthjc max = Max. Thermal Resistance Junction to Case

Rthcs max = Max. Thermal Resistance Case to Heatsink

Rths max = Max. Thermal Resistance of Heatsink R = Max. Thermal Resistance Heatsink to Ambient thsa max www.irf.com System Î Gate Drive Î MOSFET Î Design Example

RDS(ON) vs Qg • There is tradeoff between Static Drain-to-Source On- Resistance, RDS(ON) and Gate charge, Qg ⇒ ⇒ Higher RDS(ON) Lower Qg Higher PCONDUCTION & Lower PSWITCHING ⇒ ⇒ Lower RDS(ON) Higher Qg Higher PSWITCHING &Lower PCONDUCTION

Gen 7.5 100V MOSFET Platform

RDS(ON) vs. Qg

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Die Size vs Power Loss (1) • Die size has a significant influence on MOSFET power losses ⇒ Smaller Die Higher PCONDUCTION & Lower PSWITCHING ⇒ Bigger Die Higher PSWITCHING &Lower PCONDUCTION

Gen 7 100V MOSFET Platform – Power Losses @ 384kHz

Total Loss

Conduction Loss Switching Loss

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Die Size vs Power Loss (2)

• Die size is directly related with RDS(ON) and RTHjc of the MOSFET ⇒ Smaller Die Higher RDS(ON) and Higher RTHjc ⇒ Bigger Die Lower RDS(ON) and Lower RTHjc

55V Trench Technology MosFET 55V Trench Technology MosFET

Die Size vs. RDS(ON) Die Size vs. RTHjc

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Choosing the Right MOSFET for Class D Applications (1)

• The criteria to select the right MOSFET for a Class D amplifier application are:

–VBDSS should be selected according to amplifier operating voltage, and it should be large enough to avoid avalanche condition during operation η – Efficiency is related to static drain-to-source on-resistance, RDS(ON). η smaller RDS(ON) improves efficiency . RDS(ON) is recommended to be smaller than 200mΩ for mid and high-end power, full-bandwidth amplifiers – Low gate charge, Qg, improves THD and efficiency η. Qg is recommended to be smaller than 20nC for mid and high-end power, full-bandwidth amplifiers

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Choosing the Right MOSFET for Class D Application (2) – Amplifier performance such as THD, EMI and efficiency η are also related to MOSFET reverse recovery characteristics. Lower trr, Irr and Qrr improves THD, EMI and efficiency η – Rthjc should be small enough to dissipate MOSFET power losses and keep Tj < limit – Better reliability and lower cost are achieved with higher MOSFET Tj max – Finally, selection of device package determines the dimensions, electrical isolation and mounting process. These factors should be considered in package selection. Because cost, size and amplifier performance depend on it.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Development of Class D Dedicated Devices

• Performance of the Class D amplifying stage strongly depends on the characteristics of MOSFETs and ICs.

• Designers of driver IC and MOSFET silicon need to keep the special requirements of the Class D application in mind.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Influences of Stray Inductance

• PCB layout and the MOSFET internal package

inductances contribute to the stray inductance (LS) in the circuit.

• Stray inductances affect the MOSFET performance and EMI of the system.

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Influences of Stray Inductance

• Drain and source stray inductances reduces the gate voltage during turn-on resulting in longer switching time. • Also during turn-off, drain and source stray inductances generate a

large voltage drop due to dID/dt, producing drain to source over- voltage transients. www.irf.com System Î Gate Drive Î MOSFET Î Design Example DirectFET™ Packaging

Use a single multiple-finned heat sink to dissipate heat from devices passivated die DirectFET devices copper ‘drain’ clip die attach material

gate connection source connection copper track on board Both Side Circuit board Cooling Thermal interface gap filler material or pad

• Remove wirebonds from package and replace with large area solder contacts • Reduced package inductance and resistance

4.8mm • Copper can enables dual sided cooling

~ www.irf.com System Î Gate Drive Î MOSFET Î Design Example DirectFET™ Packaging DirectFET waveform SO-8 waveform

• 30A VRM output current • 500 kHz per phase • Silicon of the near identical active area, voltage and generation used in both packages • Inductance related ringing greater in case of SO-8

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Class D Amp Reference Design

• Specs

Topology: Half Bridge IR Devices: IR2011S, IRFB23N15D Switching frequency: 400kHz (Adjustable) Rated Output Power: 200W+200W / 4 ohm THD: 0.03% @1kHz, Half Power Frequency Response: 5Hz to 40kHz (-3dB) Power Supply: ~ ±50V Size: 4.0” x 5.5”

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Class D Amp Reference Board: Block Diagram

Feed back

+V C C

Integrator Level Shifter + LT1220 2N5401 LPF

GND IR2011S Gate Driver

Comparator 74HC04 IRFB23N15D

-V C C

-VCC

www.irf.com System Î Gate Drive Î MOSFET Î Design Example Circuit Diagram

1 2 3 4

CH1 Feed Back Path D D R1 R3 +50V 47K 1K C1 220pF, 100V +5V GNDP Over Current J3 1 C8 2 Level Shift 3 R37 Q2 C25 47mOHM, 2W MKDS5/3-9.5 0.01uF R12 R35 10K 0.1uF, 50V Integrator 470 GNDP GNDP C17 MMBT5401 TP3 R28 -50V 1000pF, 100V PROTECT R11 PAD 22K GNDP R23 10K TP 100 R26 1K C C18 2 C31 C38 C 1 MA2YD23 R21 1000pF, 100V C9 R82 VDD_1 C30 Input analog D6 J1 5K 1uF, 16V 10K Q5 7 U2 U4 U6 LPF

1418-ND C3 1 8 1 8 1 8 3 R31 1 D10 R10 C6 HO

3 GNDP Q1 2 7 2 7 R39 0.22uF, 100V 470uF, 50V CH1 OUT 9.1 IRFB23N15D 6 R4 3 6 3 6 2 C23 1 10K U1 VB 0.33uF, 25V RLY1A

R8 D1 D2 2 4 5 4 5 MURS120 0.22uF, 100V GNDP GNDP 10uF, 50V 1K 3 L1 330K 6 4 J5 Lin VS LT1220CS8 MMBT5401 TC7WH04FU TC7WH08FU 8 5 1 1N4148 1N4148

dummy 1 18uH 4 VCC 255-1054 (1) 2 C R49 C51 1 GNDP 5 7 4.7 2 R61 MKDS5/2-9.5 Hin COM GNDP C42 Q9 MA2YD23 C49 10, 1W R13 B MMBT3904 TP4 8 D7 Q6 LO C26 10K PAD TP GNDP 0.1uF,50V 3.3uF, 35V IR2011 R50 1 D11 C? 0.47uF, 100V C33 GNDP R41 R64 0.1uF, 100V GNDP 9.1 IRFB23N15D MURS120 100K Quantize 10 Gate Driver 0.22uF, Speaker100V output .01uF, 50V E GNDP D14 R53 R54 R55 R56 3 MURS120DICT dummydummydummydummy GNDP

B B -5V R44 SD1 R47 4.7K 10 C44 1uF, 16V Snubber

C19 dummy

R14 C32 C39 10K -50_1 -50+VCC 470uF, 50V 0.22uF, 100V GNDP GNDP GNDP A A

Title CLASS D REFERENCE BOARD --- CHANNEL 1 Sheet2 of 4 Number: Revision:1.0 INTERNATIONAL RECTIFIER Drawn by: Approvedwww.irf.com by: EL SEGUNDO, CALIFORNIA, USA File: 1. ClassD_Refbd_R2-0_CH1.~ch Date: 23-Sep-2003 Time: 15:13:04 1 2 3 4 System Î Gate Drive Î MOSFET Î Design Example Class D Amp Reference Board: Layout

Modulator Protection Analog Input (CH1) Speaker (CH1) LPF (CH1) (CH1) ±5V

Regulator Gate Driver HeatSink

Modulator Bus Capacitor LPF Speaker Analog Input (CH2) (CH2) (CH2)

(CH2) MOSFET MOSFET Gate Driver +12V DC/DC

www.irf.com Power Supply System Î Gate Drive Î MOSFET Î Design Example Performance

50W / 4Ω, 1KHz, THD+N=0.0078% THD+N v.s. Output Power 10 9.35 HP8903B CH1, f=1KHz, RL=4Ω VCC=±50.0V 1 fPWM=426KHz

THD 0.1

0.01 342W / 4Ω, 1KHz, THD+N=10%

− 3 7.5× 10 3 1 .10 3 0.1 1 10 100 1 .10 0.16 Output_Power 342.3

•Peak Output Power (f=1KHz) 120W / 8Ω / ch, THD=1% 180W / 8Ω / ch, THD=10% 245W / 4Ω / ch, THD=1% www.irf.com 344W / 4Ω / ch, THD=10% System Î Gate Drive Î MOSFET Î Design Example Performance (Cont’d)

Switching waveform THD+N v.s. Frequency 10 10 HP8903B CH1, Po=50W, RL=4Ω 1 VCC=±50.0V

fPWM=364KHz

THD 0.1

0.01

3 − 3 7.1× 101 .10 3 4 5 10 100 1 .10 1 .10 1 .10 4 20 Frequency LPF210×

Residual Noise: 62.5µVrms, A-Weighted, 30KHz-LPF

www.irf.com Conclusion

• Highly efficient Class D amplifiers now provide similar performance to conventional Class AB amplifiers - If key components are carefully selected and the layout takes into account the subtle, yet significant impact due to parasitic components.

Constant innovation in semiconductor technologies helps the growing Class D amplifiers usage due to improvements in higher efficiency, increased power density and better audio performance.

www.irf.com