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Class D Audio Amplifier Design

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Class D Audio Amplifier Design Class D Audio Amplifier Design • Class D Amplifier Introduction Theory of Class D operation, topology comparison • Gate Driver How to drive the gate, key parameters in gate drive stage • MOSFET How to choose, tradeoff relationships, loss calculation • Package Importance of layout and package, new packaging technology • Design Example 200W+200W stereo Class D amplifier www.irf.com Prepared Oct.8 2003 by Jun Honda and Jorge Cerezo Trend in Class D Amplifiers • Make it smaller! - higher efficiency - smaller package - Half Bridge • Make it sound better! - THD improvement - fully digitally processed modulator www.irf.com System Î Gate Drive Î MOSFET Î Design Example Traditional Linear Amplifier Feed back • Vcc • • Error amp Bias • • Vcc Class AB amplifier uses linear regulating transistors to modulate output voltage. η = 30% at temp rise test condition. www.irf.com System Î Gate Drive Î MOSFET Î Design Example How a Class D Amplifier Works Feed back Triangle +V C C Nch Level Shift Dead Time • • COMP Nch Error Amp • -V C C Class D amplifier uses MOSFETs that are either ON or OFF. PWM technique is used to express analog audio signals with ON or OFF states in output devices.www.irf.com Basic PWM Operation The output signal of comparator goes high when the sine wave is higher than the sawtooth. Class D COMP LPF switching stage Using f =400KHz to modulate 25KHz sinusoidal waveform PWM www.irf.com System Î Gate Drive Î MOSFET Î Design Example Topology Comparison: Class AB vs Class D ηηTemp rise test condition Efficiency Output Output Constant over Vbus Gain Proportional to Vbus Good PSRR 0 dB Both way Always from Direction of Creates Vbus pumping supply to load energy flow phenomena www.irf.com System Î Gate Drive Î MOSFET Î Design Example Analogy to Buck DC-DC Converter Buck Converter Class D Amplifier Fc of LPF is above Gate Driver Gate Driver 20KHz Q1 MOSFET Q1 MOSFET U1A 8 U1A L1 8 3 + L1 1 3 2 + 1 - INDUCTOR 2 ERROR AMP - INDUCTOR 4 R1 ERROR AMP 4 C1 LOAD R1 CAPACITOR C1 LOAD Q2 CAPACITOR MOSFET Q2 Vref MOSFET Audio signal input as a reference voltage Load Current Direction Both current directions Î Influence of dead time is different Î Dead time needs to be very tight Duty ratio is fixed Duty varies but average is 50% ÎIndependent optimization for HS/LS ÎSame optimization for both MOSFETs ÎSame RDS(ON) required for both sides ÎLow RDS(ON) for longer duty, low Qg for shorter duty www.irf.com System Î Gate Drive Î MOSFET Î Design Example Loss in Power Device Loss V 2 Pc = 0.2⋅ CC 8⋅ R Loss in class AB L 1 π Vcc Vcc P = ⋅ 1− K sinω ⋅t K sinω ⋅t • dω ⋅t C ∫ () 2⋅π 0 2 2⋅ RL 2 2 Vcc 2K K Regardless of output = ⋅ − 8π ⋅ RL π 2 device parameters. K=2/π K=1 Loss Loss in Class D Efficiency can be improved further! PTOTAL = Psw + Pcond + Pgd RDS (ON ) Pcond = ⋅ Po Pgd = 2⋅Qg ⋅Vgs ⋅ f PWM RL K=1 2 Psw = COSS ⋅VBUS ⋅ f PWM + I D ⋅VDS ⋅t f ⋅ f PWM K is a ratio of Vbus and output voltage. www.irf.com System Î Gate Drive Î MOSFET Î Design Example Half Bridge vs Full Bridge Supply voltage 0.5 x 2ch 1 Current ratings 1 2 MOSFET 2 MOSFETs/CH 4 MOSFETs/CH Gate Driver 1 Gate Driver/CH 2 Gate Drivers/CH Linearity Superior (No even order HD) DC Offset Adjustment is needed Can be cancelled out PWM pattern 2 level 3 level PWM can be implemented Notes Pumping effect Suitable for open loop design Need a help of feed back www.irf.com System Î Gate Drive Î MOSFET Î Design Example Major Cause of Imperfection Perturbation Zo Pulse width error Non linear inductance / Bus Pumping +V C C Quantization error Capacitance DCR Audio source PWM Gate Driver Dead time -V C C Delay time Finite RDS(on) Vth and Qg Body diode recovery R DS(ON) ON delay OFF delay Finite dV/dt www.irf.com System Î Gate Drive Î MOSFET Î Design Example THD and Dead Time High Side Dead Time Low Side Dead Time ON High Side OFF ON Low Side OFF 40 34 Dead Time 40nS Dead Time 15nS 30 20 High Side edges 10 Vout() t 0 Falling edges 10 THD=2.1% THD=0.18% 20 Note: THD (Total Harmonic Distortion) is a means to 30 measure linearity with sinusoidal signal. 2 2 V2 +V3 + ⋅⋅⋅ − 34 40 4 THD = 05.10 Low0.001 Side edges 0.0015 0.002 0 t 0.0021 V fundamental www.irf.com System Î Gate Drive Î MOSFET Î Design Example Shoot Through and Dead Time Q st as a function of Overlap Time & R g Vbus = 60V, Id = 2A, Vgs = 12V High side Vgs (Overlap time m easured from 50% Vgs high side fall to 10% Vgs low side rise) Rg=10 ohm 120 Low side Vgs 100 80 Rg=1Ohms 60 Rg=5Ohms rg=10O hm s 40 Shoot through current 2A/div 20 0 -10-50 5101520 O verlap time (ns) -Shoot through charge increases rapidly as dead time gets shorter. -Need to consider manufacturing tolerances and temperature characteristics. www.irf.com System Î Gate Drive Î MOSFET Î Design Example Power Supply Pumping Supply voltage Pumping effect Load Current +Vcc Vo -Vcc Commutation V ∆V max = BUS current BUS 8⋅π ⋅ f PWM ⋅ RLOAD ⋅CBUS Half Bridge Full Bridge Load Current -Significant at low frequency output -Significant at low load impedance -Significant at small bus capacitors -Largest at duty = 25%, and 75% Commutation current www.irf.com System Î Gate Drive Î MOSFET Î Design Example EMI consideration: Qrr in Body Diode 1 • 23• 1. Low side drains inductor current 2. During dead time body diode of low side conducts and keep inductor current flow 3. At the moment high side is turned ON after dead time, the body diode is still conducting to wipe away minority carrier charge stored in the duration of forward conduction. ÎThis current generates large high frequency current waveform and causes EMI noises. www.irf.com System Î Gate Drive Î MOSFET Î Design Example Gate Driver: Why is it Needed? • Gate of MOSFET is a capacitor to be charged and discharged. Typical effective capacitance is 2nF. • High side needs to have a gate voltage referenced to it’s Source. • Gate voltage must be 10-15V higher than the drain voltage. • Need to control HS and LS independently to have dead time. www.irf.com System Î Gate Drive Î MOSFET Î Design Example Functional Block Diagram Inside Gate Driver International Rectifier's family of MOS gate drivers integrate most of the functions required to drive one high side and one low side power MOSFET in a compact package. With the addition of few components, they provide very fast switching speeds and low power dissipation. Input Logic High side well www.irf.com System Î Gate Drive Î MOSFET Î Design Example Boot Strap High Side Power Supply Charge Discharge ON ON When Vs is pulled down to ground through the low side FET, the bootstrap capacitor (CBOOT) charges through the bootstrap diode (Dbs) from the Vcc supply, thus providing a supply to Vbs. www.irf.com System Î Gate Drive Î MOSFET Î Design Example Boot Strap High Side Power Supply (Cont’d) • Boot Strap Capacitor Selection To minimize the risk of overcharging and further reduce ripple on the Vbs voltage the Cbs value obtained from the above equation should be should be multiplied by a factor of 15 (rule of thumb). • Boot Strap Diode Selection The bootstrap diode (Dbs) needs to be able to block the full power rail voltage, which is seen when the high side device is switched on. It must be a fast recovery device to minimize the amount of charge fed back from the bootstrap capacitor into the Vcc supply. VRRM = Power rail voltage, max trr = 100ns, IF > Qbs x f For more details on boot strap refer to DT98-2 www.irf.com System Î Gate Drive Î MOSFET Î Design Example Power Dissipation in Gate Driver • Whenever a capacitor is charged or discharged through a resistor, half of energy that goes into the capacitance is dissipated in the resistor. Thus, the losses in the gate drive resistance, internal and external to the MGD, for one complete cycle is the following: PG = V ⋅ fSW ⋅QG For two IRF540 HEXFET® MOSFETs operated at 400kHz with Vgs = 12V, we have: PG = 2 • 12 • 37 • 10-9 • 400 • 103 = 0.36W R3 R3 High Side High Side SW1 SW1 R2 C1 R2 C1 Low Side Ciss Low Side Ciss For more details on gate driver ICs, refer to AN978 www.irf.com System Î Gate Drive Î MOSFET Î Design Example Power Dissipation in Gate Driver (Cont’d) •The use of gate resistors reduces 150.00 200 100 the amount of gate drive power 125.00 that is dissipated inside the MGD by the ratio of the respective 100.00 10 resistances. 75.00 50.00 •These losses are not temperature dependent. 25.00 Junction Tem perature (C) Tem perature Junction 0.00 1.E+03 1.E+04 1.E+05 1.E+06 Frequency (Hz) Figure 32: IR2010S Tj vs Frequency R G ATE = 10 O hm , V cc = 15V w ith IRFP E50 www.irf.com System Î Gate Drive Î MOSFET Î Design Example Layout Considerations • Stray inductance LD1+LS1 contribute to undershoot of the Vs node beyond the ground IR2011 As with any CMOS device, driving any of parasitic diodes into forward conduction or reverse breakdown may cause parasitic www.irf.com SCR latch up.
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