The Field-Effect Transistor (FET) In a field-effect transistor, an applied voltage is used to change the conductivity of an electron or “hole” channel. To understand the operation of a FET, we first should understand just a little about the chemistry and physics of semiconductor devices. Let us consider, for simplicity, only silicon devices. Some Background (this section is Explore More!...will not be tested) Silicon (Si) is an element of the periodic table that contains 4 electrons in its “outer shell”. Pure silicon can arrange itself in a diamond cubic crystal structure (ref: http://en.wikipedia.org/wiki/Band_gap) where it shares its electrons with other Si atoms. The valance band is nominally full and the conduction band is nominally empty, thus resulting in an insulating material. Within this structure, Si forms an insulating material with a band gap energy of 1.11 electron volts (1.6e-19J, the amount of energy needed to move one electron across a one volt potential) separating the valance band from the conduction band.
Figure 1: Electron band gap of an undoped (intrinsic) semiconductor.
When doped (or infused) with an element that contains 5 electrons in its outer shell (say, for instance, nitrogen, N), this element will displace one silicon atom. Only using 4 of its 5 outer-shell electrons to form tight bonds with the neighboring Si atoms, nitrogen has one electron that is only loosely bound to the lattice. An electron may be more easily excited into the conduction band (the dopant provides a smaller band gap). With enough dopants (often 1 doping atom per 1 thousand to 1 billion Si atoms) and energy to excite electrons into the conduction band, the material becomes less like an insulator and more like a conductor. This is called n-type material in reference to the negative charge of the loosely- bound electron and electrons easily excited into the valance band are called the majority charge carriers. See also http://hyperphysics.phy-astr.gsu.edu/hbase/solids/dope.html.
Figure 2: Electron band gap of an n-type (doped) semiconductor.
Similarly, the Si lattice may be doped with an element that contains 3 electrons in its outer shell (boron, B, for instance). In this case, all three electrons bind with neighboring Si atoms and the chemical bond still desires to absorb an additional electron. This electron-short bond is often referred to as a “hole” and we can envision the hole as a moving entity as neighboring electrons shift bonds to fill it. As the negatively-charged electrons move, one can analogously consider the hole to be a positively-charged entity moving in the direction opposite the electron. This is called p-type material in reference to the apparent positive charge of the hole. The holes, which allow movement of charge through the lattice are called the majority charge carriers.
Figure 3: Electron band gap of a p-type (doped) semiconductor.
In ECE110 focus, our focus will be on semiconductor devices called the Metal-Oxide-Semiconductor FET (MOSFET). In the structure shown below, the substrate is p-type material, but two wells are heavily infused with n-type dopants. While the n+ wells have plenty of electron “charge carriers”, current cannot easily flow between the two wells due to the p-type material separating the two. In order to attract electron carriers to the region, we can apply a positive voltage at the Gate relative to the Body of the device. Electrons will be repelled away from the body’s metal contact and towards the metal contact of the gate. An insulating Oxide layer prevents them from reaching the metal of the gate, however. Instead, when the gate-to-body voltage exceeds a certain threshold value, the electrons aid to form a conductive channel of electron majority carriers between the drain and the source. The only thing left is to provide a voltage potential between the drain and the source in order to cause current flow through this conductive channel. See also, for example, https://www.youtube.com/watch?v=tz62t-q_KEc.
(a) (b)
(c)
Figure 4: The n-channel MOSFET structure (enhancement style), a) without and b) with gate biasing to enhance an n-type channel. Subfigure c) emphasizes that the enhanced channel will often behave as an Ohmic channel of low resistance.
MOSFETs are of interest for several reasons. When compared to BJTs, they are generally easier to fabricate, they scale down in size better without significant changes in their electronic characteristics, and they use less power than BJTs in many common applications. BJTs are still used in very high-speed switching integrated circuits and they are common as “discrete” devices (not packaged in a larger scale integrated circuit). Circuit Symbol and Basic Biasing Turning away from the physics and chemistry aspects of these devices, we can formulate a four-terminal device. Since the Body and Source will always be connected together (for us in ECE110 as well as in most applications), we can consider it to be effectively a three-terminal device similar to the BJT.
(a) (b) (c)
Figure 5: Several n-channel MOSFET symbols; a) four-terminal, b) three terminal, c) logic symbol.
The symbols above suggest the idea that the gate is capacitive (as we observed the Gate-Body connection is much like a capacitor). The gate also serves the role of creating a conductive channel between the Drain and Source…much in the same way as the base of the BJT was used to control conduction between the Collector and Emitter.
The parallels between the BJT and the MOSFET do not end there. By “biasing” the gate voltage, , above the threshold voltage, , and by applying a voltage potential between the drain and source 𝐺𝐺𝐺𝐺 using a series voltage source and resistance (see figure below), current can be made to flow and𝑉𝑉 𝑇𝑇𝑇𝑇 output voltage will appear𝑉𝑉 across the drain and source terminals. 𝐼𝐼𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷
(a)
(b)
Figure 6: The biased MOSFET, a) in physical diagram and b) in schematic diagram form. IV Characteristics The IV characteristics of a typical MOSFET are shown in the figure below.
Figure 7: Typical MOSFET IV characteristics [source: http://en.wikipedia.org/wiki/MOSFET#mediaviewer/File:IvsV_mosfet.svg]
Like the BJT, current increases with increasing , but only to a maximum current, the saturation current! Different than the BJT characteristic, the current doesn’t begin to flow suddenly at a certain 𝑉𝑉𝐷𝐷𝐷𝐷 value ( , for the BJT), but rather begins to flow at any > 0. In this region, the ratio is nearly 𝑉𝑉𝐷𝐷𝐷𝐷 linear and𝐶𝐶𝐶𝐶 𝑠𝑠𝑠𝑠𝑠𝑠characteristic of Ohm’s law! For this reason, this region𝐷𝐷𝐷𝐷 of MOSFET operation (to the left of 𝑉𝑉 𝑉𝑉 𝐼𝐼𝐷𝐷 the red curve) is often called the linear region or the Ohmic region. In the saturation region, = ( ) . 𝐷𝐷 2 𝐼𝐼 An𝑉𝑉𝐺𝐺𝐺𝐺 Ohmic− 𝑉𝑉𝑇𝑇𝑇𝑇 approximation would result in a linearized model of the MOSFET IV characteristics shown in Figure 8. In this approximation, we assume grows linearly with until .
𝐼𝐼𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷 ≥ 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇
Figure 8: A linearized model of the MOSFET IV curves. p-channel MOSFET The p-channel MOSFET is exactly analogous to the n-channel MOSFET just described. N-type substrate replaces the p-type substrate and p+ wells replace the n+ wells. Since we are now trying to develop or “enhance” a p-type channel, the gate voltage applied must be negative relative to the Body/Source voltage. In this way, electrons are chased from the region of the designed conductive channel leaving charge-carrying holes in their wake.
CMOS N-channel MOSFET and p-channel MOSFET devices are often used together in a technology referred to as complementary MOS (CMOS) in logical devices. With p-channel MOSFETs in the upper portion of the circuit and n-channel MOSFETs in the lower portion of the circuit, an anti-symmetric structure results in a logically-valid manner of manipulating logic-valued voltages.
(a) (b)
A B Z 0 0 1 0 1 0 1 0 0 1 1 0
(c) Figure 9: CMOS circuits a) a logical inverter in 4-terminal circuit schematic form, b) a logic inverter in logic symbol form, and c) a “NOR” gate where the output is low when A or B is high.
The use of a “truth table” allows a structured way to list the output for all possible combinations of logical input values. Using the low resistance model for the Drain-to-Source channel for an enhanced channel and a high-resistance model for an inactive channel, it can be determined that the output of a properly-constructed CMOS device is always either “tied high” (connected through low resistance to ) or “tied low” (connected through low resistance to ground).
𝑉𝑉𝐷𝐷𝐷𝐷
A B Z 0 0 0 0 1 1 1 0 1 1 1 1
Figure 10: An inverter added to the output of the previous circuit results in an output that is high when A or B is high. The bits of the output column of the truth table have been “flipped” or “inverted”. Improperly-constructed CMOS circuits In lecture, we discuss the reasons why the following configurations are not true CMOS (they lack the complementary structure) and will not perform in a reliable manner for computer logic. By considering the complete truth table for each, we can find situations in which the output might be simultaneously tied high and tied low (resulting in a short between and ground) or the output sees high resistance to each and becomes indeterminate as its voltage will𝐷𝐷𝐷𝐷 hang near in a voltage-divider situation. 𝑉𝑉 𝑉𝑉𝐷𝐷𝐷𝐷 2
Figure 11: Improper CMOS designs where in a) the output can be tied simultaneously high and low (and the voltage source grounded) when A and B are different logic values and in b) the output is tied neither high nor low when A and B are different logic values. Power Consumption It is somewhat mysterious, but well-documented, that it requires an energy of to charge a capacitor to an energy of . Without getting into the rationale of why 50% of the energy2 is lost in the charging 1 𝐶𝐶𝑉𝑉 process, we can make2 note that there will be a factor of 2 difference between the power delivered by 2 𝐶𝐶𝑉𝑉 the source and the power stored in a capacitive load.
Using this knowledge, the power consumed by a single MOSFET may be calculated by
= 2 Where is the activity factor (percentage of the𝑃𝑃 clock𝑎𝑎𝑎𝑎 𝑎𝑎cycles𝑉𝑉 for which the transistor is actively switching, given as a fraction between 0 and 1), is the switching frequency in Hz, is the effective capacitance𝑎𝑎 of the CMOS’s output load in farads, and is the system’s switching voltage in volts. The switching of CMOS circuits is the largest source of𝑓𝑓 power consumption in computer𝐶𝐶 chips. An n-chip device with an average activity factor of and the same𝑉𝑉 general clock frequency, capacitance, and operating voltage would have a power consumption given by 𝑎𝑎 = 2 Computer circuit designers spend significant resources𝑃𝑃 𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 in𝑉𝑉 reducing the factors contributing to the power equation. Registers Registers are combinations of gates with feedback that serve as computer’s working memory. Each register element is a bit which can be 0 (low) or 1 (high).