Proteus Version 8.6

Layer Stackup & Smart Vias Assembly Variants Serpentine Length Matching Proteus VSM for Cortex-M3

Introduction

We are pleased to announce that Proteus V8.6 is now in public Beta testing. This is a significant release with a focus on PCB Design automation and includes feature improvements across the entire design workflow.

Layer Stackup & Smart Vias

The layer stackup of a PCB is basically the number of cores in the board and the order in which they are assembled to make the final PCB. For multi-layer boards the information provided in the stackup helps the software make intelligent decisions during board layout.

Probably the biggest impact of different stackups is in drill ranges or drill passes. When you specify the stackup, Proteus is able to work out the legal, manufacturable set of default drill passes for the layout. You can then add or remove drill passes if you need to. When you are then routing a track and you place a via, the software will automatically choose the smallest via range from source layer to destination layer. We call these smart vias because, after configuring the stackup, you no longer need to worry about via ranges.

The stackup also allows you to specify plane layers separately from signal layers. A plane layer will contain no tracking and can be auto-managed by Proteus after creation. Proteus understands plane layers during both manual and auto-routing and will prevent track placement. It will also re-generate the planes to ensure that the planes’ pull-back from the board edge is maintained during board edge changes.

Information in the layer stackup is exported in the Gerber X2 cadcam readme file to allow you to pass as much information as possible to the board manufacturer.

Assembly Variants

Assembly Variants provide a simple method of managing multiple product configurations in a single schematic/pcb project. This is done by specifying the fitted or not fitted status of each component on a per variant basis.

The most common use for assembly variants is to have a budget or midrange version of a product in which some components are not fitted. It is also used a lot with pullup resistors on a microcontroller port to indicate a hardware revision to the firmware running on the MCU.

In Proteus, the user interface is managed by the Design Explorer which has been rewritten to include a column for each variant, allowing the user to easily add/remove components from that product variant. A global combo-box in Proteus then controls the active variant and Proteus then manages this information through all of the output systems, changing the BOM Report, the Pick and Place files, the Assembly Drawings, the 3D Viewer and any export for MCAD as required. Serpentine Routing / Length Matching

Length matching of tracks is an essential step in ensuring correct timing at the signal receiver for high speed transmissions. Proteus includes support for automatic length matching of tracks via a simple select and match user interface. Lengths are matched within a specified tolerance and, if vias are used, the lengths of the vias are taken from the layer stackup information discussed earlier.

Much of the difficulty with length matching lies in the arrangement of the extra trace used to lengthen the shorter routes (often called the serpentine). Depending on the signal rise time, the frequency of the signal, the requirement for via sites on the PCB and many other factors the PCB designer may need to adjust or constrain serpentine height and width. In Proteus, this is all handled via a single dialogue form where the topology of the serpentine can be controlled. You can also adjust either an absolute or a relative tolerance for the length match according to the timing budget for your interface. Finally, you can choose to restrict the serpentine route to be regular height only and to be centred on the original track position.

Multiple routes (e.g. an address bus) can be matched by selecting them all and then invoking the length match command from the context menu on one of the tracks. The target length for all of the routes is stored after a successful length match and the pre-production check will check that the tracks remain length compliant before the board goes to manufacture.

Automatic length matching requires PCB Design Level 2 or higher.

Proteus VSM for ARM® Cortex™-M3

Proteus 8.6 includes new Cortex-M3 variants from the popular ST MicroElectronics range. The following variants are included with the initial release:

• STM32F103C4 • STM32F103R4 • STM32F103T4 • STM32F103C6 • STM32F103R6 • STM32F103T6 As always, the cycle accurate models in Proteus cover all of the main on-board peripherals in all models of operation. In the case of the STM32 variants this includes the DMA, ADC, USART, Timers, SPI, I2C, CRC, and watchdog(s). What’s Next?

Version 8.6 represents a major stepping stone on our roadmap for PCB Design in Proteus. Our next point release (Version 8.7) will almost certainly be based around manual routing improvements. We have for some time now been working on push and shove manual routing and expect the first version of that technology to be released with ersionV 8.7.

Meanwhile, we plan to incrementally add more features to help with high speed PCB design alongside our general product features. If there is anything in particular you would like to see in Proteus, please send us an e-mail to [email protected] and let us know.

Labcenter Electronics Ltd. Head Office Labcenter Electronics Ltd. USA Office 21 Hardy Grange, Grassington, BD23 5AJ, United Kingdom. 411 Queen Street, Suite 201, Newmarket, Ontario, Canada, L3Y 2G9 Tel: (+44) 1756 753440, Fax: (+44) 1756 752857 Toll Free: (+1) 866-499-8184, Fax: (+1) 905-898-0683 Web: www.labcenter.com, Email: [email protected]. Web: www.labcenter.com, Email: [email protected] Product Guide

Electronics Design

From Concept To Completion

abcenter www.labcenter.com E l e c t r o n i c s Integrated Package on the other hand, expert users tend to become frustrated if they cannot do the things they have to do often as quickly DESIGN www.labcenter.com The Proteus Design Suite comprises a fully integrated abcenter and easily as possible. SUITE E l e c t r o n i c s EDA package with modules for schematic capture (ISIS), circuit simulation (PROSPICE), PCB layout (ARES) and In Proteus, we have addressed the first issue by making the embedded co-simulation (VSM). The simulation functions editors work very much like the standard Windows The Proteus Design Suite combines schematic capture, SPICE circuit simulation, take place entirely within the schematic editor whilst ISIS applications that every computer literate user is already and PCB design to make a complete electronics design system. Add to that the and ARES share a common, easy to use, Windows user familiar with. In addition, detailed, graphical tutorials help interface. All of which reduces the time it will take you to the newcomer become productive as quickly as possible. ability to simulate popular micro-controllers running your actual firmware, and you master the software. Meanwhile, the expert user will soon appreciate that the have a package that can dramatically reduce your development time when Naturally, ISIS and ARES are themselves tightly editors are largely modeless. Objects can be placed, wired, compared with a traditional embedded design process. integrated, offering both forward and backward annotation moved, edited and deleted without having to switch and a unique Design Explorer which allows you to between several different modes. navigate and cross probe between the schematic, netlist Finally, all users - beginner and expert alike - will and PCB databases. System Components Company Profile appreciate that detailed context sensitive help is never more than a mouse click away, whilst expert technical help Labcenter Electronics Ltd. was founded in 1988 by § is no more than a phone call away. ISIS Schematic Capture - an chairman and chief software architect John Jameson. The easy to use yet extremely initial launch of the Proteus Design Suite followed soon The VSM Advantage powerful tool for entering after and has since benefited from over 18 years The Proteus Design Suite is wholly unique in offering the your designs. continuous development, evolving into one of the most ability to co-simulate both high and low-level micro- cost effective, fully featured EDA packages on the market. controller code in the context of a mixed mode SPICE §PROSPICE Mixed mode With current sales in over 50 countries spanning the globe s circuit simulation. With this Virtual System Modelling

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t SPICE simulation - industry Labcenter is continuously expanding both its product facility, you can transform your product design cycle, i portfolio and its customer base. standard SPICE3F5 reaping huge rewards in terms of reduced time to market f simulator combined with high Our goal is to provide you, the customer, with the best and lower cost of development. e speed digital simulator. package at the best price. To achieve this our company focus is threefold : If one person designs both the hardware and software, then n § that person benefits because the hardware design may be ARES PCB Layout - high Product Innovation changed just as easily as the software design. In larger e performance PCB design When deciding development strategies we focus on system with automatic Modern User Interface organizations where the two roles are separated, the usefulness, timesaving capabilities and customer feedback. software designers can begin work as soon as the hardware B component placer, rip-up We introduced the world to complete embedded software Much of the power of an application can be lost on its

e Modelling lets you co- budget annually (indeed, almost exponentially in recent r simulate embedded software years!) - product innovation backed by a world class for popular micro-controllers software development team is one of our primary strengths The VSM Advantage u and has allowed Proteus to grow into a truly complete

t alongside your hardware CAD system. Wait up to 2 weeks for PCB fabrication design. Schematic PCB Physical Software System a Continuous Development Design Layout Prototype Development Testing Unlike some packages on the market today our policy is, e System Benefits and always has been, one of continuous development on § F Integrated package with features that reduce the time to market for our customers. common user interface and Typically, we release three to four versions per year with Hardware Mods fully context sensitive help major functional enhancements in addition to maintenance m make for a quick and easy and minor releases as required. This focus on development With traditional design tools, software development and system testing cannot begin until a makes us more dynamic as a company and allows us the PCB and physical prototype are available - incurring a delay of up to 2-3 weeks. And if e learning process. flexibility to provide both new functionality and something is wrong with the hardware design, the whole process must be repeated. t §Technical support direct from maintenance releases to the customer more frequently. s the program authors means Customer Care We believe that customer care is a keystone of our success. y that expert help is available Schematic Software System PCB Working when you need it. Our technical support is free both via telephone and email Design Development Simulation Layout Prototype S for professional users and our support staff are all ü §Virtual Prototyping with experienced users of the software. Direct channels exist to Proteus VSM substantially the development team allowing us to provide quick and Hardware Mods cuts both software and comprehensive responses to even the most complex hardware development time problems. We consider user feedback to be of vital importance when determining development schedules for Using Proteus VSM, software development can begin as soon as the schematic is drawn, and and cost. new releases and have a formal system for logging and the combination of hardware and software can be thoroughly tested before physical prototyping. prioritising implementation of such features. Junction dots are placed and removed automatically. As Multi-Element Parts well as saving time, this avoids ambiguities that might The way in which ISIS represents library parts allows for otherwise arise. Manual placement of dots is also allowed, Intelligent Schematic Input System all the common possibilities: single element (e.g. 555 should you prefer to place a dot and then wire to it. timer), homogenous multi-element (four 7400 gates), and Hierarchical Design heterogenous multi-element (relay coil and contacts). ISIS lies right at the heart of the PROTEUS system and is far more than just another As well as supporting normal multi-sheet designs Gate elements are allocated automatically as you place schematics package. It combines an exceptionally powerful design environment with the (equivalent to a circuit spread over several pieces of components, and can be changed subsequently either by ability to control most aspects of the drawing appearance. Whether your requirement is the paper), ISIS supports hierarchy within a design. In other manual editing or through back-annotation from ARES. rapid entry of complex designs for simulation & PCB layout, or the creation of attractive words, a particular component can be defined as a module Connectors can also be represented as individual pin which is then represented by a further circuit diagram. The elements such that they can be distributed across the schematics for publication, ISIS is the tool for the job. hierarchy can be nested to an arbitrary number of levels, schematic, rather than having to wire everything back to a and modules can be drawn as standard components, or as single part. special sub-circuit blocks on which the interface ports can Component Properties Publication Quality Schematics be placed and removed on the fly. Each component in your design can have an arbitrary Features ISIS provides you with full control of the drawing appearance in terms of line widths, fill styles, colours and Full Support for Buses number of properties or attributes. Some properties control §Produces publication quality fonts. This enables you to produce attractive schematics Buses are used to represent multiple parallel connections, specific functions of the software (e.g. PCB package, or schematics. like you see in the magazines rather than the 'thin line' typically for data or address lines in microprocessor simulator model) but you can also add your own properties designs. ISIS provides not only a bus wire, but also the to hold other information such as stock codes or §Style templates allow diagrams often associated with older CAD software. Once ability to define components and sub-circuits with bus component costs. customization of supplied library your drawing is complete you can export it as a graphics pins. Therefore, a 32 bit processor bus connection between Furthermore, when a library part is created, default values parts. file or copy it to the clipboard for incorporation in other documents. This makes ISIS ideal for use in producing processor and memory can be represented as a single wire, and 'Property Definitions' can be supplied. Property §Mouse driven, context sensitive technical documentation, academic papers, project reports, saving both drawing time and space on the diagram. definitions provide a plain English description of the user interface. property and cause it to be displayed in its own editing as well as being an excellent front end for PCB design. Device Libraries §Automatic ‘follow me’ wire The drawing appearance is defined in terms of a style field when the component is edited. You can even specify ISIS comes with a device library including over 10,000 routing and junction dot template - especially useful if you want to apply a ‘house appropriate range limits for numeric values, and keyword parts. The libraries include standard symbols, transistors, placement/removal. style’ to all your designs. Furthermore, the scheme allows lists for strings. A special type for PCB packages allows for e diodes, thermionic valves, TTL, CMOS, ECL, you to customize the appearance of the library parts browsing of the ARES libraries. r §Hierarchical design including microprocessor and memory parts, PLDs, analog ICs and supplied with the package. parameterization of sub-circuit op-amps as well as manufacturer specific libraries from u component values. National Semiconductor, Philips, Motorola, Teccor, Texas t and Zetex. More libraries are being created as part of an §Full support for buses including

p ongoing programme. sub-circuit ports and bus pins. Visual Packaging Tool a §Preview of PCB footprints whilst selecting components and Matching schematic and PCB library parts is greatly

C making new library parts. simplified by the packaging tool. This displays the PCB footprint alongside the pins of the schematic part and §Comprehensive representation

c allows both textual and graphical entry of pin numbers for for homogenous and i each pin name.

t heterogeneous multi-element parts including connectors. a §Sophisticated management of component properties including m customization of the relevant Report Generation

e dialogue forms. Context Sensitive User Interface ISIS supports many 3rd party netlist formats making it §Large and growing component h Much thought has gone into making the most common suitable as a front end for use with other software. library of over 10,000 parts, drawing operations as quick and easy as possible. In The Bill of Materials report can be configured to include c most complete with ready to use particular, ISIS has no wiring mode per se. Instead, you whichever component properties you wish, and can also simulator models. can place a wire at any time by clicking on a component

S include column totals for selected numeric properties. § pin or on a previously placed wire. In addition, place, edit, Netlist formats: Labcenter SDF, Equally useful is the ERC report which lists possible move and delete operations can be achieved directly with SPICE, SPICE-AGE, Tango, wiring mistakes such as unconnected inputs, conflicting the mouse, without having to go through menus or icons. Boardmaker, EEDesigner, outputs and mis-typed net-labels. Futurenet, Racal & Valid. This makes ISIS very quick to use indeed. §Electrical Rules Check and Bill Wire Auto-Router of Materials reports. Placing a wire can be as simple as clicking on the two pins “We use the Proteus suite regularly and we really appreciate both the simple user §Output to any Windows printer you want to connect - the Wire Auto-Router does the rest. interface and the number of features. When we have faced a limit or a problem, the device in colour or monochrome. But if you want a wire in a particular place, you can just support response has always been fast and focused. Proteus is a good solution for click at the intermediate corners. The Wire Auto-Router §Graphical export in WMF, BMP, reasonably complex design.” also operates when components are moved, automatically DXF, EPS and HPGL formats. fixing up the affecting wiring. Gael Salles - ST MicroElectronics Junction dots are placed and removed automatically. As Multi-Element Parts well as saving time, this avoids ambiguities that might The way in which ISIS represents library parts allows for otherwise arise. Manual placement of dots is also allowed, Intelligent Schematic Input System all the common possibilities: single element (e.g. 555 should you prefer to place a dot and then wire to it. timer), homogenous multi-element (four 7400 gates), and Hierarchical Design heterogenous multi-element (relay coil and contacts). ISIS lies right at the heart of the PROTEUS system and is far more than just another As well as supporting normal multi-sheet designs Gate elements are allocated automatically as you place schematics package. It combines an exceptionally powerful design environment with the (equivalent to a circuit spread over several pieces of components, and can be changed subsequently either by ability to control most aspects of the drawing appearance. Whether your requirement is the paper), ISIS supports hierarchy within a design. In other manual editing or through back-annotation from ARES. rapid entry of complex designs for simulation & PCB layout, or the creation of attractive words, a particular component can be defined as a module Connectors can also be represented as individual pin which is then represented by a further circuit diagram. The elements such that they can be distributed across the schematics for publication, ISIS is the tool for the job. hierarchy can be nested to an arbitrary number of levels, schematic, rather than having to wire everything back to a and modules can be drawn as standard components, or as single part. special sub-circuit blocks on which the interface ports can Component Properties Publication Quality Schematics be placed and removed on the fly. Each component in your design can have an arbitrary Features ISIS provides you with full control of the drawing appearance in terms of line widths, fill styles, colours and Full Support for Buses number of properties or attributes. Some properties control §Produces publication quality fonts. This enables you to produce attractive schematics Buses are used to represent multiple parallel connections, specific functions of the software (e.g. PCB package, or schematics. like you see in the magazines rather than the 'thin line' typically for data or address lines in microprocessor simulator model) but you can also add your own properties designs. ISIS provides not only a bus wire, but also the to hold other information such as stock codes or §Style templates allow diagrams often associated with older CAD software. Once ability to define components and sub-circuits with bus component costs. customization of supplied library your drawing is complete you can export it as a graphics pins. Therefore, a 32 bit processor bus connection between Furthermore, when a library part is created, default values parts. file or copy it to the clipboard for incorporation in other documents. This makes ISIS ideal for use in producing processor and memory can be represented as a single wire, and 'Property Definitions' can be supplied. Property §Mouse driven, context sensitive technical documentation, academic papers, project reports, saving both drawing time and space on the diagram. definitions provide a plain English description of the user interface. property and cause it to be displayed in its own editing as well as being an excellent front end for PCB design. Device Libraries §Automatic ‘follow me’ wire The drawing appearance is defined in terms of a style field when the component is edited. You can even specify ISIS comes with a device library including over 10,000 routing and junction dot template - especially useful if you want to apply a ‘house appropriate range limits for numeric values, and keyword parts. The libraries include standard symbols, transistors, placement/removal. style’ to all your designs. Furthermore, the scheme allows lists for strings. A special type for PCB packages allows for e diodes, thermionic valves, TTL, CMOS, ECL, you to customize the appearance of the library parts browsing of the ARES libraries. r §Hierarchical design including microprocessor and memory parts, PLDs, analog ICs and supplied with the package. parameterization of sub-circuit op-amps as well as manufacturer specific libraries from u component values. National Semiconductor, Philips, Motorola, Teccor, Texas t and Zetex. More libraries are being created as part of an §Full support for buses including

p ongoing programme. sub-circuit ports and bus pins. Visual Packaging Tool a §Preview of PCB footprints whilst selecting components and Matching schematic and PCB library parts is greatly

C making new library parts. simplified by the packaging tool. This displays the PCB footprint alongside the pins of the schematic part and §Comprehensive representation

c allows both textual and graphical entry of pin numbers for for homogenous and i each pin name.

t heterogeneous multi-element parts including connectors. a §Sophisticated management of component properties including m customization of the relevant Report Generation

S include column totals for selected numeric properties. § pin or on a previously placed wire. In addition, place, edit, Netlist formats: Labcenter SDF, Equally useful is the ERC report which lists possible move and delete operations can be achieved directly with SPICE, SPICE-AGE, Tango, wiring mistakes such as unconnected inputs, conflicting the mouse, without having to go through menus or icons. Boardmaker, EEDesigner, outputs and mis-typed net-labels. Futurenet, Racal & Valid. This makes ISIS very quick to use indeed. §Electrical Rules Check and Bill Wire Auto-Router of Materials reports. Placing a wire can be as simple as clicking on the two pins “We use the Proteus suite regularly and we really appreciate both the simple user §Output to any Windows printer you want to connect - the Wire Auto-Router does the rest. interface and the number of features. When we have faced a limit or a problem, the device in colour or monochrome. But if you want a wire in a particular place, you can just support response has always been fast and focused. Proteus is a good solution for click at the intermediate corners. The Wire Auto-Router §Graphical export in WMF, BMP, reasonably complex design.” also operates when components are moved, automatically DXF, EPS and HPGL formats. fixing up the affecting wiring. Gael Salles - ST MicroElectronics Partial Simulation of Large Designs combination of SPICE3F5 and our own digital simulator Interactive Mixed Mode Circuit Simulator Where PROTEUS is being used to enter an entire design substantially outperforms XSPICE based systems, allowing for PCB layout, it may be inappropriate to run simulation many interactive simulations to run in real time. experiments on the entire schematic. For example, it does Fully Compatible with Manufacturers’ Models not usually make sense to simulate crystal oscillators as PROSPICE is a state of the art mixed mode circuit simulator that operates in conjunction More and more component manufacturers are providing analogue circuits when testing the digital logic that they SPICE models for their wares as well as the traditional data with the ISIS schematic capture environment. Based around the industry standard drive. PROSPICE saves you from carving up the schematic books. By choosing PROSPICE you will be able to gain SPICE3F5 analogue kernel, with our own extensions for mixed mode simulation and by supporting partial simulation of the design. The circuit maximum benefit from this resource - we have made a topology is analysed and only those components located interactive circuit animation, PROSPICE provides a powerful, interactive environment in between the input stimuli and the measurement points are which to develop and test your designs. included in the simulation. Excellent Modelling Tools If you need to create your own component models, System Features Fully Integrated Environment PROTEUS provides an excellent environment in which to Circuit simulation within PROTEUS is conducted entirely do so. The support for hierarchical design in ISIS enables §Fully integrated with schematic from within the ISIS schematic capture module. Graphs you to create a virtual test jig in which the component capture environment. appear alongside the components on the schematic, with model can be developed. This means that any changes to §Supports both Graph Based and circuit stimuli (generators) and probes being placed the model can be evaluated quickly and easily prior to Interactive Circuit Simulation. directly on the wiring. The circuit can be simulated at any storing the model as a pre-compiled netlist. time by pressing the space bar, making the edit-simulate §Simulation Advisor helps with PROSPICE also comes complete with a comprehensive set cycle extremely rapid - far more so than in packages where locating problems in the design of primitives (i.e. building blocks) with which to construct the simulator is a separate application. or simulation. your own models, whilst a DLL based API is also available for really complex modelling tasks. point of using Berkeley code to parse the SPICE netlists in Analogue Simulation SPICE3F5 Simulator Kernel order to guarantee best possible compatibility. And to get §Genuine Berkeley SPICE3F5 you started, we have gathered over 5000 SPICE models PROSPICE is based around the industry standard analogue simulator kernel with from the Internet and linked them to appropriate schematic SPICE3F5 analogue simulator developed at Berkeley extensions for true mixed mode symbols in ISIS. A further 3000 of our own models make University, California. n operation. up a total of over 8000 models supplied with the package.

o §Graph Based Analyses: Feature Rich Digital Simulation i Operating Point, Transient, PROSPICE incorporates a fully featured event driven t Frequency, DC Transfer Curve, digital simulator which is automatically invoked whenever

a DC Parameter Sweep, AC digital components are present. The digital simulation

l Parameter Sweep, Noise, paradigm correctly models timing, glitch behaviour, Distortion, and Fourier, Input & floating inputs and undefined states - beware that not all so u Output Impedance. called mixed mode simulators are anything like as good. §Advanced primitives include PLD Modelling m

i MOSFET Level 3, BSIM version Graph Based or Interactive Simulation PROSPICE includes special digital primitives which 3, MESFET, lossy transmission In addition to traditional graph based circuit simulation, represent PLD fusemaps. These devices can be used to S line and expression based construct models of any programmable logic device.

PROSPICE offers fully interactive circuit animation. You arbitrary source. Specific models for popular PLD devices are included in

t can control your design using mouse operated component the supplied component libraries. i §Direct compatibility with models (e.g. switches, pots) and observe what is manufacturers' SPICE models. happening from on screen indicators (e.g. LEDs, 7 seg. The information on how the device is programmed is read u directly from the JEDEC file produced by your PLD §Over 8000 models supplied with displays, meters). Uniquely, it is possible to design your It contains the latest convergence techniques and primitive

c assembler. Therefore, you are not tied to using any the package. own actuators and indicators, making the system suitable models. PROSPICE uses Berkeley’s source code wherever

r for modelling the actual peripherals of a real design. possible, guaranteeing best possible compatibility both in particular PLD development system. i Digital Simulation Additionally, numerous virtual instruments are provided terms of numerical results, and support for manufacturers’ Conformance Analysis SPICE models. §Event driven digital simulation including an Oscilloscope, a Logic Analyser, a Signal This unique feature compares a new set of simulation C models timing, glitch and floating Generator, and Digital Pattern Generator. These operate in True Mixed Mode Simulation results against reference data at pre-determined sampling input behaviour. much the same way as their real world counterparts, PROSPICE incorporates extensions to standard SPICE points. Coupled with VSM co-simulations of embedded making for a very intuitive approach to circuit simulation. §Fusemap models allow which allow it to model digital circuitry using an event software, it becomes an extremely powerful quality simulation of PLDs directly from Simulation Advisor driven paradigm. This is much more efficient than assurance tool; changes to the hardware or software can be checked for unwanted side effects entirely automatically. JEDEC files. Whether you are running a graph based or interactive attempting to model the transistor level behaviour. The §Full set TTL and CMOS models simulation, PROSPICE records any problems with the complete with timing information. design (e.g. logic contentions) or the simulation (convergence failure) to a log file. The messages are colour "After review of all available simulation packages, the performance power and capability § Conformance analysis facilitates coded for severity and you can navigate to any related of the Labcenter Proteus suite have proved invaluable to our cycle time on design of automatic testing of embedded component or net on the schematic. Better still, there is prototypes. Highly recommended for both professional and educational use, providing a systems. help available for simulation error messages enabling you cost effective solution to complex problems.” to understand and fix the cause of simulation failures as quickly as possible. Tony Beddard - Vice President - Accent Optical Technologies Partial Simulation of Large Designs combination of SPICE3F5 and our own digital simulator Interactive Mixed Mode Circuit Simulator Where PROTEUS is being used to enter an entire design substantially outperforms XSPICE based systems, allowing for PCB layout, it may be inappropriate to run simulation many interactive simulations to run in real time. experiments on the entire schematic. For example, it does Fully Compatible with Manufacturers’ Models not usually make sense to simulate crystal oscillators as PROSPICE is a state of the art mixed mode circuit simulator that operates in conjunction More and more component manufacturers are providing analogue circuits when testing the digital logic that they SPICE models for their wares as well as the traditional data with the ISIS schematic capture environment. Based around the industry standard drive. PROSPICE saves you from carving up the schematic books. By choosing PROSPICE you will be able to gain SPICE3F5 analogue kernel, with our own extensions for mixed mode simulation and by supporting partial simulation of the design. The circuit maximum benefit from this resource - we have made a topology is analysed and only those components located interactive circuit animation, PROSPICE provides a powerful, interactive environment in between the input stimuli and the measurement points are which to develop and test your designs. included in the simulation. Excellent Modelling Tools If you need to create your own component models, System Features Fully Integrated Environment PROTEUS provides an excellent environment in which to Circuit simulation within PROTEUS is conducted entirely do so. The support for hierarchical design in ISIS enables §Fully integrated with schematic from within the ISIS schematic capture module. Graphs you to create a virtual test jig in which the component capture environment. appear alongside the components on the schematic, with model can be developed. This means that any changes to §Supports both Graph Based and circuit stimuli (generators) and probes being placed the model can be evaluated quickly and easily prior to Interactive Circuit Simulation. directly on the wiring. The circuit can be simulated at any storing the model as a pre-compiled netlist. time by pressing the space bar, making the edit-simulate §Simulation Advisor helps with PROSPICE also comes complete with a comprehensive set cycle extremely rapid - far more so than in packages where locating problems in the design of primitives (i.e. building blocks) with which to construct the simulator is a separate application. or simulation. your own models, whilst a DLL based API is also available for really complex modelling tasks. point of using Berkeley code to parse the SPICE netlists in Analogue Simulation SPICE3F5 Simulator Kernel order to guarantee best possible compatibility. And to get §Genuine Berkeley SPICE3F5 you started, we have gathered over 5000 SPICE models PROSPICE is based around the industry standard analogue simulator kernel with from the Internet and linked them to appropriate schematic SPICE3F5 analogue simulator developed at Berkeley extensions for true mixed mode symbols in ISIS. A further 3000 of our own models make University, California. n operation. up a total of over 8000 models supplied with the package.

a DC Parameter Sweep, AC digital components are present. The digital simulation l Parameter Sweep, Noise, paradigm correctly models timing, glitch behaviour, Distortion, and Fourier, Input & floating inputs and undefined states - beware that not all so u Output Impedance. called mixed mode simulators are anything like as good. §Advanced primitives include PLD Modelling m i MOSFET Level 3, BSIM version Graph Based or Interactive Simulation PROSPICE includes special digital primitives which 3, MESFET, lossy transmission In addition to traditional graph based circuit simulation, represent PLD fusemaps. These devices can be used to S line and expression based construct models of any programmable logic device.

PROSPICE offers fully interactive circuit animation. You arbitrary source. Specific models for popular PLD devices are included in t can control your design using mouse operated component the supplied component libraries. i §Direct compatibility with models (e.g. switches, pots) and observe what is manufacturers' SPICE models. happening from on screen indicators (e.g. LEDs, 7 seg. The information on how the device is programmed is read u directly from the JEDEC file produced by your PLD §Over 8000 models supplied with displays, meters). Uniquely, it is possible to design your It contains the latest convergence techniques and primitive

c assembler. Therefore, you are not tied to using any the package. own actuators and indicators, making the system suitable models. PROSPICE uses Berkeley’s source code wherever

r for modelling the actual peripherals of a real design. possible, guaranteeing best possible compatibility both in particular PLD development system. i Digital Simulation Additionally, numerous virtual instruments are provided terms of numerical results, and support for manufacturers’ Conformance Analysis SPICE models. §Event driven digital simulation including an Oscilloscope, a Logic Analyser, a Signal This unique feature compares a new set of simulation C models timing, glitch and floating Generator, and Digital Pattern Generator. These operate in True Mixed Mode Simulation results against reference data at pre-determined sampling input behaviour. much the same way as their real world counterparts, PROSPICE incorporates extensions to standard SPICE points. Coupled with VSM co-simulations of embedded making for a very intuitive approach to circuit simulation. §Fusemap models allow which allow it to model digital circuitry using an event software, it becomes an extremely powerful quality simulation of PLDs directly from Simulation Advisor driven paradigm. This is much more efficient than assurance tool; changes to the hardware or software can be checked for unwanted side effects entirely automatically. JEDEC files. Whether you are running a graph based or interactive attempting to model the transistor level behaviour. The §Full set TTL and CMOS models simulation, PROSPICE records any problems with the complete with timing information. design (e.g. logic contentions) or the simulation (convergence failure) to a log file. The messages are colour "After review of all available simulation packages, the performance power and capability § Conformance analysis facilitates coded for severity and you can navigate to any related of the Labcenter Proteus suite have proved invaluable to our cycle time on design of automatic testing of embedded component or net on the schematic. Better still, there is prototypes. Highly recommended for both professional and educational use, providing a systems. help available for simulation error messages enabling you cost effective solution to complex problems.” to understand and fix the cause of simulation failures as quickly as possible. Tony Beddard - Vice President - Accent Optical Technologies testing using a large number of test-case programs and a How do I take Measurements? conformance mechanism that verifies that the behaviour of Proteus VSM comes with a set of virtual instruments Virtual System Modelling the programs is as expected. including an oscilloscope, logic analyser, signal generators What Debugging Facilities are Provided? and so on. These allow you to take measurements on your design just as you might with a physical prototype. Better Proteus VSM is a unique family of products for co-simulation of microprocessor based designs. Proteus VSM contains a fully featured built in source level debugger. As you would expect, this features high and low still, we also include master/slave SPI and I2C protocol The simulated micro-controller chip runs your firmware just as in real life, and you can interact level source code stepping, breakpoints, watch window, analysers offering functionality equivalent to very with it using a large range of peripheral models and powerful debugging tools. Proteus VSM is memory windows and so on. In addition, you can set expensive desktop instruments. available for a number of popular micro-controller families. Each VSM package includes a copy of breakpoints which will trigger on hardware conditions, and What other Devices are Modelled? ISIS for schematic capture and a true mixed mode interactive simulation engine based on inspect the internal status of external devices (e.g. LCD The real power of Proteus VSM stems from the fact that ProSPICE. Traditional graph based simulation is also available as an optional extra. displays, I2C memories), enabling you to find subtle you can simulate your firmware as it interacts with a problems in your designs much more quickly than with simulation of an entire hardware system. To this end, we conventional tools. provide models for hundreds of common embedded system Features You can also use Proteus VSM in conjunction with components including: What is Proteus VSM? rd § selected 3 party IDEs. For example, the Proteus VSM §7-Segment displays, LEDS, lamps and logic indicators. True co-simulation of CPU and Proteus VSM combines mixed mode circuit simulation, analog/digital electronics. MPLABä Viewer displays your hardware design in a §Alphanumeric and Graphical LCD displays. animated components and full hardware models of popular window inside MPLAB and allows you to debug your code § §Extensive built in debugging micro-controllers. Proteus VSM not only simulates the exactly as you would on a physical prototype. All the usual Universal (i.e. user definable) matrix keypad. facilities including register and software running on the micro-controller at the instruction debugging features of MPLAB are available including §Buttons, switches and potentiometers.

n memory contents, breakpoints level, but also simulates the on-board peripherals (ADC, single step, breakpoints, watch window and so on. §Piezo sounder and loudspeaker. USART etc.) right down to waveform level at the device and single stepping. § o pins. This allows the micro-controller to interact with any DC, stepper and servo motor models.

i § Watch window and watchpoint analogue or digital electronics connected to it. For §RAMs, ROMs and I2C EEPROMs. t expression breakpoints. example, if the program code writes to a port, the logic §Assorted I2C, SPI and 1-Wire I/O expanders and other

a §Source level ‘C’, BASIC and levels in the circuit change accordingly and, if the circuit peripheral devices. l assembly debugging supported changes the state of the processor’s pins, this will be seen §Storage devices e.g. ATA/IDE hard drive. for selected development tools. by your program code just as in real life. u §COM port and ethernet physical interface models §Multi CPU designs no problem. providing for interaction between the simulation and

m the real world. Supported CPU Families i Also, of course, your simulations can make use of any of § Microchip PIC12, PIC16, PIC18 the 8000 or so standard electronic component models that S and PIC24. are included with PROSPICE. - §8051/8052 including Philips and Which Compilers can I Use? o Atmel variants Proteus VSM can simulate the execution of binary files §AVR, Tiny AVR and Mega AVR (e.g. HEX) produced by any compiler. However, if you C

e Parallax BASIC Stamp. problems in both hardware and software much faster than ELF/DWARF, or UBROF. l you could when working on a physical prototype. l §More models always under Alternatively, if you use one of the IDE debug drivers such development. as the Proteus VSM MPLAB Viewer, then you can use any

o Diagnostics setup and simulation log showing trace messages from the compiler supported by that IDE.

r Benefits What can I do with it? alphanumeric LCD display model. Please check our website for detailed information about t If you are involved in developing any kind of embedded §Write, debug and test system compiler support for each Proteus VSM package. systems, then Proteus VSM will allow you to commence

n firmware before a physical software development before there is a physical prototype prototype is available.

o illegal instruction) from both LEDs and you can add your own models to the system too.

r CPU and peripheral models Consequently you can try out your micro-controller detect hard to find programming software on a virtual version of your entire product. c

i errors for you. How Accurate are the CPU Models? “I have to say at this point that in my opinion that Proteus VSM is absolutely ACE. While I §Massive productivity gain over Each CPU model is programmed to function as described try not to be too public in my delight for products, I can’t stop myself now, I have saved

M traditional embedded design in the manufacturer’s datasheet. This includes instruction days and days using this tool. Only today I got some code working where I had 2 PICs methods. See ‘The VSM execution times, interrupt priorities, interrupt latency, sleep talking to each other and monitored the timing with the Logic analyser. Stopping now and Advantage’ flowchart on page 3, modes and much more. The on-chip peripherals are then to single step at crucial points. I doubt if I could have got it working without it. It's not and the testamonial, opposite. modelled to a similar level of detail and will generate the first time I have used the tool in this way but every time I do I'm so impressed.” realistic electrical waveforms at the device pins where appropriate. The models are also subject to extensive Timothy Box - TJB Systems Ltd testing using a large number of test-case programs and a How do I take Measurements? conformance mechanism that verifies that the behaviour of Proteus VSM comes with a set of virtual instruments Virtual System Modelling the programs is as expected. including an oscilloscope, logic analyser, signal generators What Debugging Facilities are Provided? and so on. These allow you to take measurements on your design just as you might with a physical prototype. Better Proteus VSM is a unique family of products for co-simulation of microprocessor based designs. Proteus VSM contains a fully featured built in source level debugger. As you would expect, this features high and low still, we also include master/slave SPI and I2C protocol The simulated micro-controller chip runs your firmware just as in real life, and you can interact level source code stepping, breakpoints, watch window, analysers offering functionality equivalent to very with it using a large range of peripheral models and powerful debugging tools. Proteus VSM is memory windows and so on. In addition, you can set expensive desktop instruments. available for a number of popular micro-controller families. Each VSM package includes a copy of breakpoints which will trigger on hardware conditions, and What other Devices are Modelled? ISIS for schematic capture and a true mixed mode interactive simulation engine based on inspect the internal status of external devices (e.g. LCD The real power of Proteus VSM stems from the fact that ProSPICE. Traditional graph based simulation is also available as an optional extra. displays, I2C memories), enabling you to find subtle you can simulate your firmware as it interacts with a problems in your designs much more quickly than with simulation of an entire hardware system. To this end, we conventional tools. provide models for hundreds of common embedded system Features You can also use Proteus VSM in conjunction with components including: What is Proteus VSM? rd § selected 3 party IDEs. For example, the Proteus VSM §7-Segment displays, LEDS, lamps and logic indicators. True co-simulation of CPU and Proteus VSM combines mixed mode circuit simulation, analog/digital electronics. MPLABä Viewer displays your hardware design in a §Alphanumeric and Graphical LCD displays. animated components and full hardware models of popular window inside MPLAB and allows you to debug your code § §Extensive built in debugging micro-controllers. Proteus VSM not only simulates the exactly as you would on a physical prototype. All the usual Universal (i.e. user definable) matrix keypad. facilities including register and software running on the micro-controller at the instruction debugging features of MPLAB are available including §Buttons, switches and potentiometers. n memory contents, breakpoints level, but also simulates the on-board peripherals (ADC, single step, breakpoints, watch window and so on. §Piezo sounder and loudspeaker. USART etc.) right down to waveform level at the device and single stepping. § o pins. This allows the micro-controller to interact with any DC, stepper and servo motor models. i § Watch window and watchpoint analogue or digital electronics connected to it. For §RAMs, ROMs and I2C EEPROMs. t expression breakpoints. example, if the program code writes to a port, the logic §Assorted I2C, SPI and 1-Wire I/O expanders and other a §Source level ‘C’, BASIC and levels in the circuit change accordingly and, if the circuit peripheral devices. l assembly debugging supported changes the state of the processor’s pins, this will be seen §Storage devices e.g. ATA/IDE hard drive. for selected development tools. by your program code just as in real life. u §COM port and ethernet physical interface models §Multi CPU designs no problem. providing for interaction between the simulation and

wish to single step the high level source code, you need to §ARM7 / Philips LPC2000. Finally, Proteus VSM provides extensive diagnostics from choose a compiler which can generate one of the supported r §Motorola Freescale HC11 and within the device models, allowing you to locate and fix source level debug formats such as COD, COFF, OMF51, e Parallax BASIC Stamp. problems in both hardware and software much faster than ELF/DWARF, or UBROF. l you could when working on a physical prototype. l §More models always under Alternatively, if you use one of the IDE debug drivers such development. as the Proteus VSM MPLAB Viewer, then you can use any

o Diagnostics setup and simulation log showing trace messages from the compiler supported by that IDE. r Benefits What can I do with it? alphanumeric LCD display model. Please check our website for detailed information about t If you are involved in developing any kind of embedded §Write, debug and test system compiler support for each Proteus VSM package. systems, then Proteus VSM will allow you to commence n firmware before a physical software development before there is a physical prototype prototype is available.

o to work on. § Evolve hardware and software As well as a particular CPU family, each Proteus VSM c design in tandem. package includes models for common peripheral devices - §Diagnostic messages (e.g. such as LCD displays, keypads, buttons, switches and o illegal instruction) from both LEDs and you can add your own models to the system too. r CPU and peripheral models Consequently you can try out your micro-controller detect hard to find programming software on a virtual version of your entire product. c i errors for you. How Accurate are the CPU Models? “I have to say at this point that in my opinion that Proteus VSM is absolutely ACE. While I §Massive productivity gain over Each CPU model is programmed to function as described try not to be too public in my delight for products, I can’t stop myself now, I have saved

M traditional embedded design in the manufacturer’s datasheet. This includes instruction days and days using this tool. Only today I got some code working where I had 2 PICs methods. See ‘The VSM execution times, interrupt priorities, interrupt latency, sleep talking to each other and monitored the timing with the Logic analyser. Stopping now and Advantage’ flowchart on page 3, modes and much more. The on-chip peripherals are then to single step at crucial points. I doubt if I could have got it working without it. It's not and the testamonial, opposite. modelled to a similar level of detail and will generate the first time I have used the tool in this way but every time I do I'm so impressed.” realistic electrical waveforms at the device pins where appropriate. The models are also subject to extensive Timothy Box - TJB Systems Ltd Power Planes Auto-Placement Advanced Routing & Editing Software ARES features the ultimate in power plane support - user Automatic component placement makes it possible to placeable polygonal regions within which inner boundaries design an entire board with the absolute minimum of effort are automatically created around existing pads and on your part. Alternatively, since the placer can operate tracking. Change the pads and tracking and the boundaries interactively, you can pre-place critical components first Our high performance netlist based PCB design software perfectly complements ISIS. are recomputed to maintain design rule clearances. and the let ARES auto-place the rest. Incorporating both automatic component placement and a highly effective rip-up and retry Thermal reliefs can be configured on a per zone or per pad Auto-Routing auto-router, ARES transfers both time and effort from you to your PC. On the other hand, if basis and you can choose whether to hatch or fill each Our grid based router is both flexible and fast and can polygon. Further options cater for keep out areas, stitching you prefer to route your boards manually, the system places relatively few restrictions on route using any track thickness or via width, at 90 or 45 and mixed analogue/digital grounding schemes. degrees, and on 1-8 layers. It was placed in the top how you go about the task. Category A in Electronics World’s most recent review of PCB software. Modeless Selection The Rip-Up & Retry mode enables it to remove and replace tracks which block others giving 100% completion Features Modeless selection means that you can select any object at on most medium density boards routed at 50 or 25 thou. § any time, independent of the current editor mode. Supports up to 16 copper Meanwhile, our innovative costing/scheduling logic Overlapping objects are distinguished by analysis of both copper layers with any angle reduces the via count by as much as four fold over other the exact mouse position and the current layer set. Better component placement and low-medium cost routers. pad-stacks. still, context highlighting gives you visual feedback resulting in quicker and more accurate object selection, The built in router also tidy pass which reduces both track §Modeless object selection especially on densely packed multi-layer boards. length and via count whilst improving the aesthetic quality with visual feedback. of your board at the same time. Netlist & Ratsnest Handling §Fully automatic ratsnest and For those users designing really high density SMT boards, During the placement phase, ARES displays both the force vector generation. where the built in router may struggle, we also offer the ratsnest and force vectors. Both are updated in real time ELECTRA shape based autorouter at substantial discounts. §Drag and Drop pin- when you drag components. Also as you place new Please see our website for full details of the latest offers. swap/gateswap. tracking, ARES shows you the nearest termination point Design Rule Checks § for the current route, again updated in real time. 3D Visualisation Acclaimed manual routing During manual routing, ARES checks each track as you ARES includes a built in 3D visualisation tool enabling system is ideal for netlist The system fully supports design modifications - if you place it and warns you if any design rules you to view your project in the context of a mechanical based manual routing. change the schematic and re-load the netlist, ARES will (physical/electrical) are broken via a simple indicator on flag up exactly which components and/or tracks are design prior to manufacture. §Gridless, polygonal power the status bar. Double click any design rule error and affected. Equally, pin-swaps and gate-swaps made in All components in the supplied package libraries come n planes with full control of fill ARES will show you its location on the board. ARES are automaticaly fed back to the schematic. with basic 3D characterisations whilst support is provided style and thermals. Package Libraries g to enhance any or all components with more detailed 3D i §Connectivity and physical The supplied libraries cover a large range of through hole models created in the industry standard 3DS format. design rule checkers to prove components including all the most common IC, transistor, s design integrity. diode and connector packaging types. We also supply as e §Package library includes over standard, the full IEC libraries for SMT footprints which includes all the standard discrete and IC packaging styles. 1500 standard footprints. D New packages can be created directly on the drawing § Full set of CADCAM output whilst ARES also supports general 2D drafting features. and panelization facilities.

B CADCAM Outputs §Pick and Place file for As well as providing the basic ability to output your PCB

C automatic insertion machines. to standard Windows printers, ARES provides a full set of §Built in 3D visualisation. features for professional board manufacturing. P Design Automation Gerber is supported in both RS274D and the newer §Automatic Component RS274X formats whilst a standard Excellon format file is Placement. produced for drilling machines. In addition, an ASCII file listing component positions and orientations is produced § Multi-strategy grid based Route Placement & Editing for use with Pick and Place machinery. auto-routing A Gerber Viewer is also provided allowing you to check § Manual routing makes no requirement that you start from Special routines for SMT the ratsnest lines (rubberbanding). You can place tracking that Gerber files contain the expected data, and to panelize Microchip® PICDEM2+™ rendered by the ARES 3D Viewer fanouts. in any way you wish and ARES will remove ratsnest lines boards prior to issuing them for manufacture. §Rip-Up & Retry for 100% as the connections are actually completed. routing on most boards. When editing routes, you can re-route or delete any section §Tidy pass reduces via count of a track, irrespective of how it was originally placed. “PCB design is our business. We review PCB layout software on an ongoing basis and and track length. Commands are also provided to change the thickness Labcenter has topped the list for the last 10 years. Certainly the most productive and very, and/or layer of any section of tracking. §Optional ELECTRA shape- very affordable. We have licences for other very expensive products but they don't get based router available. If thick tracks are laid between obstacles such as IC pads, much use.” ARES will automatically insert a narrower 'neck' in order to maintain the current design rules. Donald Kay - Don Alan Pty Power Planes Auto-Placement Advanced Routing & Editing Software ARES features the ultimate in power plane support - user Automatic component placement makes it possible to placeable polygonal regions within which inner boundaries design an entire board with the absolute minimum of effort are automatically created around existing pads and on your part. Alternatively, since the placer can operate tracking. Change the pads and tracking and the boundaries interactively, you can pre-place critical components first Our high performance netlist based PCB design software perfectly complements ISIS. are recomputed to maintain design rule clearances. and the let ARES auto-place the rest. Incorporating both automatic component placement and a highly effective rip-up and retry Thermal reliefs can be configured on a per zone or per pad Auto-Routing auto-router, ARES transfers both time and effort from you to your PC. On the other hand, if basis and you can choose whether to hatch or fill each Our grid based router is both flexible and fast and can polygon. Further options cater for keep out areas, stitching you prefer to route your boards manually, the system places relatively few restrictions on route using any track thickness or via width, at 90 or 45 and mixed analogue/digital grounding schemes. degrees, and on 1-8 layers. It was placed in the top how you go about the task. Category A in Electronics World’s most recent review of PCB software. Modeless Selection The Rip-Up & Retry mode enables it to remove and replace tracks which block others giving 100% completion Features Modeless selection means that you can select any object at on most medium density boards routed at 50 or 25 thou. § any time, independent of the current editor mode. Supports up to 16 copper Meanwhile, our innovative costing/scheduling logic Overlapping objects are distinguished by analysis of both copper layers with any angle reduces the via count by as much as four fold over other the exact mouse position and the current layer set. Better component placement and low-medium cost routers. pad-stacks. still, context highlighting gives you visual feedback resulting in quicker and more accurate object selection, The built in router also tidy pass which reduces both track §Modeless object selection especially on densely packed multi-layer boards. length and via count whilst improving the aesthetic quality with visual feedback. of your board at the same time. Netlist & Ratsnest Handling §Fully automatic ratsnest and For those users designing really high density SMT boards, During the placement phase, ARES displays both the force vector generation. where the built in router may struggle, we also offer the ratsnest and force vectors. Both are updated in real time ELECTRA shape based autorouter at substantial discounts. §Drag and Drop pin- when you drag components. Also as you place new Please see our website for full details of the latest offers. swap/gateswap. tracking, ARES shows you the nearest termination point Design Rule Checks § for the current route, again updated in real time. 3D Visualisation Acclaimed manual routing During manual routing, ARES checks each track as you ARES includes a built in 3D visualisation tool enabling system is ideal for netlist The system fully supports design modifications - if you place it and warns you if any design rules you to view your project in the context of a mechanical based manual routing. change the schematic and re-load the netlist, ARES will (physical/electrical) are broken via a simple indicator on flag up exactly which components and/or tracks are design prior to manufacture. §Gridless, polygonal power the status bar. Double click any design rule error and affected. Equally, pin-swaps and gate-swaps made in All components in the supplied package libraries come n planes with full control of fill ARES will show you its location on the board. ARES are automaticaly fed back to the schematic. with basic 3D characterisations whilst support is provided style and thermals. Package Libraries g to enhance any or all components with more detailed 3D i §Connectivity and physical The supplied libraries cover a large range of through hole models created in the industry standard 3DS format. design rule checkers to prove components including all the most common IC, transistor, s design integrity. diode and connector packaging types. We also supply as e §Package library includes over standard, the full IEC libraries for SMT footprints which includes all the standard discrete and IC packaging styles. 1500 standard footprints. D New packages can be created directly on the drawing § Full set of CADCAM output whilst ARES also supports general 2D drafting features. and panelization facilities.

B CADCAM Outputs §Pick and Place file for As well as providing the basic ability to output your PCB

Proteus PCB Design is available in five levels offering a range of design capacities and features to match your application. Level 1 is limited on both pin count and features whilst Level 2 is limited only in terms of design capacity and offers the full set of features. Level 3 is completely unlimited. PROSPICE interactive simulation is included with all levels as standard. The Advanced Simulation option which enables the graph based simulation features may be purchased as an optional add-on.

PROTEUS PCB DESIGN LEVEL 1/1+ LEVEL 2/2+ LEVEL 3 Max Number of Pins in Netlist 1000/2000 1000/2000 Unlimited Shape based power planes 1 per layer Unlimited Unlimited Standard Auto-routing ü ü ü Rip-up and Retry Routing ü ü Auto-Placement ü ü Gate-Swap Optimizer ü ü 3D Visualisation ü ü PCB DESIGN LIMITS based polygon merging. However, in Level 1, only one PROTEUS Levels 1 and 2 impose a limit for the number of power plane is allowed per layer - partial power planes and pins in the netlist. These limits apply when loading it into multiple power planes on one layer are supported in Levels ARES. Any number of pins may be placed on the PCB 2 and 3 only. iteself enabling you to exceed the limit by the odd AUTOROUTING component should the need arise. All PROTEUS Levels include a sophisticated multi-strategy Levels 1+ and 2+ offer double the design capacity but are autorouter. otherwise identical. In Levels 2 and 3, you also get rip-up and retry operation POWER PLANES which will give 100% completion on all but the most All levels of PROTEUS handle power planes using shape complex or densely packed boards. JUST A FEW OF OUR SATISFIED CUSTOMERS

ST Microelectronics Penny & Giles Aerospace UW Radiation Calibration Lab Motorola BBC Jefferson Lab Vikram Sarabhai Space Center Delphi Diesel Systems R W Beckett Corp Volvo SGS Thompson Lexmark International Inc. UCLH Xerox Upchurch Scientific, Inc. British Army SCIAD Branch Westcode Semiconductors Calgon Carbon Corporation Ferrari Britvic TRLabs British Nuclear Fuels plc Sony Ariens Company Guys and St. Thomas Hospitals Philadelphia Scientific Hewlett Packard The Audio Partnership plc Yamaha R&D WrightPatterson Air Force Base AMD Automation Qinetiq Northrop Grumman Corporation Data Process Gmbh British Antartic Survey Xenogen Corporation Zetex plc Intel Bell South Assemtech Europe Ltd. Rutherford Appleton Labs Los Alamos National Laboratory Panasonic Visteon Automotive Naval Air Warfare Center Microchip Technologies JET Joint Undertaking COM DEV Space Group Glaxosmithkline BAE Systems Electrolux Home Products British Gas plc Symbolic Sound Corporation Tom Baker Cancer Center Linear Technologies Accent Optical Technologies HEXFET America Philips Caterpiller Peterlee Dept of NAVY - EOD Sanyo Carlton Television Xenogen Corporation Gyrus Medical Ford BC Hydro National Rail Michelin Tyre Natural Resources Canada

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