Design of Interface Circuits for Capacitive Sensing Applications

by Fatemeh Aezinia M.A.Sc., University of Tehran, 2006 B.Sc., University of Tehran, 2003

Thesis Submitted In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

in the School of Mechatronic Systems Engineering Faculty of Applied Sciences

 Fatemeh Aezinia 2014 SIMON FRASER UNIVERSITY Summer 2014

Approval

Name: Fatemeh Aezinia

Degree: Doctor of Philosophy

Title of Thesis: Design of Interface Circuits for Capacitive Sensing Applications

Examining Committee: Chair: Gary Wang Professor

Behraad Bahreyni, P. Eng. Senior Supervisor Assistant Professor

Shawn Stapleton, P. Eng. Supervisor Professor School of Engineering Science

Mehrdad Moallem, P. Eng. Supervisor Professor

Ash Parameswaran, P. Eng. Internal Examiner Professor School of Engineering Science

Kambiz Moez, P. Eng. External Examiner Associate professor, Department of Electrical and Computer Engineering University of Alberta

Date Defended/Approved: August 08, 2014

Partial Copyright Licence

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Abstract

This thesis focuses on the design of integrated readout circuits for differential capacitive sensing applications. Such circuits are needed especially for interfacing with microsensors where capacitive transduction is predominantly used. The result of this research is the development of common framework for interface circuitries suitable for different sensing applications. These interface circuits were designed and fabricated in standard Complementary Metal-Oxide-Semiconductor (CMOS) processes and can be integrated into the design of various sensing systems. The proposed circuits in this work are characterized by high dynamic range, low power consumption, and adjustable sensing range. Such circuits promote easy-to-use user interfaces while having a low cost.

Three different circuit designs were proposed and form the highlights of this thesis. The first interface circuit is a novel realization of a synchronous demodulation technique. The main advantage of the proposed circuit compared to state-of-the-art is that it has a high sensing dynamic range of 112 and is capable of measuring capacitance as small as 30 with a total power consumption of 8.

Low power consumption is one of the most important design criteria for portable sensing systems besides accuracy and precision. Following this requirement, low power consumption is the main criterion in the second circuit proposed in this work. This circuit uses a switch-based capacitance-to-voltage converter that is designed and fabricated in 0.35 CMOS technology. This circuit had a low power consumption of 600. Its simple structure offers area and power advantages over the more complex circuits. In addition, its ratiometric sensing feature provides an adjustable sensing range which can be tuned for different applications. This circuit can detect capacitances as small as 230 in 1 range of capacitance.

To reduce the effect of parasitics on the circuit performance and improve the linearity, the design of the second circuit was enhanced. By using an additional block and an analog divider, the sensitivity of the circuit to parasitics was significantly reduced. On the other hand, a time based output allowed for the elimination of the analog buffers. The fabricated circuit consumed a total power of only 720 and was fabricated in

0.35 CMOS technology. Another advantage of this circuit over the previous designs is that the pulse-width output signal of this circuit can be more easily digitized.

The proposed circuits in this thesis have been tested with different types of sensors including humidity, motion, and variable MEMS capacitors. For all of them also, the measurement results are found to be in good agreement with the analytic and simulation results. These circuits can be used as standalone chips or can be integrated into the design of larger sensing systems.

Keywords: Interface circuit; capacitive sensors; wide dynamic range; low power consumption

Dedication

To my mother, father, and my husband for

their endless love and support

Acknowledgements

I would not have been able to make it to this point without the support of my supervisor Dr. Behraad Bahreyni. His patience, generous help, and wise suggestions helped me a lot during my PhD studies. Other than his thoughtful guidance throughout my research work, he taught me a lot about technical writing and technical presentation skills. I also thank, Dr. Shawn Stapleton and Dr. Mehrdad Moallem for their helpful comments and technical suggestions through my proposal defence. I also want to thank my examiners, Dr. Ash Parameswaran and Dr. Kambiz Moez for accepting to be on my committee despite their busy schedule and giving thoughtful comments and advice.

I would also like to thank anonymous reviewers of my research papers for their comments which helped me improve the quality of my works. Thanks to the computing system staffs at SFU, especially Chao Cheng, and fabrication team at CMC Microsystems for their helps in computing problem solving and their supports through the hard time before the deadlines. Further, I thank faculty, staff, and all graduate students in both School of Engineering Science and Mechatronic Systems Engineering at SFU. Every one of these people has helped me in my studies. Also thanks to NSERC Canada, Nokia Corporation, and IMRIS Company which supported part of this work through Grant.

I would also like to thank all my friends who gave me the energy all the time to work and all members of IMUTS lab for their supports and encouragements.

Finally, I wish to thank my beloved parents and sisters for their never ending love that always filled my heart with energy. Last but not least, I thank my love, Mani, for his emotional support as a husband, his sincere suggestions as a friend, and his technical advices as a colleague throughout my PhD program.

And I start this thesis in the name of God...

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Table of Contents

Approval ...... ii Partial Copyright Licence ...... iii Abstract ...... iv Dedication ...... vi Acknowledgements ...... vii Table of Contents ...... viii List of Tables ...... x List of Figures...... xi List of Acronyms ...... xvii

1. Introduction ...... 1 1.1. Background ...... 1 1.2. Motivation ...... 3 1.3. Organization of the thesis ...... 4

2. Literature review...... 5 2.1. Capacitive sensing ...... 5 2.1.1. Basic configuration of capacitive sensors ...... 5 2.1.2. Differential capacitive sensing ...... 8 2.1.3. Capacitive sensing based on coplanar electrodes ...... 8 2.2. Applications of capacitive sensing systems ...... 10 2.3. Interface electronics for capacitive microsensors ...... 19 2.3.1. Capacitance to voltage converters (C2V) ...... 19 2.3.2. Capacitance to frequency converters (C2F) ...... 22 2.3.3. Capacitance to current converters (C2C) ...... 24 2.3.4. Capacitance to pulse-width converters (C2PW) ...... 26 2.3.5. Capacitive to digital converters (C2D) ...... 26 2.4. Synchronous demodulation-based circuits ...... 28

3. Differential capacitive sensing circuit with extended dynamic range ...... 31 3.1. Conventional synchronous demodulator topology ...... 32 3.2. Expanding the dynamic range of circuits based on synchronous demodulation ...... 43 3.3. Circuit design ...... 43 3.4. Simulation results ...... 52 3.5. Experimental results ...... 57

4. Low power differential capacitance sensing ...... 62 4.1. Circuit design ...... 63 4.2. Simulation result ...... 70 4.3. Experimental Results ...... 76

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5. Linear, low power, capacitive sensing circuit with insensitivity to parasitics ...... 87 5.1. Circuit topology ...... 87 5.2. Simulation results ...... 95 5.3. Experimental results ...... 100

6. Conclusions and future work ...... 107 6.1. Summary of results ...... 107 6.2. Future works ...... 108 6.3. Publications ...... 109

References ...... 111

List of Tables

Table 3-1.Circuit characteristics and comparison ...... 60

Table 4-1. Minimum measurable capacitance ...... 83

Table 4-2. Interface circuit characteristics and comparison...... 85

Table 5-1. Minimum measurable capacitance ...... 104

Table 5-2. Interface circuit characteristics and comparison...... 105

List of Figures

Figure 2.1. Capacitor with two parallel plates...... 6

Figure 2.2. A simple structure of a distance-type capacitive sensor along with the curves showing capacitance and the related impedance value versus the gap displacement...... 6

Figure 2.3. A simple structure of two-parallel electrodes with overlapping...... 7

Figure 2.4. Parallel plate capacitor with guard ring...... 7

Figure 2.5. Two parallel plate capacitor in an area-type sensor...... 8

Figure 2.6. A simplified structure of a differential capacitive sensing...... 9

Figure 2.7. Coplanar-plate capacitive sensing...... 9

Figure 2.8. 2D capacitive position sensing by coplanar electrodes...... 9

Figure 2.9. A capacitive liquid-level detector...... 11

Figure 2.10. Cross-sectional view of a capacitive proximity sensor...... 11

Figure 2.11. Lateral (Y-direction) movement in comb structure...... 13

Figure 2.12. Transverse (X direction) motion in comb structure...... 13

Figure 2.13. Cross-sectional view of a finger in a comb structure before on top and after rotation at the bottom...... 14

Figure 2.14. Simplified structure of a capacitive strain sensor and the fabricated device. © [2003] IEEE [65] ...... 15

Figure 2.15. Transverse movement in capacitive sensors based on comb structure...... 16

Figure 2.16. The SEM micrograph of a typical torsional accelerometer on left, Close-up of a torsional beam on right © [1998] IEEE [61]...... 16

Figure 2.17. Schematic of a capacitive humidity sensor, close-up view of the upper, lower electrodes and polyimide column © [2000] IEEE [70]...... 17

Figure 2.18. Schematic of the sensing and reference capacitor made from the two metal layers of the CMOS process. © [2002] IEEE [72]...... 18

Figure 2.19. Top view of a fully fabricated pressure sensor on left and cross- sectional view on right. © [2011] IEEE [49] ...... 18

Figure 2.20. AC bridge sensing circuit...... 20

Figure 2.21. Rectifier-based capacitive sensing system including two current sense amplifiers, two diode rectifiers and an instrumentation amplifier...... 21

Figure 2.22. Readout circuit using switched capacitor charge amplification...... 22

Figure 2.23. Basic Colpitt Oscillator Circuit...... 23

Figure 2.24. Capacitance to frequency converter using an oscillator...... 24

Figure 2.25. Schematic of a capacitance to current converter...... 25

Figure 2.26. Schematic block diagram of a readout circuit based on pulse width modulation...... 26

Figure 2.27. Basic circuit diagram of a C2D convertor on top, The related signals on bottom...... 27

Figure 2.28. Synchronous demodulation technique...... 29

Figure 2.29. Reference signal and noise before and after passing through a synchronous demodulator in frequency domain...... 29

Figure 2.30. Using synchronous demodulation technique in interface circuit based on trans-impedance amplification...... 29

Figure 3.1. Synchronous demodulation circuit diagram...... 31

Figure 3.2. The overall view of the designed circuit...... 32

Figure 3.3. Schematic diagram of TIA...... 33

Figure 3.4. Schematic diagram of a synchronous modulator ...... 33

Figure 3.5. The overall view of the low-pass filter ...... 34

Figure 3.6. Three coplanar electrodes needed for monitoring hand movements...... 36

Figure 3.7. Electrical field distribution around a conductive object moving on top of three conductive electrodes is illustrated...... 36

Figure 3.8. Capacitance between electrodes ‘1’ and ‘2’ as well as the capacitance between electrodes ‘2’ and ‘3’ simulated in ANSYS...... 37

Figure 3.9. Differential capacitance between and simulated in ANSYS...... 38

Figure 3.10. Planar electrodes needed for monitoring hand movement...... 38

Figure 3.11. Readout circuit on PCB...... 39

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Figure 3.12. Measured results of the proposed sensing system when finger moves laterally...... 40

Figure 3.13. Measured results of the proposed sensing system when finger moves vertically ...... 41

Figure 3.14. Measurement results when an object moves laterally...... 42

Figure 3.15. Experimental results when an object moves vertically...... 42

Figure 3.16. A differential capacitance measurement circuit based on synchronous demodulation of reference signals. Employing feedback (dashed line/box) let us increase the dynamic range of the circuit significantly...... 44

Figure 3.17. Schematic view of the closed-loop configuration...... 45

Figure 3.18. Schematic view of the triangular-wave generator...... 45

Figure 3.19. Schematic view of the synchronous demodulator...... 46

Figure 3.20. Schematic view of the low-pass filter...... 46

Figure 3.21. Schematic view of the amplitude controller...... 47

Figure 3.22. Bode plot of the loop gain for the designed chip...... 49

Figure 3.23. Structure of the folded cascode operational trans-conductance amplifiers in low pass filter...... 51

Figure 3.24. Comparison of analytical and simulation results for the noise performance of the circuit...... 53

Figure 3.25. Simulated results show open- and closed-loop performance of the circuit with different sense capacitors...... 54

Figure 3.26. Schematic view of the switch...... 54

Figure 3.27. Schematic view of the triangular-wave reference signal generator with switch blocks...... 55

Figure 3.28. Layout view of the proposed circuit...... 56

Figure 3.29. Simulated reference signals produced by the circuit in open-loop (top) and closed-loop configurations when ...... 56

Figure 3.30. Photograph of the die fabricated in 0.35μm CMOS technology from Austriamicrosystems...... 57

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Figure 3.31. Photograph of the off-chip circuitry including the trans-impedance amplifier, demodulator, and the low-pass filter...... 58

Figure 3.32. The comb-shaped humidity sensor...... 58

Figure 3.33. Measured reference signals generated by the fabricated chip in open-loop and closed-loop configurations...... 59

Figure 3.34. Normalized output voltage versus the differential capacitance ( ) corresponding to different humilities as well as the linearized curve...... 60

Figure 4.1. Differential capacitive sensing...... 63

Figure 4.2. Schematic view of the main block on top, switching signals on the bottom...... 64

Figure 4.3. Output buffer circuitry...... 66

Figure 4.4. The diagram of the oscillator used for switching signal generation...... 67

Figure 4.5. Digital blocks used for generating the controlling signals...... 68

Figure 4.6. The schematic of the delay unit...... 68

Figure 4.7. Layout view of the proposed circuit...... 71

Figure 4.8. Noise simulation results of the proposed circuit...... 71

Figure 4.9. Schematic view of the transistors inside the switch in C-V converter...... 72

Figure 4.10. Schematic view of the buffer ...... 73

Figure 4.11. Simulation waveforms showing the effect of clock feedthrough, output voltage which is decreasing step by step and its close-up view...... 73

Figure 4.12. Simulation waveforms of the clock ( and its close-up...... 74

Figure 4.13. Simulation results of the proposed circuit including output voltage after and before buffering in two different cases: without common- node capacitance on top and with common-node capacitance on the bottom...... 75

Figure 4.14. Optical photograph of the fabricated chip...... 76

Figure 4.15. Common-centroid symmetrical structure for building the capacitance in clock generator...... 76

Figure 4.16. Circuit’s response to sensing capacitors’ variations...... 77

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Figure 4.17. Simplified model of a displacement sensor with three electrodes...... 77

Figure 4.18. Capacitance variations versus time on top, output voltage on the bottom based on measurement...... 78

Figure 4.19. A microscope photo of the MEMS variable capacitor including the thermal actuator and a close-up view of the comb structure...... 79

Figure 4.20. Total capacitance of the comb-shaped structure versus finger engagements...... 80

Figure 4.21. Theoretical values of the surface capacitance with comb-shaped structure versus finger engagements ...... 81

Figure 4.22. Changes in capacitance of the comb-shaped structure versus displacement based the simulation results...... 81

Figure 4.23. Changes capacitance values versus time...... 82

Figure 4.24. Changes in output voltage when the distance between two electrodes becomes smaller over time, based on experimental data and simulation results (dotted points)...... 82

Figure 4.25. Noise density the circuit measured by signal analyzer...... 83

Figure 4.26. Measured output voltage versus the ratiometric change in sensing capacitance...... 85

Figure 5.1. The main building block of the proposed circuit...... 88

Figure 5.2. Simplified schematic view of the two capacitance-to-voltage converters used for cancelling the parasitic effects...... 89

Figure 5.3. Simplified schematic view of the voltage divider...... 90

Figure 5.4. Simplified schematic view of the circuits for converting voltage division to a pulse-width using both falling and rising ramp signal...... 92

Figure 5.5. Simplified schematic view of a comparator when is negative...... 93

Figure 5.6. Simplified schematic view of a comparator when is positive...... 94

Figure 5.7. Simplified schematic view of the pulse width for falling ramp...... 94

Figure 5.8. Simplified schematic view of the pulse width for rising ramp...... 95

Figure 5.9. Layout view of the proposed circuit...... 95

Figure 5.10. Simplified view of switching unit on left and a comparator when is positive on right...... 96

Figure 5.11. Simplified view of a pulse-width generator when is positive...... 96

Figure 5.12. Simulation results of the proposed circuit’s response, when . and . ...... 97

Figure 5.13. Simulation results of the proposed circuit’s response when . and . ...... 97

Figure 5.14. Simulation results for pulse-width versus capacitance variations with parasitic capacitance and with parasitic capacitance...... 98

Figure 5.15. Simulation results for output voltage () versus capacitance variations with parasitic capacitance and with parasitic capacitance...... 99

Figure 5.16. Die photograph...... 99

Figure 5.17. Difference between two sensing capacitance generates pulse at the output...... 100

Figure 5.18. Measured results for two variable capacitors, while one of the capacitors () is not changed and the other one () is changed as labeled on the graphs...... 101

Figure 5.19. Experimental results show the readout response and output pulse- width when displacement of microsensor generates different capacitances (=8)...... 102

Figure 5.20. Effects of parasitic capacitance on (=1.65)...... 103

Figure 5.21. Effects of parasitic capacitance on pulse-width ( ) testing two variable capacitance (=1.65)...... 103

Figure 5.22. Readout’s behavior in measuring comb-drive capacitive microsensor...... 105

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List of Acronyms

AC Alternating current ADC Analog to digital converter AMS Austria-Micro-Systems C2C Capacitive to current C2D Capacitive to digital C2F Capacitive to frequency C2PW Capacitive to pulse width C2V Capacitive to voltage DC Direct current FET Field effect transistor GPS Global positioning system IC Integrated circuit LVS Layout versus schematic MEMS Micro electro mechanical systems MOS Metal-oxide-semiconductor OTA-C Operational Trans-conductance Amplifier with Capacitance PEVA poly-ethylene vinyl-acetate PCB Printed Circuit Board TIA Trans-impedance amplifier

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1. Introduction

1.1. Background

Developing Metal-oxide-semiconductor (MOS) transistor which is the fundamental building block of modern electronic devices, and is ubiquitous in modern electronic systems is one of the greatest achievements of the 20th century [1], [2], [3]. Over the past decades, continuous miniaturization of transistors has led to integrating a larger number of transistors on a single chip and production of increasingly complicated systems [4], [5]. Developing ICs in CMOS technologies launched new applications, including laptops, cellphones, electronic games consoles, and portable audio player/recorders, among others.

Fabrication technologies developed for IC industries were later employed to build micromechanical features with moving structures [6], [7]. These miniaturized integrated devices or systems that combine electrical and mechanical components are called micro-electromechanical systems (MEMS) [8], [9]. They have been widely manufactured for different purposes due to their inexpensive batch fabrication, miniaturized dimensions, and in some cases, compatibility with CMOS processes. Attention in this area has predominantly been focused on microsensor development. MEMS sensors typically convert a physical, chemical, or biological signal from surrounding environment to an electrical signal [10], [11]. The first commercially fabricated microsensor was a pressure sensor [12], [13].

In recent decades, MEMS sensors have penetrated different areas of daily life [14], [15]. They are used for example, in automotive industry in airbags and braking systems for navigation and safety [16], [17], in biomedical industry for implanted microsystems [18], in cellphones for motion sensors [19], [20], and in workplaces for air condition monitoring [21]. Micro-sensors can be categorized according to the basic

transduction mechanisms they employ, including piezoresistive [22], piezoelectric [23], capacitive [24], optical [25], etc.

Among different types of microsensors, capacitive sensors are most commonly used due to the relatively simple structure, high sensitivity, as well as inherently low temperature sensitivity [26], [27], [28]. These features make them suitable for a wide variety of sensing and measurement purposes such as proximity detection, linear and rotary position monitoring, acceleration detection, pressure measurement, and so on. However, the high impedance nature of a capacitor at low frequencies makes the sensor susceptible to parasitics and electromagnetic interference, necessitating careful design of interface electronics [29].

In capacitive sensors, changes in the electric field between the two electrodes of a capacitor lead to a change in the capacitance value. These variations usually occur by changing the area or distance between the electrodes ( or ) or the dielectric constant of the material (). These changes are related to the variations in the physical or chemical quantity of interest. The capacitance value is often measured indirectly and needs to be converted into a form that can be easily processed and in many cases digitized [30]. This is the role of the interface circuit. As a result, the growth of the market of capacitive sensors leads to increasing interest in research and development of suitable interface circuits.

In most applications, capacitance variations for micromachined devices can be small [31], [32]. Hence, the interface circuit is required to possess a good noise performance. In many cases, the capacitance value can vary widely, from less than one up to tens of . Thus, having a wide sensing range is required. In most cases, the interface circuit needs to remain insensitive to parasitic capacitances. Moreover, the interface circuits should be linear. Since, many of these micro-sensors are employed in mobile devices; low-power consumptions is also desired so that the sensing system can operate for a long period of time on a limited amount of energy [33], [34].

1.2. Motivation

Generally, the sensing systems consists of sensors, interface circuits, and signal conditioning blocks that may include a digital signal processing unit, a display and communication block. These systems are usually developed for particular purposes and sometimes require several design iterations for new sensing applications. For many applications, a common framework exists where a common interface circuit can be employed, letting only sensors and digital signal processing units be customized for specific applications. Such a generic readout circuit provides a flexible, easy to use, and low cost solution for various microsensing systems [35]. Therefore, designing a common readout circuit lowers the design, prototyping, and manufacturing costs of many sensing systems.

Several companies have offered solutions to address the needs for a common interface circuit. For example, AD7745 and AD7746 from Analog Devices are capacitance-to-digital converters designed for floating sensing capacitors and AD7747 for grounded sensing capacitors [36]. They have high resolution response at the cost of high measurement time (90 /) which limits their applications. Their power dissipation is on the order of , making them unsuitable for many wireless devices. In addition, the same company offers AD7150 with lower power consumption (300 ) with 1 resolution over 5 full range sensing, while lower resolutions or wider sensing range may be needed in some applications. Hence, one of the drawbacks of this interface is not having an adjustable sensing range. A disadvantage for all of these interfaces is their limited tolerance to parasitic capacitances. Also, often their performance is very sensitive to the current leakage of the capacitive sensor. On the other hand, designing interface circuits is pursued by many research groups [37], [38], [39]. Most of these systems were designed for industrial applications, where very low power consumption is often not the deciding factor. As a consequence, their power dissipation is unacceptably high for today’s mobile applications.

This study aims to propose multi-purpose readout architectures for capacitive sensing systems. These interface circuits were designed based on configurable blocks. The settings of these blocks can be adjusted according to the needs of different applications, such as dynamic range, sensitivity, minimum measureable capacitance,

and insensitivity to parasitics. The developed topologies were tested with several capacitive sensors at macro and micro scales in applications such as humidity, proximity, and displacement sensing.

1.3. Organization of the thesis

This thesis has been divided into six chapters. In Chapter 2, an overview of principle properties of capacitive microsensors and their applications is provided. This is followed by a discussion of various techniques for designing interface circuits. Recent works for improving the performance of the capacitive readout circuit are presented in details. Three circuit architectures are designed, analyzed, and tested which result in following chapters.

In Chapter 3, a capacitive measurement circuit based on synchronous demodulation is described. The basic operation of a synchronous demodulation has been tested by building a prototype on printed-circuit board. It is tailored for hand- gesture monitoring for consumer electronic devices such as cell phones. In order to expand the dynamic range of the circuit, a new feedback mechanism is added to the original circuit. This circuit was designed in 0.35 μ CMOS technology and tested with a humidity sensor.

To reduce the power consumption, an interface circuit based on charge transfer method was employed. The design and analysis of the switch-based capacitive to voltage converter is presented in Chapter 4. Simulation and experimental evaluations are also provided. Having a ratiometric capacitive sensing automatically extends the sensing range in this design. This topology was implemented in 0.35 μ CMOS technology and tested for position sensing. To eliminate the dependence of sensing response on the parasitic capacitance, a new technique is proposed in Chapter 5. In this design, a capacitance-to-pulse-width converter is built utilizing the main building block from the preceding design and addition of a voltage-to-pulse-width converter. Both simulation and experimental evaluations are provided. This circuit was also fabricated in 0.35 μ CMOS technology and tested with a position sensor as well as a variable MEMS capacitor. Conclusions for this study and future work are presented in Chapter 6.

2. Literature review

2.1. Capacitive sensing

Capacitive microsensor detects the changes of a physical or chemical stimulus by measuring the displacement or changes in dielectric properties of a material. In designing the sensing element structure, care should be taken to determine how the stimulus influences the capacitance value. The basic principles of capacitive sensors will be reviewed in the following.

2.1.1. Basic configuration of capacitive sensors

A simple configuration of a capacitive sensor is two parallel electrodes with distance and overlapping area (Figure 2.1). The capacitance value can be obtained from:

(2.1)

where is the permittivity of the vacuum, and is the relative permittivity of the dielectric in between the two electrodes.

Capacitive sensing based on change in gap

One of the methods used for capacitive sensing is based on changing the plates separation distance, (Figure 2.2). The capacitance is inversely proportional to the gap between the electrodes. If capacitive impedance is measured, the behaviour is linear. However, the output is nonlinear if the capacitance is measured directly instead. Hence, the direct measurement often requires further signal conditioning to compensate for the reciprocal relationship between the capacitance and its electrodes’ motion. One of the

Figure 2.1. Capacitor with two parallel plates. problems with parallel-plate capacitive sensor is its cross-sensitivity to motion along other axes. This problem can be remedied by fully enclosing one of the electrodes’ edges by the other (Figure 2.3). Having different dimensions ensure that the two plates are constantly overlapping and, as a result, mitigating errors caused by movement along the edges.

Another source of nonlinearity in a parallel plate sensor is the fringe fields along the edges of the two plates. Adding a guard ring to the sensor leads to a homogenous electric field between them and reduces the effects of this nonlinearity on measurement [40]. A guard ring is an extra electrode separated by an insulator that encloses the sensing electrode in the same potential. As illustrated in Figure 2.4, field lines are distorted at the edges of the guard electrode but remain uniform between sensing electrodes.

Impedance Impedance Capacitance

Displacement Displacement

Figure 2.2. A simple structure of a distance-type capacitive sensor along with the curves showing capacitance and the related impedance value versus the gap displacement.

Figure 2.3. A simple structure of two-parallel electrodes with overlapping.

Although, these methods lessen the nonlinear effects in capacitive sensors, the main drawback of using these sensors with varying gaps is the limit on useful range of motion. The reciprocal relationship between motion and capacitance as mentioned earlier limits the sensing range.

Capacitive sensing based on change in area

Another family of capacitive sensors work based on changes in overlap area between of the electrodes [41]. A transverse motion sensor is shown in Figure 2.5. The common area of the two plates is changed by the lateral movement of one of the plates against the other. Since the area and capacitance values are linearly proportional (see equation. (2.1)), measured capacitance is linearly related to the displacement. Same as distance-type sensors, area-type sensors are sensitive to spacing and tilt. Some of the cross-sensitivity errors can be reduced with modifying the electrode geometries [40]. The accuracy of these types of sensors depends on mechanical accuracy of the electrodes. Roughness of the electrodes’ surface, deformation, and varying distance between them can lead to nonlinear effects on these types of measurements.

Figure 2.4. Parallel plate capacitor with guard ring.

Impedance Displacement

Figure 2.5. Two parallel plate capacitor in an area-type sensor.

Capacitive sensing based on change in dielectric properties

Changes in dielectric properties of the medium between the electrodes also vary the capacitance (see equation (2.1)). A direct relationship between the relative permittivity of a dielectric and its capacitance value makes these capacitive sensors suitable for material characterization [42]. They may also be used to determine the position of the interface between various different types of materials. Humidity measurement and liquid level detection are well-known applications of this type of sensing [43]. For example, capacitive humidity sensor is usually composed of a material whose dielectric constant varies with humidity and a capacitor employing that material as the dielectric [44].

2.1.2. Differential capacitive sensing

Sensitivity to mechanical displacements can be improved by using an additional electrode in between of the two plates in both spacing and area variation techniques (see Figure 2.6). The three-plate sensor offers the well-known advantages of a differential system, such as rejection of common-mode interference [45]. The detection circuit measures the difference between two capacitances rather than an absolute value of one capacitance [46]. Depending on the sensing system, the measured value can be

proportional to or .

2.1.3. Capacitive sensing based on coplanar electrodes

Aside from the simple parallel plate capacitive sensors previously discussed, two coplanar electrodes may also be used for capacitive sensing (see Figure 2.7). The fringing field between the two electrodes defines the mutual capacitance between them [47]. Interference with this fringing field changes the capacitance value. For example,

Figure 2.6. A simplified structure of a differential capacitive sensing. moving one of the electrodes or changing the effective dielectric material result in capacitance variations.

The technique of the differential capacitive sensing can be extended to coplanar- plate capacitive sensors. One simple example of this structure is a 2D capacitive position sensor, as shown in Figure 2.8, where the dielectric properties of the human body affect the coupling between adjacent electrodes. Such an arrangement can, for example, be used for touchless display units.

Figure 2.7. Coplanar-plate capacitive sensing.

Figure 2.8. 2D capacitive position sensing by coplanar electrodes.

2.2. Applications of capacitive sensing systems

Capacitive microsensors are used in numerous macro and micro-devices for sensing different physical/chemical properties such as acceleration [48], pressure [49], strain [50], position [51], proximity [52], humidity [53], gas concentration [54], etc. An important advantage of capacitive sensing in such cases is the ease of the mass production and low cost [43]. Another advantage of using capacitive sensing is that the power consumption of these sensors is low. This is because ideal capacitors are perfect insulators at Direct Current (DC) frequencies; i.e., they do not require any DC current which makes them ideally suited for low-power applications. Their other advantages include:

 Simple structure

 Relative insensitivity to temperature

 Good resolution, stability, and speed

 Compatibility with microfabrication technologies

In this document, micro-scale sensors refer to devices that are batch fabricated through MEMS micromachining processes in contrast to macro-scale devices that are made through conventional serial assembly techniques. Some structures of capacitive sensors in macro-scales can be fabricated and used in micro-scales as well. The main distinction in that case will be batch fabrication versus serial assembly.

Macro-scale capacitive sensing applications

One benefit of capacitive sensing at macro-scales is that there is no physical contact between the measuring surfaces, which means that the sensor does not physically load the mechanical movement. One application of capacitive sensors is monitoring the liquid level in a container. For this application high resolution sensing is required that can be provided by capacitive sensing [55]. As shown in Figure 2.9, the electrode structure consists of a long electrode and one that is divided into insulated segments. At each time the test electrode is connected to readout circuit and the rest are

all connected to ground. Changes in the measured capacitance from one electrode to another provide information about the level of the liquid inside the tank.

A proximity sensor detects the presence of a nearby object without physical contact [52], [56]. Proximity measurement constitutes a large number of measurements made in science and technology. For many practical purposes, it is important to be able to measure small changes in distance between two parts.

Figure 2.9. A capacitive liquid-level detector.

Figure 2.10. Cross-sectional view of a capacitive proximity sensor.

The proximity sensor shown in Figure 2.10 works based on the principle of fringe capacitance between two electrodes with ring-shaped structure [57]. Bringing an object close to the fringing field increases the capacitance value. The target object can be either conductor or non-conductor.

Micro-scale capacitive sensing applications

The typical capacitive sensor arrangements produce small capacitances at micro-scales. The change in capacitance can be a result of a change in area, gap, or dielectric properties of the material between the two electrodes as discussed in section 2.1.1. Depending on the application requirements, MEMS designers can employ one of three mechanisms mentioned in the above to achieve the design objectives. For example, most pressure sensors operate based on the deflections of a membrane as a function of pressure. For capacitive pressure sensors, the change in capacitance is a result of the change in the gap between the membrane and a fixed electrode. For laterally moving structures, the area of the capacitive elements is limited due to the small thickness of MEMS structures (typically between 1μm and 100μm). Therefore, the change in capacitance as the structure moves is often rather small. To increase the effective area between the electrodes without modifying the microfabrication process, interdigitated electrodes are commonly used at micro-scales [58]. The interdigitated electrodes, often referred to as comb structures, increase the overlap area between the electrodes and can improve the output linearity.

Comb capacitors are used to measure lateral [59], transverse [60], and torsional [61] displacements. In lateral configuration, two planar fingers move towards each other as shown in Figure 2.11. When the top electrode moves toward the fixed electrode on the bottom, the capacitance value between the two electrodes increases. The amount of the capacitance can be found from:

(2.2)

Figure 2.11. Lateral (Y-direction) movement in comb structure.

where is the height of fingers, is the distance between the fingers, is the engagement length of fingers, and is the fringing capacitance, and is the number of fingers.

In transverse configuration, movement occurs sideways (see Figure 2.15) [62]. Moving the top beam along the X-axis changes the mutual capacitance. The amount of the capacitance is found from:

, (2.3)

Figure 2.12. Transverse (X direction) motion in comb structure.

As illustrated in Figure 2.13, in torsional configuration, one electrode rotates around one side of the beam. Varying the side overlapping area between the electrodes changes the mutual capacitance. For small angles, change in the mutual capacitance of this comb-structure with fingers can be found from [61]:

2 (2.4)

where is the length of rotating finger, is the length of fixed finger, is the distance between the fingers, and is the rotating angle.

The aforementioned comb structures can be used in different applications. Capacitive strain sensors employ changes in capacitance to measure the displacements of the beam due to external strain. They are used in advanced industrial applications, such as torque sensing in rotating shaft, blades, and ball-bearings [63], [64]. They can also be employed in biomechanical application such as spinal fusion detection [50]. A lateral comb configuration of a strain sensor with three amplifying beams for improving the device’s sensitivity is depicted in Figure 2.14 [65]. An external strain causes a displacement (∆) and the lateral movement of the comb-structures in different direction provides differential sensing which has better sensing performance compared to the single one.

Figure 2.13. Cross-sectional view of a finger in a comb structure before on top and after rotation at the bottom.

Transverse comb structures can also be employed for various purposes. For example, in force sensors, an external force moves one comb electrode respect to another one and as a result the mutual capacitance between them changes. One unit cell of a typical capacitive sensor is shown in Figure 2.15. Two fixed structures used in this unit act as a plate for two separate electrodes of the capacitors. Force causes the beam movement and results in decreasing one capacitor while increasing the other one. Higher number of unit cells enhances the sensitivity of the overall sensing system.

Torsional comb structure can be employed in acceleration sensing [66]. Capacitive MEMS accelerometers employ changes in capacitance to measure the displacements of the proof-mass due to external acceleration [67], [68], [69]. Figure 2.16 shows a capacitive accelerometer working based on torsional motion. The change in

Figure 2.14. Simplified structure of a capacitive strain sensor and the fabricated device. © [2003] IEEE [65]

capacitance happens because the overlapping area between comb electrodes varies. The direct relationship between capacitance and overlapping area enables the design of sensors with a wide full-scale range since the size of the air gap no longer limits the movement range of the electrodes.

Figure 2.15. Transverse movement in capacitive sensors based on comb structure.

Figure 2.16. The SEM micrograph of a typical torsional accelerometer on left, Close-up of a torsional beam on right © [1998] IEEE [61].

Figure 2.17. Schematic of a capacitive humidity sensor, close-up view of the upper, lower electrodes and polyimide column © [2000] IEEE [70].

The aforementioned capacitive sensors with comb structure work based on changes in area or gap. In some applications, changes in dielectric properties change the mutual capacitance between two comb-structure electrodes. Polymer coated materials are sensitive to humidity as well as the types of chemicals exposed to. Their transduction mechanism relies on the permittivity changes and swelling of the coating polymer exposed to humidity and chemical materials [71], [72]. For example, the polymer named poly-ethylene vinyl-acetate (PEVA) which swells on exposure to benzene can be used as a dielectric material of capacitive sensing to detect the concentration of benzene in the air [73]. Thus, capacitive sensors are useful for sensing the relative humidity and distinguishing the surrounding materials [74], [75].

As shown in Figure 2.17, the humidity sensor consists of a capacitive sensor with two electrodes which are electrically isolated from each other. The top electrode has a comb shape and is located in parallel to the bottom one. The dielectric layer consists of thousands of polyimide columns with relative permittivity sensitive to absorbing water [70].

Figure 2.18 shows a chemical capacitive sensor consisting of sensing and reference capacitance; each of them comprises two comb-structure metal layers. When the sensor is exposed to the target material, absorption from the material to the dielectric film takes place and results swelling in the polymer and increasing in dielectric permittivity. The sensitivity can be increased by maximizing the polymer volume in the region with strong electric field.

Figure 2.18. Schematic of the sensing and reference capacitor made from the two metal layers of the CMOS process. © [2002] IEEE [72].

Figure 2.19. Top view of a fully fabricated pressure sensor on left and cross-sectional view on right. © [2011] IEEE [49]

In addition to the comb-structure capacitive sensors, two parallel plate capacitive sensors are still a good choice in sensing large capacitances, especially when the gap between two plates varies in response to an external force. This method can be used in MEMS pressure sensors. Figure 2.19 shows top view of a pressure sensor as well as the cross-sectional view of the capacitive sensing element. It consists of a two parallel plane electrodes [49]. Increasing the diaphragm size, reducing diaphragm thickness, and decreasing sensing gap lead higher pressure sensitivity of a capacitive pressure sensor. In contrary, decreasing the sensing gap results in non-linearity and limited dynamic range of the sensing system.

2.3. Interface electronics for capacitive microsensors

A signal conditioning circuit to measure the capacitance value is needed to convert the capacitance change into a voltage [76], frequency [77], pulse-width [78], or current [79]. Depending on the output signals, different topologies of readout circuits can be employed [80], [81], [82]. In the following sections, different conversion techniques are presented with examples. Some state-of-the-art interfaces are introduced to enhance various design factors in capacitive sensing systems, such as resolution, dynamic range, power, and linearity.

2.3.1. Capacitance to voltage converters (C2V)

AC bridge

Using an AC bridge is a classic method for measuring changes in a capacitance. The principal function is similar to the resistive Wheatstone bridge where a balanced ratio of impedance results a balanced condition as indicated by a voltage detector. Changes in one of the impedances cause imbalance that is sensed [83]. In an AC bridge, this detector can be an oscilloscope, voltage amplifier, or any devices capable of registering small AC voltage levels (see Figure 2.20).

Figure 2.20. AC bridge sensing circuit.

Despite its simple structure, a major drawback of this circuit is its sensitivity to electrical interference between the bridge circuit and external bodies. A potential problem of this sensing circuit is the stray capacitance between either end of the voltage detector and ground. These stray capacitances result in current paths to ground, can affect the bridge balance, and causes nonlinearity of the sensor response.

Rectifying circuits

In this configuration, a reference voltage is processed by a circuit that converts the capacitors’ value to a voltage. The signal is then rectified and processed by a low- pass filter to generate a DC value proportional to the amplitude.

Figure 2.21 presents a differential capacitive sensing system using this topology [84]. Based on the capacitance variation, different current signals are generated. The generated currents are then fed to TIAs whose outputs are then passed through the diode rectifiers and filtered. The differential signal is finally fed to the input of an instrumentation amplifier. The gain control resistor of the instrumentation amplifier provides the option of dynamic range extension. Moreover, connecting the sensing electrodes to the virtual ground input node of the instrumentation amplifier reduces the sensitivity to interferences. However, one limitation of this topology is that the frequency of the reference signal should be more than 1/ to have a linear relationship between output and sensing capacitance. In addition, having diodes or diode-connected

Figure 2.21. Rectifier-based capacitive sensing system including two current sense amplifiers, two diode rectifiers and an instrumentation amplifier. transistors limits the amplitude of the signal before rectifier and decreases the output swing.

Switched-capacitor amplifying circuits

In switched-capacitor amplifier based readout circuit, switches are used to transfer the charge accumulated on the sensing capacitor to the output signal. In Figure 2.22, a simplified model of a switched capacitor amplifier is shown. Square-wave signal has been used for the excitation. In one phase , integrator’s capacitor is discharged and in the following phase , accumulated charges on sensing capacitance will be transferred to the output [85]. In this case, the output voltage is directly proportional to the differential capacitance ( ) and amplitude of the excitation voltage ():

∝ (2.5)

Figure 2.22. Readout circuit using switched capacitor charge amplification.

The main advantage of the switched-capacitor amplifier based readout circuit is its temperature insensitivity, as capacitors, when compared to resistors, are relatively insensitive to the temperature variations. Major drawbacks are the speed limitation and the need for non-overlapping clock signals. In MOS sampling circuits, channel charge injection and clock feedthrough of the switches lead to gain error, DC offset, and nonlinearity [86].

2.3.2. Capacitance to frequency converters (C2F)

Capacitance to frequency converters are simple and often require less power compared to C2V circuits. The output of these circuits is a quasi-digital quantity (frequency) and there is no need for an analog to digital converter in the front-end. On the other hand, the high sensitivity to process parameters of most practical implementations limits the achievable accuracy.

Linear oscillators

A linear oscillator can be based on an LC-tank where capacitor in the tank is variable [87]. The output frequency of a Colpitts oscillator shown in Figure 2.23 is

proportional to the fixed inductance ( ∝1⁄ ) [80]. These oscillators have less temperature sensitivity compared to most other types of the oscillator topologies. Their high power consumption and high frequency limits their applications in typical capacitive measurement. In addition, its frequency measurement can be very sensitive to the parasitic capacitances involved in the measurement of sensor and all external interferences [88].

Figure 2.23. Basic Colpitt Oscillator Circuit.

Nonlinear oscillators

Many topologies exist that operate based nonlinear elements or switches to produce a signal whose frequency is a function of a particular capacitor value. A simplified schematic of an example circuit is shown in Figure 2.24. The sensor capacitance is charged and discharged with constant currents (). The output voltage

drives the switch. The comparators convert the triangular voltage on the capacitor

to a square-wave and the multiplexer changes the output level.

Figure 2.24. Capacitance to frequency converter using an oscillator.

The comparators have two different threshold voltages (, ) to set the upper and lower limits of the triangular voltage. However, the effects of temperature and supply voltage variations on the output frequency are eliminated in this structure [77], [82]. For this particular design, the output frequency is a function of the charging/discharging currents, and hence, the circuit’s performance is sensitive to the variation of these currents. For many nonlinear oscillator circuits (e.g., relaxation type), the output frequency is a function of passive or active element values, which in general, adversely affect the stability of the oscillator signal. Nonetheless, these circuits often consume little power and are widely employed.

2.3.3. Capacitance to current converters (C2C)

A simplified model of this topology is shown in Figure 2.25. In this circuit, switches are controlled by a clock signal of period equal to ( ). During the discharge phase

(), and are closed and currents and are the same, thereby forcing to be zero. Differential current amplifier provides a virtual ground at its inputs and ideally nullifies the effect of the stray capacitances at these nodes [79]. As a result, when these two switches are open in measurement phase (), the input current () will be divided in two branches according to the ratio of the two capacitors and the output current can be found by:

(2.6)

where and are sensing capacitance, is the input current, and is the output current. These two switches (,) are needed to be closed periodically to avoid the saturation of the circuit that might occur because of a linear increase of the voltage at the sensor common node due to constant input current (. One of the advantages of this method is that adding or subtracting current signals are simple. Additionally, current amplification is possible through using simple current-mirror-like schemes for improved sensitivity [89]. Thus, capacitance to current converters are adopted to increase speed and simplify the circuit complexity and enable low-voltage, low-power operation [79], [84]. On the other hand, this solution is sensitive to the stray capacitance at the common node electrode which should be smaller than the sensing capacitance for proper operation. Another drawback is that current leakage in switches can lead to nonlinearity issues in the signal path and output signal.

Figure 2.25. Schematic of a capacitance to current converter.

2.3.4. Capacitance to pulse-width converters (C2PW)

Figure 2.26 shows a topology to produce a pulse-width modulated signal with pulse duration linearly proportional to a capacitance. In this circuit, sensing capacitance is charged and discharged by a DC current (. In charging phase ( is on), the slope of the triangular-wave signal after block is positive and is compared with a threshold voltage (. When this voltage becomes larger than the threshold voltage of the comparator, the output of the comparator becomes high.

One of the advantages of these types of readout circuit is that a digitized signal is produced without realizing the analog to digital converter. Hence, the hardware cost can be reduced. Besides, the output signal is a pulse stream, it can be transmitted over moderately noisy or nonlinear channels, such as RF or optical links [78], [90]. Furthermore, this signal can be easily read by a microcontroller or converted into an analog signal using only a low pass filter [78]. One of the drawbacks of these circuits is that the output frequency could not be higher than hundred kHz frequency band which limits the dynamic range.

Figure 2.26. Schematic block diagram of a readout circuit based on pulse width modulation.

2.3.5. Capacitive to digital converters (C2D)

In some applications, it is needed to have a digital output. Sigma-delta converters can be used for these purposes. They usually have high resolution and high accuracy

[91], [92]. However, due to the oversampling technique, the main disadvantage of this readout circuit is its long measurement time. Having a higher clock rate can lead to a higher measurement bandwidth but at the cost of higher power consumption and complexity of the circuit. Figure 2.27 presents a basic circuit diagram of a sigma-delta converter [42]. An amplifier with C in its feedback loop acts as an integrator. It is supposed that the output voltage of the integrator is negative at the beginning of the measurement. Thus, output of the comparator (D) is zero as shown in Figure 2.27. Both control signals (φ,φ) are low when is low. When clock () is high, is charged by

and in the second phase ( is low), the charge ( ) is transferred to . As long as the output of integrator ( /) is negative, comparator generates zero.

When it becomes positive, the charge of is transferred to . So, for times / and for times / will be added to the integrator’s output ( and are number of ones and zeroes in , respectively). the ratio of ones to the total numbers (⁄ )) equals to the ratio of (/) [42].

Figure 2.27. Basic circuit diagram of a C2D convertor on top, The related signals on bottom.

2.4. Synchronous demodulation-based circuits

Synchronous demodulation technique is a good solution in readout circuit design to reduce noise, increase linearity, and dynamic range. It is a common signal processing technique to extract weak signals from low-frequency noise and interferences. A simplified structure of a synchronous demodulator for a capacitance to voltage conversion is shown in Figure 2.28. It consists of a reference signal generator, an amplifier, a synchronous demodulator unit, and a low-pass filter. The reference signal is an AC signal that is typically in the range of 1 to 10 [40]. Different signals can be used for the excitation but square-wave and sinusoidal signals are most commonly used. Sine wave excitation is suitable for measuring small capacitances with high accuracy. However, on-chip generation of a sine wave reference signal is difficult. Square wave oscillators are easy to integrate on a single chip system, but nonlinear effects may reduce the performance of the circuit [79]. As illustrated in Figure 2.28, the reference voltage is connected to the sensing capacitance (). An amplifier is used to convert the capacitance value to an amplified AC voltage. After passing through the synchronous demodulator block, the low-pass filter produces a DC output signal with an amplitude and phase corresponding to the sensing capacitance value. Moreover, the low-pass filter limits the bandwidth, and thus, enhances the resolution.

Figure 2.29 illustrates the transformations in frequency domain when a sinusoidal reference signal passes through the test device and the synchronous demodulator topology. Synchronous demodulator block operates at the same frequency as the reference signal generator. After initial amplification and passing through the synchronous demodulation block, the amplified reference signal with a value proportional to is moved to low-frequency region. Finally, the low-pass filter limits the noise-bandwidth independently of the reference and input signal frequencies, making this circuit well-suited for low-noise measurement of small signals.

Figure 2.28. Synchronous demodulation technique.

Figure 2.29. Reference signal and noise before and after passing through a synchronous demodulator in frequency domain.

Figure 2.30. Using synchronous demodulation technique in interface circuit based on trans-impedance amplification.

Figure 2.30 demonstrates using a synchronous demodulation technique in a differential capacitive sensing system. In this design, a Trans-Impedance Amplifier (TIA) is used to convert the differential sensing capacitor to an amplified voltage. The output voltage of this circuit is directly proportional to the differential capacitors, excitation frequency (), and feedback resistor () of the TIA:

∝ (2.7)

As discussed in details earlier, this circuit architecture is one of the most common methods for measuring capacitance because of its high accuracy and flexibility. Measuring capacitance at higher frequencies and using synchronous demodulation allows for separation of the sensing signal from amplifier offset, 1⁄ noise, and other interferences located mainly in the low frequency range. In addition, differential sensing and using an amplifier with virtual ground input node results low sensitivity to parasitic capacitance and other environmental interferences. Limiting the bandwidth of the low- pass filter also provides high dynamic range and high resolution.

3. Differential capacitive sensing circuit with extended dynamic range

As mentioned in Chapter 2, differential capacitive sensing is often used to improve the sensing resolution and reject common-mode interferences. In differential sensing, the influence of undesired inputs and disturbances (e.g., temperature) is cancelled largely. Besides the differential sensing method, high performance readout circuits are needed to improve the efficiency of the sensing process.

Most sensor output signals are in the low-frequency band, where many interfering signals such as 1⁄ noise, op-amp offset, and main-supply interferences are also located [42], [93]. A good way to separate the sensor signal from the above- mentioned undesired interfering signals is to modulate the sensor signal to a higher frequency, so that it can be processed to eliminate 1⁄ noise, offset and main-supply interference [94], [95]. The modulated signal is shown by in Figure 3.1. After demodulation, the signal is converted back to the baseband frequency. A low-pass filter removes the undesired signals. The demodulation can easily be performed with a mixer (see Figure 3.1). The amplified input signal is demodulated, while the op-amp input noise and offset are chopped by the square-wave signal and passing through the low- pass filter.

Figure 3.1. Synchronous demodulation circuit diagram.

3.1. Conventional synchronous demodulator topology

A differential interface circuit working based on synchronous demodulation for capacitive sensing is designed. The block diagram of this circuit is shown in Figure 3.2 [96]. The circuit is composed of three main building blocks: a C2V converter, a synchronous demodulator, and a low-pass filter for reducing noise bandwidth and removing the high-frequency harmonics. The output is DC signal in correspondence to the capacitance changes. The configuration and working principle of these building blocks is described in detail in following sections.

TIA which plays the role of C2V converter translates the changes in capacitance to a voltage signal (see Figure 3.3). With sinusoidal waves with opposing polarities applied to the sense electrodes [96], the output voltage is:

sin cos (3.1) 2

where and are the two sensing capacitors, is the feedback resistor shown in

Figure 3.3 ( sin). The demodulator can be made using a differential amplifier and two switches that are controlled by reference signals phase shifted by 90° or 270° (see Figure 3.4).

Figure 3.2. The overall view of the designed circuit.

Figure 3.3. Schematic diagram of TIA.

Figure 3.4. Schematic diagram of a synchronous modulator

Figure 3.5. The overall view of the low-pass filter

The upper switch that is controlled by 90-degree phase-shifted signal passes the first half of the cycle of the output voltage of TIA (). The bottom switch that is controlled by 270-degree phase-shifted signal passes the second half of the cycle of the output voltage of TIA () which is become inverted by the differential amplifier. As a result, the out () becomes rectified and can be found by:

|cos | (3.2)

The final block of the interface electronic structure, which follows the synchronous demodulator, is a Bessel low pass filter to extract the DC component of the signal (see Figure 3.20). The average value of a periodic function can be calculated from (3.2) in which is the period of the periodic function and in this design is equal to .

1 (3.3) || 2

As a result, the output of the filter () which is a DC voltage whose level is proportional to the amplitude of the rectified sine wave from the previous stage (i.e.,

proportional to the difference between the capacitance of the sensing electrodes). The output voltage () is given by:

2 (3.4)

3.1.1. Using synchronous demodulation for differential capacitive sensing

As an example for potential applications of capacitive detection circuit based on synchronous demodulation, a circuit for touchless interfaces for mobile devices was designed and analyzed. In this experiment, three coplanar electrodes were used as a capacitive displacement sensor and an interface circuit to translate an object’s (e.g., user’s finger) movement on top of device display to a voltage signal. An analytical model presented by Chen et al [81] showed that the capacitance between two parallel coplanar electrodes in semi-infinite domain is directly proportional to the relative dielectric constant of the material on top of the surface. Since water has high dielectric constant

( 80), and human body is largely composed of water, finger displacement can change the capacitance significantly.

This sensor detects the displacement of a user’s hand or finger near the device surface in three-dimensional space. Compared to the sensor with one sensing element, using these electrodes differentially has lower sensitivity to environmental effects (e.g., temperature or humidity variations) [95]. The advantages of using capacitive transducers for motion monitoring over other methods based on video, sonar, or RF signals are low power consumption, small size, and low cost of construction [84], [97], [98].

As shown in Figure 3.6, the differential capacitive sensor is composed of three coplanar electrodes. When the finger represented by a conducting cylinder above the electrodes moves from side to side, the mutual capacitances between the sense electrodes and the centre reference electrode change correspondingly. Interfering with the electric field built between them is basically the reason of changes in the mutual capacitances. With the aid of another set of three electrodes along the other axis (e.g., y-axis), hand movement can be detected in two-dimensional (x-y) space (as discussed

Figure 3.6. Three coplanar electrodes needed for monitoring hand movements. in section 2.1.3). To trace hand movements along the z-axis (i.e., normal to the plane of electrodes) a single capacitive sensor (i.e., one pair of electrodes located on a plane perpendicular to z-axis) can be employed. Moving hand too far from the surface (more than 10 cm for our prototype) decreases the contribution of hand capacitance.

Figure 3.7. Electrical field distribution around a conductive object moving on top of three conductive electrodes is illustrated.

Finite element simulations were employed to study the field distribution around the sensing element. The structure is modeled by three rectangular elements as the electrodes and one circular element as a human finger. Since our body consists of ions, it is considered as a conductive material. Thus, both electrodes and finger were defined as conductors which were surrounded by a body of air around the structures. Selecting different material and geometry for the elements in sensing structure alters electric field distributions and mutual capacitance between them (see Figure 3.7).

Variation in mutual capacitance between two electrodes is illustrated in Figure 3.8 when the finger (located at 2 above the surface) is moved from 9 cm to the left to

9 to the right of center electrode. It can be seen that each of these capacitances ( and ) reaches its maximum where finger is located around the middle of that pair of electrodes. The differential capacitance (C ) is also illustrated in Figure 3.9.

200

C 180 23 C 12 160

140 Capacitance (fF)

120

100 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 Longtitude (cm)

Figure 3.8. Capacitance between electrodes ‘1’ and ‘2’ as well as the capacitance between electrodes ‘2’ and ‘3’ simulated in ANSYS.

40 30

10 (fF)

12 0 −C 23 −10 C −20 Differential capacitance −30

−40 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 Longtitude (cm)

Figure 3.9. Differential capacitance between and simulated in ANSYS.

To verify the proposed capacitive sensing and its sensitivity to the capacitance changes, a prototype including three electrodes on glass in both x and y directions and readout circuit were designed and implemented on a printed circuit board (PCB) (see Figure 3.10 and Figure 3.11). This circuit was based on the topology shown in Figure 3.2. Movement of a finger along x-y axis on top of these electrodes changes the differential capacitance in each direction. To separate the signals for x and y directions from each other, two different reference frequencies (250 and 300 ) were adopted.

Figure 3.10. Planar electrodes needed for monitoring hand movement.

Figure 3.11. Readout circuit on PCB.

In our measurement, the reference electrode in x and y directions are connected to 2 sinusoidal signals of 250 and 300 frequencies, respectively. Lateral displacement along x-axis and y-axis change the two output signals displayed by pink and yellow waveform in Figure 3.12. Also, normal displacement along z-axis generates voltage changes at the outputs. Depending on the location of the finger (on top of x-axis electrodes or y-axis electrodes), pink and yellow signals are created which are shown in Figure 3.13.

Measured responses of the sensing circuit are plotted in Figure 3.14 and Figure 3.15 while moving a finger laterally above the electrodes and vertically between each pair of electrodes. It can be seen in Figure 3.14 that the output voltage reaches its maximum when finger is in the middle of each pair of electrodes (i.e., between the sensing electrode and the middle electrode) and decreases when a finger is taken away from the sensing electrodes. According to these measured data, finger’s lateral movement from 9 to 4 which is related to the change of 5 differential capacitive sensing can be detected by this circuit.

Figure 3.12. Measured results of the proposed sensing system when finger moves laterally.

Figure 3.13. Measured results of the proposed sensing system when finger moves vertically

Figure 3.14. Measurement results when an object moves laterally.

Figure 3.15. Experimental results when an object moves vertically.

3.2. Expanding the dynamic range of circuits based on synchronous demodulation

Since every sensor has its own requirements for readout, a configurable sensor interface is crucial for successful implementation. This allows users to reuse a given circuit topology for several applications and adjust the sensing range and sensitivity for each particular application [85]. Although the synchronous demodulation topology provides a good noise performance, its dynamic range is limited especially if the circuit is realized using IC technologies.

In addition to being able to interface a wider variety of capacitive sensors, a large dynamic range is required especially when the sensing capacitance changes nonlinearly. In some cases, the gap between the two electrodes of a capacitive sensor changes during operation. Since the sensor sensitivity is inversely proportional to the gap, the measurements will be inherently nonlinear. Other phenomena such as structural deflections often exacerbate these nonlinearities [99]. It is therefore necessary that the signals from capacitive microsensors be measured with adjustable sensing range circuits to capture the wide range of input quantities. Depending on the microsensor and the application, the capacitance value can change from sub-fF to hundreds of pF, making design of such circuits challenging [100], [94].

In the next part, we present a circuit topology with adjustable sensing range for differential capacitive sensors. In this design, differential sensing is also employed to cancel or reduce the influence of interferences. The reference signals required for this measurement scheme were produced on-chip. The sensing range was increased using a novel feedback mechanism that modified the reference signal amplitudes.

3.3. Circuit design

The topology proposed here uses the output signal of the open-loop topology in Figure 3.16 and, through a feedback network, adjusts the amplitude of the reference signals, in accordance to the sensed capacitor values. This ensures that the amplifier remains in its linear region and enhances the linear sensing range of the system.

The designed circuit consists of a TIA, a synchronous demodulator, amplitude controller, and a low pass filter, as shown in Figure 3.16, [101]. Capacitors ∆ and ∆ are differentially driven by reference signals and . These signals are in the form of triangular-wave signals and are produced on chip. As shown in Figure 3.17, they are generated through charging and discharging of on-chip timing capacitors, , using two constant current sources with value , which are switched by a symmetric square control signal, . The current alteration is labeled in this figure which is zero in open loop case. The control signal, , is produced by an on-chip relaxation oscillator and is a square wave signal with period 1/, 50% duty cycle, and zero DC [101].

The TIA transforms the difference in currents through the two capacitors into a square-wave voltage signal. The output of the amplifier is then fed to a switching synchronous demodulator stage which uses to rectify the amplifier’s output. Schematic view of the demodulator stage is depicted in Figure 3.19, while half of the signals will be passed through each of the two switches at every cycle. A low-pass filter extracts the DC component of the demodulated signal, which is directly proportional to the differential changes in input capacitors. The low pass filter using the operational trans-conductance amplifier with capacitance (OTA-C) technique is employed in this design. This filter topology is suitable for IC implementation because no resistors are used and the capacitance values are much smaller than active RC filters. The schematic view of the second order integrator filter is shown in Figure 3.20.

Figure 3.17. Schematic view of the closed-loop configuration.

Figure 3.18. Schematic view of the triangular-wave generator.

Figure 3.19. Schematic view of the synchronous demodulator.

Figure 3.20. Schematic view of the low-pass filter.

During the open-loop operation, currents used to charge and discharge the timing capacitors are the same (i.e., ), and hence, and have the same amplitude. The DC output voltage is given by:

2 Δ (3.5)

where is the transfer function of filter and is the amplitude of the reference signal, which can be found from:

/ 1 (3.6) 2

where , where is fixed but can be modified during the closed loop operation as explained below. The circuit sensitivity at low frequencies is given by:

(3.7) 2

When feedback loop is closed, the amplitude of reference signals is modified through changing the charge/discharge currents of the timing capacitors, and . A current signal, , which is proportional to changes the charge/discharge current at these capacitors, and thus, changes the amplitude of the triangular-wave reference signals. The signals across these timing capacitors are separated from the sensor capacitors through voltage buffers. The net result of the closed loop operation is a balanced change to the amplitude of the signals applied to the test capacitors, i.e.,

∆ will be driven with a smaller signal than ∆. The amplitude controller block in Figure 3.21 converts the output signal from the filter to proper control voltages (/ and /) to adjust the charge/discharge currents.

Figure 3.21. Schematic view of the amplitude controller.

Circuit Analysis

When the loop is closed, the output of TIA is given by (see Figure 3.17):

2 (3.8) ∆

In frequency domain, the output signal can be expressed as:

∆ 2 ∆ 2 (3.9) ∆ 12

where is gain of the voltage to current converter in Figure 3.17. A second order filter was used in the circuit and we have:

(3.10)

In closed-loop configuration, the loop gain is given by:

(3.11) 2

For the designed circuit, the frequency of the control signal, , was 175 . Other circuit parameters were 9, 1, 100Ω, 51, and

175. It can be shown that 3 is needed to maintain a 60° phase margin. Bode plot of the loop gain is shown in Figure 3.22 for 10 and 30.

20 0 10 −20 0 −40 −10 −60 −20 −80 −30 −100 Phase −40 Amplitude −120 Magnitude (dB) −50 Phase −140 −60 −160 −70 −180 3 4 5 6 7 10 10 10 10 10 Frequency (Hz)

Figure 3.22. Bode plot of the loop gain for the designed chip.

Employing equation (3.6) to simplify equation (3.5) at low frequencies, we have:

(3.12) 2 2

As a result, the maximum differential capacitance that the open-loop circuit can linearly measure is limited by the swing at the output node:

(3.13) ∆

For the implemented chip, the output stage is a source follower which limits the output voltage to 1.2 for 1.65 the maximum measurable capacitance difference in open-loop case is ∆ 12 . From (3.9), the output signal at low frequency can be found by:

∆ 2 2∆ (3.14) 2 12

As a result, the maximum differential capacitance that the closed-loop circuit can linearly measure is also limited by the swing at the output node:

(3.15) ∆ 2 2

Considering 1.2 for 1.65, the maximum measurable capacitance difference is ∆ 6 1.8. For the implemented design, maintaining a 60° phase shift requires that 3. Thereby, the maximum measurable capacitance is ∆ 38 13, indicating that the circuit can measure a that is larger than the initial value of the test capacitors, . This situation in particular can occur when the gap between the electrodes is significantly reduced during sensor operation. In most cases, however, is a fraction of .

Determining the minimum detectable capacitance requires analysis of the noise behavior of the sensing system. The output noise of the amplifier used in the trans- impedance amplifier is dominated by the thermal noise of the feedback resistor for a low noise amplifier [12]. The amplifier used in this TIA block was a predesigned cell from the AMS design kit. Based on the datasheet value and simulation data, it has 68 10 ⁄ output noise power, which is negligible compared to the output thermal noise of the feedback resistor at 16 10 ⁄ [11]. The thermal noise of the feedback resistor is added to the flicker and thermal noises of the filter. The input referred noise of the filter is:

4 (3.16)

where is the temperature, is the Boltzmann’s constant. The first term represents the thermal noise of the feedback resistor of TIA. The output noise of the filter is:

|| (3.17)

The second order OTA-C filter is made of four cascaded folded cascode operational trans-conductance amplifiers (OTA) as shown in Figure 3.23 [102]. Grounding of the capacitors improves the high frequency behavior. The first stage of the filter contributes the most noise to the circuit output [102]. Flicker and thermal noise of the folded cascode OTA are found from:

1 (3.18)

16 1 (3.19) 3

where is frequency while , and , are the flicker noise coefficients and mobility of charge carriers for the NMOSFETs and PMOSFETs, respectively.

Figure 3.23. Structure of the folded cascode operational trans-conductance amplifiers in low pass filter.

Using equations (3.5) and (3.6), the minimum detectable capacitance can be obtained in open-loop case which is:

∆ (3.20) 2

where is the total noise voltage at the output and represents the noise bandwidth.

According to (3.13), the dynamic range that we have in the original circuit, the one without feedback loop, can be obtained from:

(3.21)

According to (3.15), the dynamic range of the proposed design, the one with feedback loop, can be obtained:

1 (3.22) 2

As a result, according to these equations, (3.21) and (3.22), the dynamic range of sensing expands in closed-loop case while the amplitude of the reference signal is adjusted on the fly.

3.4. Simulation results

As previously stated, flicker and thermal noise of the filter as well as thermal noise of the feedback resistor mainly contribute to the overall output noise of the circuit. The input referred noise of the filter plotted in Figure 3.24 represents the sum of these noises. Both analytical calculations and numerical simulations (using Cadence) of noise behavior are compared.

−5 10

Input referred noise of the filter /Hz)

2 Output noise−Analytical model Output noise−Simulated by Cadence −10 10

−15 10 Noise power density (V

1 2 3 4 5 10 10 10 10 10 Frequency (Hz)

Figure 3.24. Comparison of analytical and simulation results for the noise performance of the circuit.

For a full bandwidth of 100, the total output noise () is 46 μ (for

3 1). According to equation (3.20), the minimum detectable capacitance is 0.15 . Since, the maximum detectable capacitance is 13 , the dynamic range is 98 . It is noteworthy that 100 is a rather wide bandwidth for most sensing applications. Reducing to a more sensible value of 1 lowers the output noise to 9 μ and as a result lowers the minimum detectable capacitance () to 30 and improves the dynamic range to 112 dB.

To sense higher capacitance, the off-chip timing capacitors () can be adjusted.

If we set to 10 ( can be 30 ), the minimum detectable capacitances reach to 4.6 for a full bandwidth of 100. The maximum detectable capacitance can be also expanded to 400 . Thus, employing the closed-loop configuration, we can sense higher values of sensing capacitances. In other words, wider linear range of sensing in closed-loop configuration provides wider range of sensing compared to the open-loop one. For example, with a large test capacitance of 34, open-loop circuit becomes nonlinear for 10 percent of changes in sensing capacitance while in closed-loop one it has a linear response for 50 percent of changes. Figure 3.25compares the response of the circuit to different sensing capacitances (34 and 1) under open- and closed- loop conditions.

Figure 3.25. Simulated results show open- and closed-loop performance of the circuit with different sense capacitors.

Schematic views of the switch block and triangular-wave signal generator are shown in Figure 3.26 and Figure 3.27, respectively. The switching blocks is a transmission gate consisting of NMOS and PMOS transistors. The triangular-wave signals in both open and closed-loop cases when 34 and Δ 12 are illustrated in Figure 3.29 while the layout view of the circuit is employed for post- processing (Figure 3.28). When operated in closed-loop, the amplitude of the reference signal applied to the larger capacitance is lowered by the feedback loop which increases the dynamic range as explained in the next section.

Figure 3.26. Schematic view of the switch.

Figure 3.27. Schematic view of the triangular-wave reference signal generator with switch blocks.

Figure 3.28. Layout view of the proposed circuit.

s (V 0.2 V = 209mV V pk−pk tri− V 0.1 tri+

−0.1 V = 209mV pk−pk ΔC = 0pF −0.2

Simulated Reference signal 0.2 V V = 230mV V = 146mV tri+ pk−pk pk−pk V 0.1 tri−

−0.1 ΔC = 12pF −0.2 200 210 220 230 240 Time (μ s)

Figure 3.29. Simulated reference signals produced by the circuit in open-loop (top) and closed-loop configurations when .

3.5. Experimental results

A fabricated prototype (see Figure 3.30) was tested at room temperature in both closed- and open-loop topologies. It is noteworthy that all of these circuits were realized in a mature 0.35μ CMOS technologies from Austria-Micro-Systems (AMS) [103]. Although the Layout Versus Schematic (LVS) did not show any problems, the submitted layout had a misplaced via. The layout error (misplaced via) caused a disconnect along the signal path and a portion of the circuit on the fabricated chip could not be reached. As a result, the trans-impedance amplifier, demodulator, and low pass filter had to be realized off-chip so that the design idea could be verified using the remainder of the circuit blocks. However, on-chip blocks encompass the main contributions of this work; i.e., generation of reference signals and control of the reference signal amplitude in closed-loop. The experimental results reported here are obtained using this hybrid system.

Photograph of the off-chip circuitry is shown in Figure 3.31. The hybrid system in open-loop configuration with a capacitive humidity sensor was used to monitor the environmental humidity. In this experiment, one of sensing capacitors is a capacitive relative humidity (RH) sensor and the other capacitor is a fixed 22 ( and

in Figure 3.16). The humidity sensor which is shown in Figure 3.32 has a comb-shaped structure and its dielectric material consists of a polyimide material.

Figure 3.30. Photograph of the die fabricated in 0.35μm CMOS technology from Austriamicrosystems.

Figure 3.31. Photograph of the off-chip circuitry including the trans-impedance amplifier, demodulator, and the low-pass filter.

Figure 3.32. The comb-shaped humidity sensor.

Figure 3.33 demonstrates an example that shows how the difference between differential capacitances affects the amplitude of the triangular-wave reference signals. The variations in reference signal amplitudes due to a difference in sensing capacitors can be seen in this figure.

Figure 3.33. Measured reference signals generated by the fabricated chip in open-loop and closed-loop configurations.

Figure 3.34 shows how the alteration in differential sensing capacitors resulted by variations in humidity changes the DC voltage at the output of the filter. Defining the percentage of nonlinearity as [104]:

max (3.23) ..

Where max is the maximum deviation from the fitted line in input capacitance and .. is the maximum full scale input. As shown in Figure 3.34, the maximum deviation of is 2 based on the least-squares fitted line. Thus, with

1 90

0.8 80

0.6 70

0.4 60 Relative humidity %

Normalized DC output voltage 0.2 Measured voltage versus diff. cap. 50 Linear fit of voltage versus diff.cap. Measured humidity versus diff. cap.

0 40 15 20 25 30 35 40 45 50 55 ΔC (pF)

Figure 3.34. Normalized output voltage versus the differential capacitance ( ) corresponding to different humilities as well as the linearized curve.

30 full scale input, nonlinearity becomes 7%. From simulations, minimum detectable capacitance () is 30 and the maximum detectable capacitance is 13 which gives us 112 dB dynamic range using (3.22).

Table 3-1.Circuit characteristics and comparison

Parameter This work * [85] [100] [105] Dynamic range (dB) 112 * 69** 84** 60** Eq. noise cap (aF) 30* 83* 61* 490** Technology (µm) 0.35 0.5 0.7 0.35 Supply ±1.65 3.3 5 3.3 Clock (kHz) 175 1000 5000 1000 Power (mW) 7.9* 0.001** 7** 1.44** Area () 0.47* 0.078 2.66 0.048 *Post-layout simulation results **Measured results

Table 3-1 compares the performance of the proposed topology against other interface circuits for capacitive sensors in literature. A charge amplifier with capacitive feedback is used in one of these designs [85]. This circuit was fabricated in 0.5μ double-poly CMOS process. It works based on single capacitive sensing rather than

differential sensing which makes it sensitive to interferences. The output voltage is prone to being saturated to the supply rails and become unstable without the shielding metal box. To stabilize the DC output voltage in this design, the charge adaptation circuit was used. The power consumption (1μ) provided in this table is just the power consumption of the charge amplifier’s. The power consumption in the charge adaptation circuit required for output stabilization will be in the range of milliwatts.

A switched-capacitor C2D converter working based on the use of a relaxation oscillator was designed by another research group in 0.7μ CMOS technology [100]. In this work, a negative-feedback circuit controls the charge-transfer speed to prevent the overload of the input amplifier for large sensing capacitances which thus results better noise performance and enables a wide dynamic range of capacitor values. Since there is a serious limitation for the value of a parasitic capacitance to function properly, additional blocks are required to extend the minimum parasitic capacitance. Despite the relatively high dynamic range which is 84, the power consumption is in the order of milliwatts.

In [105] a switch-based C2D converter working based on sigma-delta modulation was used. It was fabricated in 0.35μ CMOS technology. In order to automatically set the offset to zero, additional blocks including charge-mode digital-to- analog converter and successive approximation register unit were added to this interface circuit. These blocks add more power consumption while automatically calibrate the zero point. Although the dynamic range of this circuit is about 80 , the maximum measurable capacitance in this design is limited to 0.5.

Readout circuits designed in [105] and [85] do not have the ability to adjust their sensing range especially for large sensing capacitances. The high dynamic range of the circuit proposed in this chapter was obtained at the expense of more power consumption compared to the other circuits[100], [85], [105]. We will investigate low power circuits that occupy small chip area in the following chapters.

4. Low power differential capacitance sensing

Capacitive sensing is widely used in battery powered or wireless systems where low-power design is essential [106]. In some sensing systems, arrays of electrodes are required [107]. Thus, a large number of electronic channels need to be integrated on a single chip to read the output of each element of the sensor array. Therefore, developing a low-power front-end circuit is desired to accommodate increasing number of channels with a reasonable size, power, and dissipated heat [108].

Simplicity and low number of components are two main factors in lowering the power consumption. Since no DC current passes through the capacitors, switch- capacitor amplifiers and charge-transferring techniques are commonly used in low- power designs [109], [85], [110]. For instance, the power consumption of these circuits is expected to be significantly smaller than synchronous demodulation based readout designs discussed earlier [111].

To improve the noise performance in switch-capacitor amplifier, some techniques such as correlated double sampling and chopper stabilization are used along with the amplifier [94], [112]. The correlated double sampling circuits are used to remove noise by extracting signals from subtracting the foreground and background measurements and reduce the effect of parasitic capacitance. The chopper stabilization circuit modulates the input signal to high frequency and avoids the significant 1/ noise. Since power is mainly consumed in amplifier block and additional blocks needed for noise reduction, attention should be paid in designing low-power amplifiers is such readout circuits.

When comparing the power consumption of different capacitive-sensor interfaces, it is important to take into account that power consumption can typically be traded for other performance metrics such as noise, accuracy, and speed. Different applications may require different levels of performance. For example, in many of portable sensing systems low power consumption is essential weighed more heavily.

Hence, having low power consumption and relatively good resolution and accuracy are our main goals in the proposed design discussed in the following.

In this chapter, a simple switch-based readout circuit with lower power consumption for capacitive sensing is presented. This topology is based on using MOSFETS as switches for charge transfer. Converting changes in sensing capacitance with MOS switches to a voltage signal makes this design suitable for mobile applications. In this work, instead of using an amplifier to convert charges to the voltages, sample and hold capacitors are employed. In fact, this simple interface circuit not only can save energy, but it also offer advantages, such as small silicon area and design time over the more complex circuits.

4.1. Circuit design

As highlighted in the previous part, reducing the power consumption is one of the critical aspects in designing the readout circuits for many applications. The circuit described here converts the differential capacitance to the voltage signal. Its adjustable sensing range makes it suitable for various applications. Detailed specifications of the proposed circuit structure are discussed in the following.

The overall sensing system architecture is illustrated in Figure 4.1 comprising the capacitance-to-voltage converter, output buffer, biasing unit, clock generator. The proposed topology is illustrated in Figure 4.2, where and represent the two sensing

Figure 4.1. Differential capacitive sensing.

capacitors. The main function of the circuit is getting samples from the charge modification on and and transferring it to the output capacitance (). The timing diagram of the clock signals having period of with the output voltage trend are shown in Figure 4.2.

The operation of the circuit is as follows. Two signals ( and ) generated by

and switches are applied to the two sensing terminals. Before the sampling phase, switch , grounds in order to avoid voltage drop or jump at the common node.

Figure 4.2. Schematic view of the main block on top, switching signals on the bottom.

When is high, charge is injected into the common terminal () putting on one of the sensing terminals () and on the other one () while , , and are open. This charge is transferred to the sampling capacitance () via switch in sampling phase and will be stored on when closes. If is equal to , the total transferred charge to will be:

(4.1)

Before starting the next cycle, signal discharges capacitance () to prevent voltage saturation at . The difference between the sensing capacitance (, ) generates this charge ( which modifies as well as charge redistribution between and at every step of sampling.

can be expressed by:

(4.2)

1 (4.3) where is the current step number, 1 represents previous step number controlled by clock.

The output voltage of the C-V converter () approaches to its final value gradually after several sampling steps. Thus, simplifying equation (4.3), we have:

1 (4.4)

Figure 4.3. Output buffer circuitry.

As a result, the output voltage of the C-V converter can be found from:

(4.5)

Typically is much smaller than and the output voltage becomes:

(4.6)

According to the equation (4.6), the measurement range is adjustable depending on the sum of the sensing capacitances. A unity gain output buffer as shown in Figure 4.3 is utilized to probe the output voltage.

Figure 4.4. The diagram of the oscillator used for switching signal generation.

Clock signal is generated on chip to control the switches in charge and discharge phases. The schematic diagram of the oscillator is presented in Figure 4.4 [113], [114].

Depending on the output of the Schmitt-trigger, transistor may be on so that the capacitor (Cap) is discharged or it might be off which results in charging the capacitor. Clock frequency is found from:

(4.7) 2

where and are high and low transition voltage of the Schmitt-trigger, respectively. The current, , is the biasing current flowing through the capacitor (Cap).

In order to generate the non-overlapping controlling signals for the switches, delay units are employed. These delay units are shown as D-unit blocks inside the clock generator unit (see Figure 4.5). The schematic diagram of the implemented delay unit is presented in Figure 4.6. It is composed of two inverters and timing capacitors. The timing capacitors are being charged and discharged depending on the input signal.

Charging and discharging currents and ) are controlled by and .

The delay time (), the time from rising (falling) edge of the input voltage to the rising (falling) edge of the output voltage, is determined by charging and discharging times of the capacitors.

Figure 4.5. Digital blocks used for generating the controlling signals.

To have the same delay time for both rising and falling input signals of the delay unit (), should be constant and equal to . Moreover, less charge/discharge current and smaller timing capacitors promisingly improve power consumption and silicon area compared to the other available delay circuits.

Figure 4.6. The schematic of the delay unit.

The delay time is a function of and timing capacitors when equals :

4 2 (4.8)

Circuit’s response under nonideal conditions

The error sources involved in the proposed circuit’s response are mainly due to channel charge injection and clock feedthrough, the common-node capacitance ( in Figure 4.2, the offset voltages of the output buffer, and the leakage current of the switches. In this section, these error sources will be studied.

The problem of charge injection is reduced through using complementary NMOS/PMOS switches. Dummy switches, driven by inverse of the clock signal can be used to lower the effect of charge injection [86]. In each cycle of sampling, switch turns off and introduces an error in the output voltage and results a constant offset. This charge transfers to the output node through gate-drain capacitance of the transistors in switch . Also, clock feedthrough from , , while turning off changes the charge accumulated on and as a result changes the output voltage. Using large sampling capacitances reduces the error resulted by the clock feedthrough [86]. If the charge transfer can be represented by , the output voltage can be found from:

(4.9)

If the capacitance ( at the common electrode of the sensing capacitance ( is not negligible compared to the sum of the sensing capacitors, it affects the charge sharing amount and results in nonlinearity.

(4.10)

The offset voltage of the output buffer affects the accuracy of the circuit. If the offset voltage of the buffer be ,, the output voltage is given by:

, (4.11)

Charge loss can also be affected by the leakage current of the switches. For example current leakage () of switch results voltage change (∆) at that is given by:

∆ (4.12)

The minimum detectable differential capacitance can be determined by the noise of the circuit. Assuming and , output voltage referred noise is:

2 (4.13) 2

The minimum differential capacitance (equivalent noise capacitance: can be obtained by:

(4.14) 2

Thus, this circuit has an adjustable minimum capacitance that is proportional to sum of the initial capacitance ( 2) and . It is also sensitive to the common- node capacitance (.

4.2. Simulation result

The proposed circuit has been designed and fabricated in 0.35 μ CMOS technology (CMOSP35 AMS). The layout view is shown in Figure 4.7. The switching frequency is 200 . The simulated gain-bandwidth product, DC current and the offset voltage of the op-amp used for output buffering are 3.5 , 10 μ and 1, respectively. Noise analysis illustrated in Figure 4.8 shows that the total output noise is

250 μ for a full bandwidth of 10. The circuit requires 40 of power from 1.65 supply voltages. More than 95 percent of the power consumption is for biasing and output buffer cells.

Figure 4.7. Layout view of the proposed circuit.

−4 10 Hz) √

−5 10 Simulated noise density (V/ −6 10 0 1 2 3 4 10 10 10 10 10 Frequency (Hz)

Figure 4.8. Noise simulation results of the proposed circuit.

Schematic view of the switch used in simulated C-V converter is shown in Figure 4.9. Schematic view of the buffer connected to C-V converter is also shown in Figure

4.10. Simulation results showed that the output voltage is decreasing step-by-step at each clock cycle while we have 1 and 3 sensing capacitors instead of and , respectively. Output voltage reaches its final value after almost 80 times of the clock cycle. In order to show how clock feedthrough can affect response of the circuit while switches are closed by controlling signals, the voltage at the output capacitance () and clock signal are illustrated in Figure 4.11 and Figure 4.12, respectively. The voltage at the output capacitance () reaches the voltage at the sampling capacitance () after rising edge of clock ( (Figure 4.12). At the falling edge of this clock, the output voltage drops as a result of the feedthrough. This phenomenon can affect the accuracy of the measurement.

Figure 4.9. Schematic view of the transistors inside the switch in C-V converter.

Figure 4.10. Schematic view of the buffer

0.05 −0.2

0 −0.21 −0.05 −0.22 clock (φ ) feedthrough effect 4 −0.1 (mV)

(mV) −0.23 out −0.15 out V V −0.24 −0.2

−0.25 −0.25

−0.3 −0.26 0 10 20 30 40 30 32 34 36 38 40 Time (μs) Time (μs)

Figure 4.11. Simulation waveforms showing the effect of clock feedthrough, output voltage which is decreasing step by step and its close-up view.

2 2

1.5 1.5

1 1

0.5 0.5 (V) 0 (V) 0 4a 4a φ φ −0.5 −0.5

−1 −1

−1.5 −1.5

−2 −2 0 10 20 30 40 30 32 34 36 38 40 Time (μs) Time (μs)

Figure 4.12. Simulation waveforms of the clock ( and its close-up.

The circuit response is shown in Figure 4.13. It shows that parasitic capacitance at the common electrode decreases the sensitivity. For higher ratio of difference to sum of the sensing capacitance , output voltage after buffer is limited by its maximum value which is given by:

, (4.15)

where shows the source to drain saturation voltage of transistor and shows the gate to source voltage of transistor. The minimum value of the output voltage is limited by the drain to source voltage of transistor.

The common node capacitance increases the sensing range. Figure 4.13 illustrates the case when 1 common node capacitance is added. In this simulations,

is 100 , and sum of the sensing capacitances is 2 which is much larger than . Therefore, the output voltage has a linear relationship to the difference to sum ratio of the sensing capacitance (see equation (4.3)). As seen in Figure 4.13, output voltage reaches 1150 for difference to sum ratio of 0.7 which is in a good agreement with equation (4.3).

As seen in equation (4.10), common-node capacitance ( ) can be used to adjust the sensing range of the circuit. However, this can also be a disadvantage as parasitic capacitances can act as unknown values.

1000

V , Simulated C2V V , Analytic 500 C2V V , Simulated out

Voltage (mV) without C CN −500

−1000

−0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (C −C )/(C +C ) 1 2 1 2

1000

V , Simulated C2V V Simulated 500 out, V , Analytic C2V

with C = 1pF CN Voltage (mV) −500

−1000

−0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (C −C )/(C +C ) 1 2 1 2

Figure 4.13. Simulation results of the proposed circuit including output voltage after and before buffering in two different cases: without common-node capacitance on top and with common-node capacitance on the bottom.

4.3. Experimental Results

The fabricated chip is shown in Figure 4.14. The area occupied by the circuit is 200 μ 330 μ excluding I/O cells (ESD protection and pads). To avoid possible timing problems and glitches, special attention needs to be paid to maintain the symmetry of the clocking block and match parasitic capacitance in drawing the layout [86]. The close-up view of the capacitors which are used in clock generator is shown in Figure 4.15.

Figure 4.14. Optical photograph of the fabricated chip.

Figure 4.15. Common-centroid symmetrical structure for building the capacitance in clock generator.

Figure 4.16. Circuit’s response to sensing capacitors’ variations.

Figure 4.16 demonstrates how the proposed circuit responds to the hand movement when the circuit is connected to the touchless interface in section 3.1. This figure also shows how the output signal changes while 1 , 1.5 , 2 are added instead of and .

In addition to the coplanar hand motion sensor, a displacement sensor shown in Figure 4.17 is used to detect the movement of the top electrode. This sensor works based on the area variation of the electrodes in sensing two differential capacitances ( and ). According to the simulation results, these capacitors are 70 when the top electrode is located in the middle. Changing the top electrode’s position from the middle point to the left side varies from 70 to 146 and changes from 70 to 24 . Figure 4.18 shows changes in the differential capacitance over time when the top electrode was moved step by step. Experimental results are illustrated in Figure 4.18 as the output voltage was measured by the oscilloscope.

Figure 4.17. Simplified model of a displacement sensor with three electrodes.

4.3.1. Measurements based on a MEMS variable capacitor

A MEMS variable capacitor was used to analyze the circuit’s response for microsensor applications. This variable capacitor is made from a comb capacitor where one electrode can be pushed in using a thermal actuator [115]. A photograph of this device is shown in Figure 4.19. This comb capacitor consists of two interdigitated electrodes. Each electrode has 20 fingers. Each finger is 3 width and 20 long. The electrode’s thickness is 25 with finger engagement of 5, and gap of 2.5.

As shown in Figure 4.19, a thermally actuated chevron structure is connected to the comb-drive structure to move the inside electrode of the capacitance. Passing current through the chevron structure, heats it up leading to thermal expansion of the beams [116]. Its deformation causes a vertical displacement proportional to the rise in

150

100

50 (fF) 2 0 −C 1 C −50

−100

−150 0 5 10 15 20 25 30 35 40 45 50 Time (s)

200 180 160 140 120 100 (mV) 80 out

V 60 40 20 0 −20 0 5 10 15 20 25 30 35 40 45 50 Time (s)

Figure 4.18. Capacitance variations versus time on top, output voltage on the bottom based on measurement.

temperature generated by the applied voltage [117]. It is given by:

(4.16) ∆ 3 where is the voltage applied to the beam, L is the chevron’s arm length, n is the number of chevron beams, is the angel between arm and horizon, is the thermal expansion coefficient, is the resistivity and is the thermal conductivity of the beam. In experiments, two similar devices were used as and . acts as a reference capacitance.

Figure 4.19. A microscope photo of the MEMS variable capacitor including the thermal actuator and a close-up view of the comb structure.

When chevron beam moves, the electrode of the comb-drive capacitance () connected to the chevron structure moves towards the other electrode and the capacitance between them increases. As discussed in section 2.2, the total capacitance consists of surface capacitance () and fringing capacitance (). The total capacitance is related to the amount of displacement that is given by:

2 ∆ (4.17)

where is the initial finger engagement and ∆ is the change in finger engagement of the comb-drive beam with thickness , gap between fingers and n is the number of fingers. Finite element simulation result shows that the total capacitance () with width of 3, length of 20, finger engagement of 5 and gap of 2.5 is 41 (see Figure 4.20).

45 (fF) total

C 44

41 5 5.2 5.4 5.6 5.8 6 6.2 6.4 6.6 y +Δy (μm) 0

Figure 4.20. Total capacitance of the comb-shaped structure versus finger engagements.

(fF) 20 surf C

16 5 5.2 5.4 5.6 5.8 6 6.2 6.4 6.6 y +Δy (μm) 0

Figure 4.21. Theoretical values of the surface capacitance with comb-shaped structure versus finger engagements

Theoretical values of surface capacitance (without considering the fringing field) in Figure 4.21 and comparing it with the total capacitance in Figure 4.20 show that the contribution of fringing field cannot be negligible. Thus, the values of the capacitance between two comb-shape beams are calculated through finite element simulation in ANSYS. Figure 4.22 shows how the capacitance changes with respect to the displacement.

5 C (fF)

Δ 4

Simulated 2

0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Δ y (μm)

Figure 4.22. Changes in capacitance of the comb-shaped structure versus displacement based the simulation results.

Changes in differential capacitance versus time are shown in Figure 4.24. Figure 4.24 demonstrates how the output voltage changes when the engagement of fingers in sensing capacitance increases. In this figure, experimental and simulated results are compared.

5 ) (fF) 1 4 −C 2

(C 3

0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Time (s)

Figure 4.23. Changes capacitance values versus time.

20 Output voltage−experimental results Output voltage−simulation results 10

−10 Output voltage (mV)

−20

−30 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Time (s)

Figure 4.24. Changes in output voltage when the distance between two electrodes becomes smaller over time, based on experimental data and simulation results (dotted points).

4.3.2. Readout circuit’s performance analysis

Noise density captured by a signal analyzer is illustrated in Figure 4.25. For a full bandwidth of 10, the total output noise () is 370 μ. Depending on the initial, common-node, and sampling capacitance values, different minimum capacitance can be measured. Some cases are studied in Table 4-1. For example for 170 sum of the initial capacitances ( ) and 700 common-node capacitance, it will be 110 .

Table 4-1. Minimum measurable capacitance

100 Without common-node capacitance ( 0)

Sum of initial capacitance, , (fF) 80 1000 10000

Minimum Cap., , 2⁄ (aF) 20 120 1100

100 With common-node capacitance ( 700 )

Sum of initial capacitance, , (fF) 80 1000 10000

Minimum Cap., , 2⁄ (aF) 100 200 1200

−3 10 Hz)

√ −4 10

−5 10

−6 10 Measured noise density (V/ −7 10 0 1 2 3 4 10 10 10 10 10 Frequency (Hz)

Figure 4.25. Noise density the circuit measured by signal analyzer.

As discussed earlier in this chapter, the circuit response in term of linearity is directly related to the common-node and sum of the differential capacitance value. If sum of the sensing capacitance changes during the measurement, the term contributes to the nonlinearity error that can be seen in:

∆ 1 (4.18) 1

where is the sum of the differential capacitances (∆ ) and is the source of nonlinearity. If ≪ , we have:

∆ 1 (4.19)

Output voltage versus ratio of the MEMS sensing capacitance ( ) and the best fitted line are plotted in Figure 4.26. As can be seen in this figure, the maximum deviation of is 0.002 based on the least-squares fitted line. According to equation (3.23), with 0.07 of full scale ratiometric input, nonlinearity becomes 3%.

−5

−10

−15

−20 Measured output voltage (mV)

−25 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 (C −C )/(C +C ) 1 2 1 2

Figure 4.26. Measured output voltage versus the ratiometric change in sensing capacitance.

Table 4-2. Interface circuit characteristics and comparison.

Parameter This work Sync. Demo. ** [94]** [100] [105] [107] [109]

Power (μ) 720 7900 3780 7000 1400 102 2500

Eq. Noise Cap. 100 30 228 61 490 122 N/A (aF)

Area () 0.066 0.47 N/A 2.66 0.048 0.403 0.3

Clock (kHz) 200 175 4000 N/A 1000 100 2000

Technology 0.35 0.35 0.35 0.7 0.35 0.18 0.18 (µm)

Supply ±1.65 ±1.65 3.3 5 3.3 1.2-3.6 3.3

**Results are based on simulation.

Performance of the circuit is compared against other similar works in

Table 4-2. In [94], a correlated double sampling demodulator technique is employed to reduce the non-linearity and AC distortion. In this work, the simulation results showed that the sensing circuit can achieve low power consumption of 3.78 with a sampling frequency of 4. As mentioned in previous chapter, the designed circuits in [100] and [105] were C2D converters. These readout circuits consume power in the range of miliwatt because of having some additional blocks required to be insensitive to parasitics and be automatically calibrated.

A low-power capacitance-to-digital converter was designed in [107]. It was fabricated in 0.18μ CMOS technology. It consists of a 16-channel multiplexer, a C2V converter and a C2PW converter providing a digital output. The C2V converter is a switch-capacitor amplifier and C2PW is a switch-capacitor structure having a feedback loop. Although, the switch-based structure leads low power consumption, its accuracy and resolution highly depend on the matching of the capacitors. Beside its low power consumption, it has a relatively high update rate compared to the other C2D converters [100].

The readout circuit design in [109] works based on charge transfer principle. Connecting the middle electrode to a TIA makes the common node of the differential capacitance virtually grounded, thus it becomes insensitive to stray capacitors. Since the DC output voltage is greatly affected by 1⁄ noise and offsets of the op-amp, additional blocks were used to modulate the input signal to high frequency and demodulate it after amplification. Also, low-pass filter was used to eliminate the noise. This circuit was fabricated in 0.18μ CMOS technology The power consumption of this circuit is 2.5 which is much more than the power consumption in the proposed deign in this chapter.

As shown in this table, the circuit proposed in this chapter consumes much less power compared to the proposed circuit in Chapter 3 and also compared to the two other circuits fabricated in the same CMOS technology [94], [105]. Because of the ratiometric sensing feature, the minimum measurable capacitance in this design is adjustable and can change depending on the sum of two sensing capacitance.

5. Linear, low power, capacitive sensing circuit with insensitivity to parasitics

A common node capacitor, e.g. parasitic, caused nonlinear response in the response of the circuit discussed in Chapter 4. This chapter discusses an interface implementation for capacitance-to-time conversion to eliminate the effect of the parasitic capacitances at the common node. In this method, the output signal can be easily digitized using a digital counter. While maintaining the ability to handle parasitic capacitors up to five times larger than the sensor capacitance, the proposed interface consumes less power compared to the reported one in previous chapter.

In this chapter, the operating principles of this circuit are explained and more details about elimination of the parasitic effects are addressed. Circuit behaviour is analyzed along with the simulation and measurement results.

5.1. Circuit topology

The proposed circuit consists of two switched-based capacitance-to-voltage converters as well as a voltage-to-pulse-width converter as shown in Figure 5.1. One of the capacitance-to-voltage converters provides a voltage proportional to the difference between sensing capacitors and the other one produces a voltage proportional to the sum of the sensing capacitors . In order to eliminate the parasitic effects, a voltage divider is used to divide the output voltage of these capacitance-to-voltage converters, and therefore cancels the term ⁄ avoiding the nonlinearity error. The divider is show in Figure 5.1 by a voltage-to-pulse-width converter block that produces a pulse-width value corresponding to the differential capacitance that is proportional to the ratio of output voltage of capacitance-to-voltage converters. These capacitance-to-voltage converters two blocks are selected using six switches controlled by two non-overlapping clock signals to read the capacitors consecutively (see Figure

5.1). Since the clock rate is much more than sensing capacitance changing rate, during the measurement time sensing capacitance does not change.

More details about the capacitive-to-voltage-converter circuits are illustrated in Figure 5.2. The first circuit is the same as the switched-based circuit discussed in

Chapter 4, and the second has the same configuration but instead of , both and

are connected to through switches (. Considering the common-node capacitance, is given by:

1 (5.1) 1

where and are the sensing capacitances, represents the parasitic capacitance,

is the sampling capacitance, and is the output capacitance.

Figure 5.1. The main building block of the proposed circuit.

Figure 5.2. Simplified schematic view of the two capacitance-to-voltage converters used for cancelling the parasitic effects.

and is:

1 (5.2) 1

Dividing these two voltages provides a value independent of the unknown (parasitic) capacitance at the common node:

(5.3)

The proposed structure of the voltage-to-pulse-width converter is simplified in

Figure 5.3. In this configuration, at first, is converted to a current. If we use this current to charge or discharge a capacitor (), the slope of the voltage across the capacitor that is the derivative of the voltage () with respect to time, is:

(5.4)

where is the gain of V-I converter and the voltage drop on the capacitance () is shown by . Thus, this slope is proportional to the output voltage (∝ ).

Figure 5.3. Simplified schematic view of the voltage divider.

According to equation (5.4), the time required to have ∆ change in voltage drop across the charge or discharge capacitance () is:

∆ ∆ (5.5)

Thus, the required time to have a voltage drop that equals the output voltage is:

∆ (5.6)

In order to capture this time, a comparator is used to compare the voltage drop

∆ with the output voltage ∝ . In other words, the difference between the output voltage and ground level voltage substitutes the change in drop voltage ∆. Since the output voltage can be positive or negative depending on the sign of , two parallel circuits are used as shown in Figure 5.4. For negative values of , discharging capacitance () is used while for positive values of the charging capacitance () is employed.

When is negative and switch is closed, the output current of V-I converter flows through the capacitor () and negative slope sawtooth-wave signal is generated. The sawtooth-wave signal () is compared with negative by a comparator and the pulse-width-modulated signal ( appears at the output. On the other cycle when switches is closed and is positive, the output current of V-I converter flows through the capacitor () and positive slope sawtooth-wave signal is generated. Eventually, after comparing this ramp () with , a pulse-width signal will be generated. Therefore, appearing a pulse at shows that we have positive value of which means is greater than , while having pulse at shows that we have negative value of which means is greater than .

Figure 5.4. Simplified schematic view of the circuits for converting voltage division to a pulse-width using both falling and rising ramp signal.

To guarantee that the pulse-width signal only appears when the voltage drop () across capacitor () is rising, and the pulse-width signal appears when the voltage drop () across capacitor () is falling, two AND-gates are employed after the comparator as displayed in Figure 5.4. One of the AND-gates is connected to the clock signal synchronized with closing time of switch , while the other one is connected to the inverted clock synchronized with closing time of switch . Also, to insure that the ramps and pass the ground level, the reference voltages

(, ) should be above and below zero volt, respectively.

Assuming the charge and discharge capacitances are the equal, the output pulse width (), the time that takes for the ramp starting from the ground level to reach , is:

(5.7)

where is a coefficient that equals to ⁄. As shown in equation (5.7), this method has also an adjustable sensing range similar to the proposed switch-based circuit in previous chapter. According to this equation, capacitive sensing range expands when the capacitance value (, ) increases. Also, tuning the charge or discharge capacitor () allows more expansion in the sensing range. In addition, having higher

(⁄) results wider pulse width, and therefore more resolution can be obtained.

The comparator employed in pulse-width generator consists of an open-loop amplifier with current mirror load as shown in Figure 5.5. It is used for converting the falling ramp to the pulse width. In rising ramp when becomes greater than , output voltage of the comparator () comes down and gets limited by drain-source voltage of . Thus, NMOS input transistor is not suitable for rising ramp signals. Comparator with PMOS input transistors is used for detecting and comparing the rising ramp signal as shown in Figure 5.6.

Figure 5.5. Simplified schematic view of a comparator when is negative.

Figure 5.6. Simplified schematic view of a comparator when is positive.

As mentioned before the falling ramp signal (), starts from with positive value close to zero volt to make sure it passes the ground level. To measure the exact time between ground level and voltage of , another comparator is needed to compare ground and . Eventually the pulse will be generated by passing a AND gate as shown in Figure 5.7.

Figure 5.7. Simplified schematic view of the pulse width for falling ramp.

Figure 5.8. Simplified schematic view of the pulse width for rising ramp.

5.2. Simulation results

The proposed circuit was designed and fabricated in 0.35 μ CMOS technology (AMS 0.35 μ from austriamicrosystems). The layout of this circuit is shown in Figure 5.9. It is built on 330 600 area on silicon. Its switching frequency is 80 . The schematic view of switching unit which produces rising sawtooth signal () is shown in

Figure 5.10. The two transistors ( and ) are controlled by signal that is connected to the inverted clock represents the switches and . Comparator and pulse-width generator employed for the pulse-width signal are shown in Figure 5.10 and Figure 5.11.

Figure 5.9. Layout view of the proposed circuit.

Figure 5.10. Simplified view of switching unit on left and a comparator when is positive on right.

Figure 5.11. Simplified view of a pulse-width generator when is positive.

Behavior of the proposed circuit after post layout simulation is demonstrated in Figure 5.12 and Figure 5.13. As shown in these figures, pulse starts when ramp signal passes zero volt and it is high till its absolute value becomes greater than (||). The

capacitance in pulse-width modulator ( ) is 2 in this design. Setting to

100 and to 100 , the readout circuit produces 730 pulse-width for 5 differential capacitance. In this example, sum of the two capacitances is 10 and is 1.65 ( 1).

1.5 V pw− 1 V out1 V 0.5 c1

0 Voltage (V) −0.5

−1

−1.5

−2 979 980 981 982 983 984 985 986 987 988 989 990 Time (μs)

Figure 5.12. Simulation results of the proposed circuit’s response, when .and ..

1.5

0.5

0 V out1

Voltage (V) V −0.5 c2 V pw+ −1

−1.5

−2 976 977 978 979 980 981 982 983 984 985 986 987 Time (μs)

Figure 5.13. Simulation results of the proposed circuit’s response when .and ..

According to the post-layout simulation, this circuit along with all biasing, clock generating units consume 180 current from 1.65 supply voltage. The power consumption is therefore about 600. To analyze the behavior of the circuit when parasitic capacitance at the common node increases, two different cases are considered in Figure 5.14, one with 5 parasitic capacitance and the other one with 10 .

In Figure 5.14, the generated pulse widths are compared with each other. In this simulations, is 100 , and sum of the sensing capacitance is 10 and is the same as . In Figure 5.15, the generated output voltages () are compared with each other in two cases when we have 5 and 10 parasitic capacitances. The output signal varies in about %25. However, the maximum variations of the pulse widths when we put 5 and 10 parasitic capacitances is less than %5.

1600

1400 with 5pF parasitic capacitance 1200 with 10pF parasitic capacitance

1000

800

600 Pulse−width (ns)

400

200

0 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (C −C )/(C +C ) 1 2 1 2

Figure 5.14. Simulation results for pulse-width versus capacitance variations with parasitic capacitance and with parasitic capacitance.

800

600

400

200

(V) 0 out1 V −200 with 10pF parasitic capacitance with 5pF parasitic capacitance −400

−600

−800 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (C −C )/(C +C ) 1 2 1 2

Figure 5.15. Simulation results for output voltage () versus capacitance variations with parasitic capacitance and with parasitic capacitance.

Figure 5.16. Die photograph.

Figure 5.17. Difference between two sensing capacitance generates pulse at the output.

5.3. Experimental results

5.3.1. Testing with variable capacitors

The fabricated chip is shown in Figure 5.16. Employing two variable capacitors and changing their values generates different values of the pulse-width ( and ). As shown in Figure 5.17, increasing the differential sensing capacitance generates a pulse signal. In this experiment, 0.2 change in sensing capacitance while sum of the sensing capacitance is 10.7 results a 70 pulse-width. Figure 5.18 demonstrates the experimental results and shows how circuit response to the variations in sensing capacitance. In this experiment, one of the capacitance is fixed ( 5.5 ) and the other one () changes from 3.1 to 9.1 .

100

2 5.8 pF 6.2 pF 1 6.7pF

(V) 6.9 pF

pw+ 7.4 pF 0 7.9 pF 8.5 pF 9.1 pF

Measured V −1

−2 0 100 200 300 400 500 600 700 800 Time (ns)

4.7 pF 1 4.3 pF (V) 4 pF pw− 3.7 pF 0 3.1 pF

Measured V −1

−2 0 100 200 300 400 500 600 700 800 Time (ns)

Figure 5.18. Measured results for two variable capacitors, while one of the capacitors () is not changed and the other one () is changed as labeled on the graphs.

5.3.2. Characterization with a MEMS variable capacitor

To analyze the readout’s behavior in detecting the beam displacement in microsensors, the comb-drive capacitive microsensor introduced in previous chapter has been used. In order to have a differential sensor, one comb capacitive sensor is connected instead of and the other one is used instead of . In this experiment, the capacitance

acts as a reference capacitance. Since smaller leads larger pulse-width, to have better resolution in this experiment, is set to 0.2 8. As shown in Figure

5.19, increasing the ratio of ⁄ , increases the pulse-width signal. The

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measured output pulse-width signals for each of these capacitance variations are illustrated in Figure 5.19.

5.3.3. Readout circuit’s response with parasitic capacitance

In order to test the effect of parasitic capacitance on the output signal, the circuit`s response has been studied using different values of parasitic capacitance. According to these experiments, the output pulse-width varies a little. This variation is still smaller than the method discussed in previous chapter. As shown in Figure 5.20 and Figure 5.21, adding 5 parasitic capacitance to the common node of two variable capacitors (from 3.1 to 9.8 ) changes the pulse-width for only 5%.

2.4 s) μ 2.3 2.2 2.1 2 1.9 Measured pulse width ( 1.8 1.7 0.145 0.15 0.155 0.16 0.165 0.17 0.175 0.18 0.185 0.19 (C −C )/(C +C ) 1 2 1 2

1.5

(V) 0.5 PW+ 0

−0.5

Measured V −1

−1.5

−2 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 Time (μs)

Figure 5.19. Experimental results show the readout response and output pulse-width when displacement of microsensor generates different capacitances (=8).

102

1000 900 with 1pF parasitic capacitance 800 with 10pF parasitic capacitance 700 Fitted line 600 500 400 300 200

Measured output pulse width (ns) 100 0 −0.3 −0.25 −0.2 −0.15 −0.1 −0.05 0 (C −C )/(C +C ) 1 2 1 2

Figure 5.20. Effects of parasitic capacitance on (=1.65).

700

600 with 5pF parasitic capacitance 500 with 10pF parasitic capacitance Fitted line 400

300

200 Measured output pulse width (ns) 100 0.05 0.1 0.15 0.2 0.25 0.3 (C −C )/(C +C ) 1 2 1 2

Figure 5.21. Effects of parasitic capacitance on pulse-width ( ) testing two variable capacitance (=1.65).

The minimum pulse width that can be generated by the designed circuit is limited by rise time and fall time of the output signal. In measurement, the probe capacitance of the oscilloscope generates higher rise time and fall time compared to the simulations. According to the simulation results in Figure 5.12 and Figure 5.13, the rise and fall times of the generated pulse-width signal are less than 10. Also, the measurement results showed that there are some fluctuations in pulse-width value. These variations can also affect the minimum measurable pulse width. These variations have been measured by frequency counter; it shows 20 deviation in pulse width. Since the maximum rise/fall

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time is less than this deviation, we assume that the circuit is capable of measuring the pulse-width greater than 20. Thus, the minimum sensing capacitance can be found by:

(5.8)

Some different cases are shown in Table 5-1. For example, having 2 for and 1.3μ for , 100 for sum of the sensing capacitance and considering 1, the minimum differential capacitance will be 1. As can be seen in this table, higher results higher resolutions because of having wider output pulse width.

The circuit response in testing a MEMS microsensor and its fitted line are plotted in Figure 5.22. As can be seen in this figure, the maximum deviation of is 0.001 based on the least-squares fitted line. According to equation (3.23), with 0.036 of full scale ratiometric input, nonlinearity becomes 2%.

Table 5-1. Minimum measurable capacitance

1 and 1.65 1.65 and 0.2 ( 1.65) ( 8.25) Sum of initial capacitance, 100 1000 10000 100 1000 10000 , (fF)

Minimum Cap., (fF) 1.3 13 130 0.16 1.6 16

104

2.5

2.4 s)

μ 2.3

2.2

2.1

2 Measured 1.9 Fitted line Output pulse−width ( 1.8

1.7 0.145 0.15 0.155 0.16 0.165 0.17 0.175 0.18 0.185 0.19 (C −C )/(C +C ) 1 2 1 2

Figure 5.22. Readout’s behavior in measuring comb-drive capacitive microsensor.

Table 5-2. Interface circuit characteristics and comparison.

Parameter This work Switch-based Synch. Demo. [94]* [100] [109]

Power (μ) 720 600 7900 3780 7000 2500

Min. Measurable. 160 127 200* 228 61 N/A Cap. (aF)

Area () 0.198 0.066 0.47 N/A 2.66 0.3

Clock (kHz) 80 200 175 4000 N/A 2000

Technology (µm) 0.35 0.35 0.35 0.35 0.7 0.18

Supply ±1.65 ±1.65 ±1.65 3.3 5 3.3

*The results are based on simulations.

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Table 5-2 compares the performance of the proposed topology against two other interface circuits proposed in this research along with three other circuits designed for capacitive sensors in literature. As mentioned before, this work has less sensitivity to the parasitic capacitance at the expense of power consumption and using a bit more area of silicon compared to the switch-based circuit discussed in Chapter 4. Same as the switch-based circuit it has adjustable sensing range as well as minimum measurable capacitance.

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6. Conclusions and future work

Capacitive sensing systems are experiencing a strong market growth in areas such as consumer electronics, automotive industry, and biomedicine. Due to steady increase in the numbers and applications of microsensors and MEMS-based devices, developing high performance interface circuits is essential to convert the capacitance value to a proper electrical signal. Depending on the application, some factors in circuit design can be more important than the others. For example, having small size and low power dissipation are the key features of interface circuits aimed at mobile, battery- powered applications. In order to lower the design cost in production of sensing systems for various applications, it is desirable to design a number of common readout circuit topologies with different optimal performance metrics. This issue was the subject of the research presented in this work.

6.1. Summary of results

The objective of this research was to design the integrated capacitive sensor interfaces with emphasis on optimizing resolution, dynamic range, power consumption, and the required area of silicon. We looked at different circuit architectures used to address these features. The synchronous demodulation technique provides high resolution and is widely used. To increase the dynamic range of sensing of this circuit, we proposed a novel architecture based on synchronous demodulation technique where a feedback signal adjusted the reference signal amplitude on the fly. This circuit was fabricated in 0.35 CMOS technology. The circuit had an adjustable sensing dynamic range of up to 112 and was capable of measuring capacitance as small as 30 with a total power consumption of 8.

Low power consumption is one of the most important design criteria for portable sensing systems. To overcome the power constraints of the first technique, I proposed another interface topology. This circuit had a simple switch-based structure and

107

operated based on charging and discharging of known capacitors. It was fabricated in 0.35 CMOS technology and had a low power consumption of 600. Moreover, its ratiometric sensing feature provided an adjustable sensing range which could be tuned for different applications. This circuit can detect capacitances changes as small as 200 in 1. This circuit however was sensitive to the parasitic capacitances.

To eliminate the effect of parasitics on the circuit performance and improve the linearity, the design of the second circuit was improved. By using an additional block and an analog divider, the sensitivity of the circuit to parasitics was significantly reduced. The fabricated circuit consumed a total power of only 720 and was fabricated in 0.35 CMOS technology. This circuit can detect capacitances changes as small as 160 in 100. Another advantage of this circuit over the previous designs is that the pulse- width output signal of this circuit can be more easily digitized.

6.2. Future works

The future work would be moving on to characterizations of the oscillator unit employed in the designed circuits. All of the circuits developed in this work will benefit from having a low- phase noise/jitter oscillator on the chip. Studying the effects of oscillator phase noise on the overall noise performance of the circuit will provide valuable insight into design optimization and improvements. Design of low-phase noise on-chip oscillators that meet the power consumption requirements will be a contribution that is of interest to many microsystem designers. A potential solution can be integration of MEMS resonators with CMOS electronics.

Further research is needed to study the contribution of the oscillator block and the controlling signal generator on the response time of the circuits. Methods to improve the speed of the proposed circuit and decreasing the rise/fall time should also be studied.

Proposing solutions to eliminate the effect of non-idealities such as charge loss due to leakage, charge injection, and clock feed-through of MOSFET switches employed in low-power switch-based designed circuit may also be considered as a future work.

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Sensing systems often operate during short random intervals. A useful addition of a sleep mode can reduce the power dissipation of the integrated circuit further. The wake-up signal may be generated automatically through, for instance, a sudden charge at the input.

Optimizing the silicon layout may also be considered as a future work. It should be also considered that shrinking the interconnecting wires and the space between them may cause cross-talk effect and degrades its performance. Integration of the proposed interface circuits and capacitive sensors on the same chip can be followed in the future to reduce the parasitic capacitance effects. It also enhances noise and linearity, thereby improving the performance of the sensory system as a whole.

6.3. Publications

The presented research has resulted in the following publications. Analysis of the synchronous demodulation technique which was employed for detecting hand motion and the results were appeared in these papers:

 Fatemeh Aezinia, YiFan Wang, and Behraad Bahreyni, “Touchless Capacitive Sensor for Hand Gesture Detection,” Proceeding of the 2011 IEEE Sensors Conference, pp.546-549, 28-31 Oct. 2011

 Fatemeh Aezinia, YiFan Wang, and Behraad Bahreyni, “Three Dimensional Touchless Tracking of Objects using Integrated Capacitive Sensors”, IEEE Transactions on Consumer Electronics, vol.58, no.3, pp.886-890, August 2012.

 Fatemeh Aezinia, Mark Alexiuk, Behraad Bahreyni, Mehran Fallah-Rad, Labros Petropoulos, “A Capacitive Proximity Sensor for Enhanced Clinical Workflow with Intra-operative MRI”, 4th Annual iOIS Meeting - Gateway to the Surgery of the Future, 2013.

The proposed circuit with feedback loop working based on synchronous demodulation technique resulted in these papers:

 Fatemeh Aezinia, and Behraad Bahreyni, “A Sensitive Interface Circuit with Wide Dynamic Range for Capacitive Sensors,” Proceeding of the 2012 IEEE Sensors Conference, pp.1-4, 28-31 Oct. 2012.

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 Fatemeh Aezinia and Behraad Bahreyni, “A Readout Circuit with Wide Dynamic Range for Differential Capacitive Sensing Applications,” 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), pp.1-4, 5-8 May 2013

 Fatemeh Aezinia and Behraad Bahreyni, “An Interface Circuit with Wide Dynamic Range for Differential Capacitive Sensing Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol.60, no.11, pp.766-770, Nov. 2013.

Study and analysis on switch-based charge transferring circuit as well as simulations and experimental results were published in these papers:

 Fatemeh Aezinia and Behraad Bahreyni, “A Low Power CMOS Integrated Circuit for Differential Capacitive Measurement,” IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), pp.189-192, 4-7 Aug. 2013.

 Fatemeh Aezinia and Behraad Bahreyni, “A Low-power, Low-cost Switched- capacitor Circuit for Differential Capacitive Microsensors,” 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), pp.1-4, 5-8 May 2013.

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