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Intel® Communications Chipset 8925 to 8955 Series Software Programmer's Guide

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Intel® Communications Chipset 8925 to 8955 Series Software Programmer's Guide Intel® Communications Chipset 8925 to 8955 Series Software Programmer's Guide March 2016 Order No.: 330751-005 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or visit http:// www.intel.com/design/literature.htm. Any software source code reprinted in this document is furnished for informational purposes only and may only be used or copied and no license, express or implied, by estoppel or otherwise, to any of the reprinted source code is granted by this document. Basis, Basis Peak, BlueMoon, BunnyPeople, Celeron, Centrino, Cilk, Curie, Flexpipe, Intel, the Intel logo, the Intel Anti-Theft technology logo, Intel AppUp, the Intel AppUp logo, Intel Atom, Intel CoFluent, Intel Core, Intel Inside, the Intel Inside logo, Intel Insider, Intel RealSense, Intel SingleDriver, Intel SpeedStep, Intel vPro, Intel Xeon Phi, Intel XScale, InTru, the InTru logo, the InTru Inside logo, InTru soundmark, Iris, Itanium, Kno, Look Inside., the Look Inside. logo, Mashery, MCS, MMX, Pentium, picoArray, Picochip, picoXcell, Puma, Quark, SMARTi, smartSignaling, Sound Mark, Stay With It, the Engineering Stay With It logo, The Creators Project, The Journey Inside, Thunderbolt, the Thunderbolt logo, Transcede, Ultrabook, VTune, Xeon, X-GOLD, XMM, X-PMU and XPOSYS are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2013–2015, Intel Corporation. All rights reserved. Intel® Communications Chipset 8925 to 8955 Series Software Programmer's Guide March 2016 2 Order No.: 330751-005 Revision History—Intel® Communications Chipset 8925 to 8955 Series Software Revision History Date Revision Description March 2016 006 Updates include: • Updated Epolled Mode on page 22 • Updated Stateful Compression Level Details on page 54 and Stateless Compression Level Details on page 54 • Added DRBG_POLL_AND_WAIT optional build flag to Build Flag Summary on page 56 September 005 Updates include: 2015 • Updated Response Processing on page 20, Interrupt Mode on page 20, User Space Interrupt Mode on page 39, and Build Flag Summary on page 56 • Added Running Applications as Non-Root User on page 60 • Updated Intel® QuickAssist Technology API Limitations on page 95 • Added Epolled Mode on page 22, Epoll Sample Code on page 83 and Event-Based Polling (Epoll) APIs on page 136 • Updated Service Instances and Interaction with the Hardware on page 142 • Updated Cryptographic Logical Instance Parameters on page 154 and Data Compression Logical Instance Parameters on page 155 February 004 Updates include: 2015 • Added Intel® QuickAssist Technology Entries in the /proc Filesystem on page 41 • Added How to Call the Heartbeat Query on page 46 and What the Heartbeat Query Does on page 47 • Updated Build Flag Summary on page 56 • Added Acceleration Driver Return Codes on page 62 • Updated Dynamic Instance Configuration Example on page 72 and Resubmitting After Getting an Overflow Error on page 98 November 003 Updates include: 2014 • Changed "ICP_AUTO_DEVICE_RESET" optional build flag names; see Build Flag Summary on page 56 • Updated Intel® QuickAssist Technology API Limitations on page 95 • Added Resubmitting After Getting an Overflow Error on page 98 • Added two new APIs at the bottom of Dynamic Instance Allocation Functions on page 104 September 002 Updates include: 2014 • Added Intel® QuickAssist Technology Compression API Errors on page 53 • Added new APIs to Dynamic Instance Allocation Functions on page 104 • Updated PfVfComms Feature Functions on page 131 • Updated Reset Device Function on page 134 • Added Thread-less APIs on page 135 • Other general updates. July 2014 001 Updates include: • First “public” version of the document. Based on “Intel Confidential” document number 523126-1.3 with the revision history of that document retained for reference purposes continued... Intel® Communications Chipset 8925 to 8955 Series Software March 2016 Programmer's Guide Order No.: 330751-005 3 Intel® Communications Chipset 8925 to 8955 Series Software—Revision History Date Revision Description • Added Support for Multiple Acceleration Hardware Generations on page 23 • Added Utility for Loading Configuration Files and Sending Events to the Driver - adf_ctl on page 32 • Updated and added new sections to Heartbeat Feature and Recovery from Hardware Errors on page 46 • Updated Build Flag Summary on page 56 and General Parameters on page 65 • Added Stateless Compression Level Details on page 54 • Added further explanation and images to "decompression service" bullet at end of Intel® QuickAssist Technology API Limitations on page 95 • Added PfVfComms Feature Functions on page 131 • Added Reset Device Function on page 134 March 2014 1.3 Updates include: • Added new information to "direct user space access" bullet in Acceleration Drivers Overview on page 27 • Added further detail to note in Hardware Assisted Rings on page 27 • Updated Linux* Software Context for Acceleration Drivers on page 29 • Added Stateless Compression Level Details on page 54 • Added Dynamic Compression for Data Compression Service on page 99, Maximal Expansion with Auto Select Best Feature for Data Compression Service on page 99, and Maximal Expansion and Destination Buffer Size December 1.2 Updates include: 2013 • Added new information to Intel® QuickAssist Technology API Limitations on page 95 • Changed document and software title (expanded SKU range to include "8955") October 2013 1.1 Updates include: • Added NRBG and DRBG information to Random Number Generation Functions on page 119 October 2013 1.0 Corresponds with software release 1.0. Updates include: • Removed two stateful compression/decompression limitations from Intel® QuickAssist Technology API Limitations on page 95 • Changed product branding June 2013 0.5 Corresponds with software release 0.5 Intel® Communications Chipset 8925 to 8955 Series Software Programmer's Guide March 2016 4 Order No.: 330751-005 Contents—Intel® Communications Chipset 8925 to 8955 Series Software Contents Revision History..................................................................................................................3 Part 1: Overview............................................................................12 1.0 Introduction................................................................................................................13 1.1 Terminology.........................................................................................................13 1.2 Document Organization......................................................................................... 13 1.3 Product Documentation......................................................................................... 13 1.4 Typographical Conventions.....................................................................................14 2.0 Platform Overview...................................................................................................... 15 2.1 Platform Synopsis................................................................................................. 15 2.2 Determining the PCH SKU Type.............................................................................. 15 2.3 Determining the PCH Device Stepping..................................................................... 17 3.0 Software Overview..................................................................................................... 18 3.1 High-Level Software Architecture Overview.............................................................. 18 3.2 Logical Instances.................................................................................................. 20 3.2.1 Response Processing................................................................................. 20 3.2.1.1 Interrupt Mode............................................................................. 20 3.2.1.2 Polled Mode..................................................................................21 3.2.1.3 Epolled Mode................................................................................22 3.3 Operating System Support..................................................................................... 23 3.4 OpenSSL* Library Inclusion and Usage.................................................................... 23 3.5 Support for Multiple Acceleration Hardware Generations.............................................23 Part 2: Acceleration Drivers...........................................................26 4.0 Acceleration Drivers Overview.................................................................................... 27 4.1 Hardware Assisted Rings........................................................................................27
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