Overview n Getting Started with Lab 2 Lecture 8: n Just get a single pixel calculating at one time n Then look into filling your pipeline n Multipliers More Pipelining n Different options for pipelining: what do you need? n 3 Multipliers or put x*x, y*y, and x*y through sequentially? David Black-Schaffer n Pipelining
[email protected] n If it won’t fit in one clock cycle you have to divide it EE183 Spring 2003 up so each stage will fit n The control logic must be designed with this in mind n Make sure you need it EE183 Lecture 8 - Slide 2 Public Service Announcement Logistics n n Xilinx Programmable World Lab 2 Prelab due Friday by 5pm n Tuesday, May 6th n http://www.xilinx.com/events/pw2003/index.htm n Guest lecture next Monday n Guest Lectures Synchronization and Metastability n Monday, April 28th These are critical for high-speed systems and Ryan Donohue on Metastability and anything where you’ll be connecting across Synchronization clock domains. n Wednesday, May 7th Gary Spivey on ASIC & FPGA Design for Speed n The content of these lectures will be on the Quiz SHOW UP! (please) EE183 Lecture 8 - Slide 3 EE183 Lecture 8 - Slide 4 1 Easier FSMs Data Path always @(button or current_state) Do this if nothing else is begin Xn Yn write_en <= 0; specified. Mandel X Julia X Mandel X Julia Y output <= 1; next_state <= `START_STATE; Mux * * * Mux case(current_state) Note that the else is not `START_STATE: specified. begin write_en <= 1; - <<1 + if (button) next_state <= `WAIT_STATE; What is the next state? end What do we+ do if the+ wholeIf>4