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32-Bit RISC Series SH-4, ST40 System Architecture, Volume 1: System UM0339 User manual SuperH™ (SH) 32-bit RISC series SH-4, ST40 system architecture, volume 1: system This manual describes the ST40 family system architecture. It is split into four volumes: ST40 System Architecture - Volume 1 System - ADCS 7153464. ST40 System Architecture - Volume 2 Bus Interfaces - ADCS 7181720. ST40 System Architecture - Volume 3 Video Devices - ADCS 7225754. ST40 System Architecture - Volume 4 I/O Devices - ADCS 7225754. July 2007 Rev 2 1/426 www.st.com PRELIMINARY DATA Contents Preface xxi Document identification and control xxi ST40 documentation suite xxi ST40 Micro Toolset User’s Guide xxi OS21 User’s Manual xxii OS21 for ST40 User Manual xxii 32-Bit RISC Series, SH-4 CPU Core Architecture xxii 32-Bit RISC Series, SH-4, ST40 System Architecture xxii Conventions used in this guide xxiii General notation xxiii Hardware notation xxiii Software notation xxiii 1Overview 1 1.1 ST40 features 1 1.2 Block diagram 2 1.2.1 CPU 3 1.2.2 FPU/MAC 3 1.2.3 MMU 4 1.2.4 Cache 4 1.2.5 Interrupt 5 1.2.6 DMA controller 5 STMicroelectronics ADCS 7153464G SH-4, ST40 System Architecture, Volume 1: System PRELIMINARY DATA vi 1.2.7 Debugging and emulation 5 1.2.8 Power management 6 1.2.9 Timers 6 1.2.10 Real-time clock 6 1.2.11 Serial communication 6 1.2.12 External memory support 6 2 System organization 7 2.1 The SuperHyway 7 2.1.1 SuperHyway architecture 7 2.1.2 Packets 9 2.1.3 Transactions 10 Request Response A complete transaction 2.1.4 SuperHyway packet-router 13 2.2 Physical address map 13 3 Interrupt controller (INTC) 15 3.1 Overview 15 3.1.1 INTC features 15 3.1.2 Block diagram 16 3.1.3 Pin configuration 17 3.1.4 Register configuration 17 3.2 Interrupt sources 19 3.2.1 NMI interrupts 19 3.2.2 IRL interrupts 20 3.2.3 On-chip peripheral module interrupts 22 3.2.4 Interrupt exception handling and priority 23 3.3 INTC registers 26 3.3.1 Interrupt priority registers A to D (IPRA to IPRD) 26 3.3.2 Interrupt control register (ICR) 27 STMicroelectronics SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G PRELIMINARY DATA vii Bit 15: NMI input level (NMIL) Bit 14: NMI interrupt mask (MAI) Bit 9: NMI block mode (NMIB) Bit 8: NMI edge select (NMIE) Bit 7: IRL pin mode Bits 13 to 10 and 6 to 0: reserved 3.3.3 Interrupt priority registers (INTPRI00, INTPRI04, INTPRI08) 30 3.3.4 Interrupt request registers (INTREQ00, INTREQ04, INTREQ08) 32 3.3.5 Interrupt mask registers (INTMSK00, INTMSK04, INTMSK08) 34 3.3.6 Interrupt mask clear registers (INTMSKCLR00, INTMSKCLR04, INTMSKCLR08) 36 3.3.7 INTC2 mode register (INTC2MODE) 38 3.4 INTC operation 40 3.4.1 Interrupt sequence 40 3.4.2 Multiple interrupts 42 4 GPDMA controller (DMAC) 43 4.1 Features 43 4.2 Address map 45 4.2.1 Channel 0: multiplexed DMA channel 47 4.2.2 Channels 1 to 4: linked list DMA channel 49 4.3 Peripheral allocation 50 4.4 DMA operation 51 4.4.1 DMA transfer procedure 51 Stall Error Disable Completion 4.4.2 DMA transfer units 53 4.4.3 DMA timing model 53 Free-running Triggered STMicroelectronics ADCS 7153464G SH-4, ST40 System Architecture, Volume 1: System PRELIMINARY DATA viii Paced 4.4.4 DMA requests 54 4.4.5 DMA data organization 55 Single location/0D Incrementing/1D Rectangular array/2D 4.4.6 Endianness 57 4.4.7 DMA channel arbitration 57 4.4.8 Extension to basic DMA operations 57 Single linked list Multiplexed channels 4.5 Interfaces 60 4.6 Register descriptions 61 4.6.1 Global registers 62 DMA.VCR.STATUS DMA.VCR.VERSION DMA.ENABLE DMA.DISABLE DMA.STATUS DMA.INTERRUPT DMA.ERROR DMA.DEFINED DMA.HANDSHAKE 4.6.2 Channel specific registers 71 DMA.CHAN[n].IDENTITY DMA.CHAN[n].ENABLE DMA.CHAN[n].DISABLE DMA.CHAN[n].STATUS DMA.CHAN[n].ACTION DMA.CHAN[n].POINTER DMA.CHAN[n].REQUEST DMA.CHAN[n].SUBBASE DMA.CHAN[n].SUBENABLE DMA.CHAN[n].SUBDISABLE DMA.CHAN[n].SUB_INTENB DMA.CHAN[n].SUBINT_DIS DMA.CHAN[n].SUBINT_STAT DMA.CHAN[n].SUBINT_ACT 4.6.3 Memory mapped channel registers 93 STMicroelectronics SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G PRELIMINARY DATA ix DMA.CHAN[n].CONTROL DMA.CHAN[n].COUNT DMA.CHAN[n].SAR DMA.CHAN[n].DAR DMA.CHAN[n].NEXT_PTR DMA.CHAN[n].SRC_LENGTH DMA.CHAN[n].SRC_STRIDE DMA.CHAN[n].DST_LENGTH DMA.CHAN[n].DST_STRIDE 5 Parallel input/output (PIO) 107 5.1 PIO ports 0 to 2 107 5.2 Register descriptions 109 5.2.1 Output registers 109 5.2.2 Input registers 112 5.2.3 Configuration registers 113 5.2.4 PIO input compare and compare mask registers 116 5.2.5 Pseudoregisters 118 6 Clock and power management 121 6.1 Overview 121 6.2 Address map 122 6.2.1 CPG bank 122 6.2.2 CLKGEN bank 123 6.3 Clock functionality 125 6.3.1 Internal organization 125 6.3.2 PLL1 control 127 Diagram Introduction Allowable transitions State definitions Enabling and disabling PLL1 Changing PLL1 divide ratios (clk1 to 3) Changing the PLL1 divide ratio for clock 14 Changing PLL1 lock frequency STMicroelectronics ADCS 7153464G SH-4, ST40 System Architecture, Volume 1: System PRELIMINARY DATA x PLL frequency calculation 6.3.3 Configuring PLL2 132 Introduction Procedure to enable and disable PLL2 Changing the frequency of PLL2 6.3.4 Register description 134 Frequency control register 1 (CPG.FRQCR) CLKGEN.PLL1CR1 CLKGEN.PLL1CR2 CLKGEN.PLL2CR CLOCKGEN.CLK4CR CLOCKGEN.CPGBYPASS CLKGEN.PLL2_MUXCR CLKGEN.CLK1CR CLKGEN.CLK2CR CLKGEN.CLK3CR CLKGEN.CLK_SELCR 6.4 Watchdog timer 153 6.4.1 Block diagram 153 6.4.2 Register configuration 154 6.4.3 Register descriptions 154 Watchdog timer counter (CPG.WTCNT) Watchdog timer control and status register (CPG.WTCSR) Bit 7: timer enable (TME) Bit 6: timer mode select (WT/NOT_IT) Bit 5: reset select (RSTS) Bit 4: watchdog timer overflow flag (WOVF) Bit 3: interval timer overflow flag (IOVF) Bits 2 to 0: clock select 2 to 0 (CKS2 to CKS0) Writing to CPG.WTCNT and CPG.WTCSR 6.4.4 Using the WDT 159 Standby clearing procedure Frequency changing procedure Using watchdog timer mode Using interval timer mode 6.5 Power management unit (PMU) 161 6.5.1 Types of power-down modes 162 6.5.2 Register configuration 164 STMicroelectronics SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G PRELIMINARY DATA xi 6.5.3 Pin configuration 165 6.5.4 Register descriptions 165 Standby control register (CPG.STBCR) Bit 7: standby (STBY) Bit 6: peripheral module pin high impedance control (PHZ) Bit 5: peripheral module pin pull-up control (PPU) Bit 4: unused Bit 3: module stop 3 (MSTP3) Bit 2: module stop 2 (MSTP2) Bit 1: module stop 1 (MSTP1) Bit 0: module stop 0 (MSTP0) Peripheral module pin pull-up control Standby control register 2 (CPG.STBCR2) Bit 7: unused Bit 6: status pin high-impedance control (STHZ) Bits 5 to 2: reserved Bit 1: module stop 6 (MSTP6) Bit 0: module stop 5 (MSTP5) Standby control request register (CLOCKGEN.STBREQCR) Standby control acknowledge register (CLOCKGEN.STBACKCR) 6.6 Functionality 171 6.6.1 Sleep mode 171 Transition to sleep mode Exit from sleep mode Exit by interrupt Exit by reset 6.6.2 Deep sleep mode 172 Transition to deep sleep mode Exit from deep sleep mode 6.6.3 Standby mode 172 Transition to standby mode Exit from standby mode Exit by interrupt Exit by reset 6.6.4 Clock pause function 174 6.7 Module standby function 175 STMicroelectronics ADCS 7153464G SH-4, ST40 System Architecture, Volume 1: System PRELIMINARY DATA xii 6.7.1 Transition to module standby function (CPG modules) 175 6.7.2 Transition to module standby function (CLOCKGEN modules) 176 6.7.3 Exit from module standby function (CPG modules) 176 6.7.4 Exit from module standby function (CLOCKGEN modules) 177 6.8 STATUS pin change timing 177 7Real-time clock (RTC) 179 7.1 Overview 179 7.1.1 Features 179 7.1.2 Block diagram 181 7.1.3 Pin configuration 182 7.1.4 Register configuration 182 7.1.5 Register initialization 184 7.2 Register descriptions 185 7.2.1 64 Hz counter (RTC.R64CNT) 185 7.2.2 Second counter (RTC.RSECCNT) 186 7.2.3 Minute counter (RTC.RMINCNT) 188 7.2.4 Hour counter (RTC.RHRCNT) 190 7.2.5 Day-of-week counter (RTC.RWKCNT) 192 7.2.6 Day counter (RTC.RDAYCNT) 194 7.2.7 Month counter (RTC.RMONCNT) 196 7.2.8 Year counter (RTC.RYRCNT) 198 7.2.9 Second alarm register (RTC.RSECAR) 200 7.2.10 Minute alarm register (RTC.RMINAR) 202 7.2.11 Hour alarm register (RTC.RHRAR) 204 7.2.12 Day-of-week alarm register (RTC.RWKAR) 206 7.2.13 Day alarm register (RTC.RDAYAR) 208 7.2.14 Month alarm register (RTC.RMONAR) 210 7.2.15 RTC control register 1 (RTC.RCR1) 212 7.2.16 RTC control register 2 (RTC.RCR2) 215 STMicroelectronics SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G PRELIMINARY DATA xiii 7.3 Operation 219 7.3.1 Time setting procedures 219 7.3.2 Time reading procedures 221 7.3.3 Alarm function 222 7.4 Interrupts 223 7.5 Usage notes 223 7.5.1 Register initialization 223 7.5.2 Crystal oscillator circuit 224 8 Timer unit (TMU) 227 8.1 Overview 227 8.1.1 Features 227 8.1.2 Block diagram 229 8.1.3 Pin configuration 229 8.1.4 Register configuration 230 8.2 Register descriptions 232 8.2.1 Timer output control register (TMU.TOCR) 232 8.2.2 Timer start register (TMU.TSTR) 233 8.2.3 Timer constant registers (TMU.TCOR) 234 8.2.4 Timer counters (TMU.TCNT) 235 8.2.5 Timer control registers (TMU.TCR) 236 8.2.6 Input capture register (TMU.TCPR2) 243 8.3 Operation 244 8.3.1 Counter operation 244 Example of count operation setting procedure Auto-reload count operation TCNT count timing 8.3.2 Input capture function 248 8.4 Interrupts 249 8.5 Usage notes 250 8.5.1 Register writes 250 8.5.2 TCNT register reads 250 STMicroelectronics ADCS 7153464G SH-4, ST40 System Architecture, Volume 1: System PRELIMINARY DATA xiv 8.5.3 Resetting the RTC frequency
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