Design of W-Band High-Isolation T/R Switch

Chien-Chang Chou,Shih-Chiao Huang, Wen-Chian Lai, H.-C. Kuo,and Huey-Ru Chuang Institute of Computer and Communication Engineering, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.

transmitting Port 1 Abstract — This paper presents a W-band CMOS SPDT signal V c Antenna Vcb high isolation T/R switch fabricated in 90nm CMOS. The leakage signal switch is designed by using series-shunt structure with t On t body-floating technique to improve the insertion loss and M M linearity. To achieve high-isolation performance, the TX 1 RB 2 RB RX parallel inductor and leakage cancellation technique are Port 3Vcb Vc Port 2 adopted. The measurement results show that the designed switch has a good performance in the return loss, insertion loss and isolation in W-band 75-110GHz frequency band. 90° M3 Microstrip line M4 Compared with reported works, the designed switch has Microstrip line Microstrip line the best isolation performance of 48 dB at 94-GHz. L 90° phase shifter 90° phase shifter L Index Terms — 90-nm, body-floating, CMOS, high- isolation, leakage cancellation, T/R Switch, W-band

Fig. 1. Circuit schematic of the proposed W-band high-isolation T/R I. INTRODUCTION switch with leakage cancellation.

A high performance millimeter-wave (MMW) R RD RB transmitter/receiver (T/R) switch plays an important role D in wireless communication systems. The T/R switch is used so that the transmitter and the receiver can be Tx Tx R Antenna RD Ron Antenna fabricated in a chip simultaneously with single antenna on C R RB to save area and cost of the chip. In the past few years, off D Coff Transmitted signal the operating frequency of the related MMW researches Leakage signal Transmittrd signal has raised to sub-Tera hertz, such as W- / D- / F-band for Smaller leakage signal (a) (b) high data rate communication [1]. For example, the 94- GHz frequency band is used in MMW imaging radar for Fig. 2. Equivalent-circuit model in Tx mode: (a) without, and (b) with concealed weapon detection and gesture recognition [2]. body-floating technique. Many MMW switches designed at sub-Tera hertz range have been reported [3]–[6]. Due to the advantage of low- II. CIRCUIT DESIGN cost and high integration of the baseband and the RF front-end, the CMOS technology is one of the most The proposed schematic of the W-band series-shunt attractive solutions to implement a highly-integrated type SPDT T/R switch with the body-floating, parallel systems-on-chip (SoC) for millimeter-wave inductor and leakage cancellation technique is shown in communication applications. Fig. 1. The body-floating technique is adopted to reduce Low insertion loss and high isolation are the design the insertion loss by simply connecting a large resistor key points of T/R switches. The series-shunt structure RB to ground at body of transistor in this work. This can be used to achieve good performance in single-pole technique can provide a high impedance path to decrease the leakage signal and obtain a better insertion loss double-throw (SPDT) switches. However, the performance as shown in Fig. 2. In MMV frequency performance of series-shunt structure is deteriorated by range, the parasitic effect of the transistor becomes the parasitic effect at high frequency range. For instance, significant. Hence, the isolation will be degraded when the drain-to-source capacitance of the transistor will the Tx signal leaks to the Rx port through the parasitic degrade the isolation performance at MMW frequency drain-source capacitor (Cds). The leakage cancellation range. In [7], the leakage cancellation technique is technique [7] which consists of two transistors (M3-M4) adopted in 60-GHz CMOS switch to improve the and two 90-degree phase shifters can be used to isolation between receiving (Rx) and transmitting (Tx) overcome this issue. As shown in Fig .1, the isolation port. Furthermore, the parallel shunt inductor [8] is used can be further improved by eliminate the leakage signal to enhance switch isolation. As for the insertion loss, the (red line) with another signal (blue dot line) with 180° body-floating technique by adding a large resistor at the phase difference. Here, two meander transmission lines body of the MOS switch transistor can reduce the are used to obtain a 180° phase difference. insertion loss [9]. 0 50 Meas._Return Loss (@ Vc = 1.2 V) -0.5 Simu._Return Loss (@ Vc = 1.2 V) 40 Meas._Insertion Loss (@ Vc = 1.2 V)

-1 ) Simu._Insertion Loss (@ Vc = 1.2 V)

B

)

B

d (

d -1.5 30

(

|

L

1

I

2 -2

S | & 20 -2.5

NMOS:ON L

finger_8 finger_32 R -3 10 finger_16 finger_40 finger_24 finger_48 -3.5 40 60 80 100 120 140 0 Frequency (GHz) 75 80 85 90 95 100 105 110 (a) Frequency (GHz) 0 (a) -3 70

) Tx to Rx isolation B -6

d 60

(

|

)

1 2

-9 B

S

d 50

| (

NMOS:OFF n

-12 finger_8 finger_32 o 40 i

finger_16 finger_40 t

finger_24 finger_48 a l 30

-15 o

40 60 80 100 120 140

s I Frequency (GHz) 20 Meas._Isolation_Tx (b) Simu._Isolation_Tx Fig. 3. Size choosing of the transistors with different number of 10 75 80 85 90 95 100 105 110 fingers when (a) NMOS on, (b) NMOS off . Frequency (GHz) 0 (b) Fig. 5. Simulated and measurement results: (a) input return loss (S11) -15 and insertion loss (S21), (b) isolation (S32)

)

B -30 d

(

|

3 can be reduced and a better insertion loss performance is

2 -45 S | achieved. However, the junction capacitance is increased by larger nf and results in more signal leakage. Base on -60 W/o inductor With inductor the analysis and simulation results above, nf is chosen as With inductor and leakage cancellation -75 16 with width and length as 2 and 0.1 μm respectively 70 80 90 100 110 120 130 140 for this proposed circuit design. Frequency (GHz) Fig. 4. Simulated isolation results with/without using parallel inductor and leakage cancellation B. Parallel inductor design

In order to further increase the isolation in this work, A. Transistors size consideration four parallel inductors are connected to each transistors. At resonance frequency (f = 1 / 2π ), the parasitic In order to obtain both of the high isolation and low LC insertion loss performance for the designed W-band T/R capacitors of transistors in off-state can resonate with parallel inductors and act as a open circuit. By using this switch, Fig. 3 (a)-(b) shows the simulated S21 of single transistor with different number of fingers (nf). From technique, the isolation performance will be improved. simulation results, a better insertion loss performance After deciding the size of transistors in section A, the can be achieve by choosing bigger nf. However, if the equavilent capitances of transistors in off-state at transistor is chosen with larger nf, a worse isolation specific frequecy can be obtained from ADS simulator. performance is occured. There are trade-off between From simulation result, a equavilent capitance of 11.7 fF isolation and insertion loss performance. This simulation is estimated. Therefore, by determining center frequency results can be explained from eq. (1), as 105 GHz, the inductance is chosen as 245 pH. As shown in Fig. 4, the isolation performance of this work 1 R  becomes better after using parallel inductor and leakage on W (1) μCox (Vgs Vt ) cacellation techniques. L The insertion loss of the transistor is dominated by its on-resistance (Ron). By increasing the transistor’s nf, Ron

TABLE I PERFORMANCE COMPARISON OF MMW T/R SWITCHES

[3] [4] [5] [6] This work Reference MTT 2006 MWCL 2010 EuMC 2010 MWCL 2007 0.15 µm 90 nm 45nm 90 nm 90-nm Process GaAs HEMT COMS CMOS CMOS CMOS Topology SPDT SPDT SPDT SPDT SPDT Transmission-line Leakage Design Approach Traveling wave Traveling wave Traveling wave integrated cancellation Frequency range (GHz) 20-135 60 – 110 50-110 50-94 75 - 110 Return loss (dB) > 10 > 15 > 5 > 10 > 11.1 < 6.3 Insertion loss (dB) < 6 < 4 5.3@ 94GHz < 3.3 4.5 @ 94GHz > 27 > 25 > 20 Isolation (dB) 20.5@ 94GHz 31@ 94GHz 42 @ 94GHz 27 @ 94GHz 48 @ 94GHz 11.2 @ 77-GHz IP (dBm) 15@ 77 GHz 10.5@ 75 GHz 11@ 60GHz 15@ 77 GHz 1dB 11@ 94-GHz Chip size (mm2) 0.69 0.3 0.56 0.24 0.33

15 III. MEASUREMENT RESULTS Tx mode

) The designed switch is fabricated with the 90-nm m 10

B CMOS process. The switch uses high (1.2 V) and low (0

d (

V) control voltages for T/R mode selection. The HFSS B

d 5 and ADS simulation tool is used for the field analysis.

1 P

I As shown in Fig. 5(a)-(b), the measurement results show simu. that the insertion loss and isolation performance are meas. 0 better than 6.3 dB and 20 dB from 75 to 110 GHz, 75 77 79 81 83 85 respectively. At 94-GHz, a high-isolation performance of Frequency (GHz) 48 dB is observed. As shown in Fig. 6, the measured Fig. 6. Simulated and measurement results: IP1dB. IP1dB is better than 11 dBm up to 77 GHz (due to 80 frequency limitation of the instrumentation setup). At Tx mode meas. @ 94GHz 70 94-GHz, it is estimated that the IP1dB can be about 11

) 60 dBm. Also, the variation of isolation in different input B

d 50 power at 94-GHz has been investigated as shown in Fig.

(

n 7. The measured isolation is from 47.6 to 30.7 dB as the

o 40 i

t input power increases from -8.5 to 9 dBm. The chip a

l 30

o micrograph is shown in Fig. 8. with a chip size of 0.33 s I 20 Input power = -8.5 / 9 dBm mm2 . Isolation : 47.6 / 30.7 dB 10 Table I summarizes the measured performance 0 -10 -8 -6 -4 -2 0 2 4 6 8 10 comparison. Overall, the designed switch has a good performance in the return loss, insertion loss and Input power (dBm) Fig. 7. Measured isolation at different input power at 94-GHz isolation in W-band 75-110GHz frequency band. Also compared with reported works, the designed switch has the best isolation performance of 48 dB at 94-GHz.

IV. CONCLUSION

The design of a W-band CMOS SPDT high isolation T/R switch fabricated in 90nm CMOS is presented. The switch is designed by using series-shunt structure with floating technique to improve the insertion loss and linearity. The parallel inductor and leakage cancellation techniques are used to obtained a high-isolation performance. The measured insertion loss and isolation are better than 6.3 dB and 20 dB from 75 to 110 GHz, respectively. At 94-GHz, a high-isolation performance of 48 dB is achieved. The insertion loss, IP1dB and IIP3 are

4.5 dB, 11 and 20.8 dBm at 94 GHz, respectively. The chip size is 0.33 mm2. The designed T/R switch will be Fig. 8. Chip micrograph. (chip size: 0.33 mm2) very useful for the front-end integration of the W-band CMOS single-chip RF transceiver. REFERENCES

[1] A. Arbabian, S. Callender, S. Kang, B. Afshar, J. –C. Chien, and A. M. Niknejad, “ A 90 GHz Hybrid Switching Pulsed- Transmitter for Medical Imaging,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2667–2681, Dec 2010. [2] A. Arbabian, S. Callender, S. Kang, M. Rangwala, and A. M. Niknejad, “A 94 GHz mm-Wave-to-Baseband Pulsed-Radar Transceiver with Applications in Imaging and Gesture Recognition,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 1055–1071, Apr. 2013. [3] Z. M. Tsai, M. C. Yeh, M. F. Lei, H. Y. Chang, C. S. Lin, and H. Wang, “FET-integrated CPW and the application in filter synthesis design method on traveling-wave switch above 100 GHz,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 5, pp. 2090–2097, May 2006. [4] R.-B. Lai, J.-J. Kuo, and H. Wang, “A 60–110 GHz transmission- line integrated SPDT switch in 90 nm CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 2, pp. 85–87, Feb. 2010. [5] T. Quémerais, L. Moquillon, J.-M. Fournier1, and P. Benech, “A SPDT Switch in a standard 45 nm CMOS process for 94 GHz Applications,”. in Eur. Microwave Conf., Sep. 2010, pp. 425 – 428 [6] S. F. Chao, H. Wang, C.-Y. Su, and J. G. J. Chern, “A 50 to 94- GHz CMOS SPDT switch using traveling-wave concept,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 2, pp. 130–132, Feb. 2007 [7] C. –S. Kuo, H. –C. Kuo, H. –R. Chuang, C. -Y Chen and T. –H. Huang “A High-Isolation 60GHz CMOS Transmit/Receive Switch,” in IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2011, pp. 1–4. [8] C.-Y. Ou, H.-R. Lin, H.-R. Chuang and T.-H. Huang, “A high- isolation high-linearity 24-GHz CMOS T/R switch in the 0.18- μm CMOS process,” in Eur. Microw. Conf., Sep. 2009, pp. 250– 253. [9] F.-J. Huang and K.O, “A 0.5 μm CMOS T/R switch for 900-MHz wireless application,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 486-492, Mar. 2001.