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Formal Equivalence Checking and Design Debugging Frontiers in Electronic Testing

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Formal Equivalence Checking and Design Debugging Frontiers in Electronic Testing FORMAL EQUIVALENCE CHECKING AND DESIGN DEBUGGING FRONTIERS IN ELECTRONIC TESTING Consulting Editor Vishwani D. Agrawal Books in the series: On-Line Testing for VLSI M. Nicolaidis, Y. Zorian ISBN: 0-7923-8132-7 Defect Oriented Testing for CMOS Analog and Digital Circuits M. Sachdev ISBN: 0-7923-8083-5 Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques W. Kunz, D. Stoffel ISBN: 0-7923-9921-8 Introduction to IDDQ Testing S. Chakravarty, P.J. Thadikaran ISBN: 0-7923-9945-5 Multi-Chip Module Test Strategies ¥. Zorian ISBN: 0-7923-9920-X Testing and Testable Design of High-Density Random-Access Memories P. Mazumder, K. Chakraborty ISBN: 0-7923-9782-7 From Contamination to Defects, Faults and Yield Loss J.B. Khare, W. Maly ISBN: 0-7923-9714-2 Efficient Branch and Bound Search with Applications to Computer-Aided Design X.Chen, M.L. Bushnell ISBN: 0-7923-9673-1 Testability Concepts for Digital ICs: The Macro Test Approach F.P.M. Beenker, R.G. Bennetts, A.P. Thijssen ISBN: 0-7923-9658-8 Economics of Electronic Design, Manufacture and Test M. Abadir, A.P. Ambler ISBN: 0-7923-9471-2 IDDQ Testing of VLSI Circuits R. Gulati, C. Hawkins ISBN: 0-7923-9315-5 FORMAL EQUIVALENCE CHECKING AND DESIGN DEBUGGING by Shi-Yu Huang National Semiconductor Corporation and Kwang-Ting (Tim) Cheng University 0/ California, Santa Barbara ~. SPRINGER SCIENCE+BUSINESS" MEDIA, LLC Library of Congress Cataloging-in-Publication Huang, Shi-Yu, 1965- Formal equivalence checking and design debugging / by Shi-Yu Huang and Kwang-Ting (Tim) Cheng p. cm. Includes bibliographical references and index. ISBN 978-1-4613-7606-4 ISBN 978-1-4615-5693-0 (eBook) DOI 10.1007/978-1-4615-5693-0 1. Integrated circuits-- Verification. 2. Electronic circuit design--Data processing. 3. Application specific integrated circuits--Design and construction. I. Cheng, Kwang-Ting, 1961- 11. Title. TK7874.H82 1998 621.3815--dc21 98-23993 CIP Copyright <0 1998 Springer Science+Business Media New York. Second Printing 2002. Originally published by Kluwer Academic Publishers, New York in 1998 Softcover reprint of the hardcover 1st edition 1998 This printing is a digital duplication of the original edition. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC Printed on acid-free paper. FORMAL EQUIVALENCE CHECKING AND DESIGN DEBUGGING CONTENTS Foreword xi Preface xvii Chapter 1 Introduction 1 1.1 Problems of Interest ......................................................................................... 1 1.1.1 Equivalence Checking ........................................................................ 3 1.1.2 Design Error Diagnosis and Correction .............................................. 8 1.2 Organization ................................................................................................... 10 PART I EQUIVALENCE CHECKING Chapter 2 Symbolic Verification 17 2.1 Symbolic Verification by FSM TraversaL .................................................... 17 2.2 Implicit State Enumeration by BDD .............................................................. 19 2.2.1 Set Representation ............................................................................ 20 2.2.2 Input/Output Relation ....................................................................... 21 2.2.3 Transition Relation ........................................................................... 23 2.2.4 Next-State Computation ................................................................... 25 2.2.5 Complete Flow ......................................................................... , ........ 26 2.2.6 Error Trace Generation ..................................................................... 28 2.3 Speed-up Techniques ..................................................................................... 30 2.3.1 An Efficient Method for Constructing Transition Relation ;............. 30 2.3.2 Reduction on Image Computation .................................................... 33 2.3.3 Reduction on Reachable State Computation .................... , ............... 36 2.4 Summary ........................................................................................................ 37 Chapter 3 Incremental Verification for Combinational Circuits 39 3.1 Substitution-Based Algorithms ...................................................................... 39 3.1.1 Brand's Algorithm Using ATPG ....................................................... 39 Pairing up candidate pairs ................................................................ 41 Pruning the miter incrementally ....................................................... 42 Checking the equivalence of primary outputs .................................. 44 3.1.2 Enhancement by Local BDD ....................................................... , .... 44 Constructing BDDs using a dynamic support .................................. 46 Experimental results ......................................................................... 48 3.2 Learning-Based Algorithms ...................................................................... :.... 50 3.2.1 Recursive Learning ....................................... , ............................. :..... 50 Vlll 3.2.2 Verification Flow Using Recursive Learning .................................... 51 3.3 Transformation-Based Algorithm .................................................................. 53 3.3.1 Identifying Dissimilar Region .......................................................... 53 3.3.2 Similarity Enhancing Transformation (SET) .................................... 55 3.4 Summary ........................................................................................................ 57 Chapter 4 Incremental Verification for Sequential Circuits 61 4.1 Definition of Equivalence .............................................................................. 62 :4.1.1 Equivalence of Circuits With A Reset State ..................................... 62 "4.1.2 Equivalence of Circuits Without A Reset State ................................ 62 Sequential Hardware Equivalence .................................................... 63 Safe Replaceability ........................................................................... 65 Three-Valued Safe Replaceability .................................................... 66 Three-Valued Equivalence ................................................................ 67 4.1.3 Comparison of Definitions ................................................................ 67 4.2 Methodology .................................................................................................. 72 4.2.1 Checking Three-Valued Safe Replaceability .................................... 73 4.2.2 Checking Reset Equivalence ............................................................. 74 4.2.3 Checking Three-Valued Equivalence ................................................ 76 4.3 The Speed-Up Techniques ............................................................................. 76 4.3.1 Test Generation with Breadth-First-Search ...................................... 77 4.3.2 Exploring the Structural Similarity ................................................... 79 4.3.3 Identifying Equivalent Flip-Flop Pairs ............................................. 80 4.4 Experimental Results ..................................................................................... 84 4.5 Summary ........................................................................................................ 86 4.6 Appendix ........................................................................................................ 87 Chapter-S AQUILA: A Local BDD-based Equivalence Verifier 91 5.1 Overall Flow .................................................................................................. 91 5.2 Two-Level Inductive Algorithm ..................................................................... 93 5.2.1 .Second-Level Assume-And-Then-Verify ......................................... 95 5.3 Symbolic Backward Justification ................................................................... 97 5.3.1 Partial Justification .......................................................................... 100 5.3.2 An Example .................................................................................... 102 5.4 Experimental Results ................................................................................... 105 5.5 Summary ...................................................................................................... 107 Chapter 6 Algorithm for Verifying Retimed Circuits 111 6.1 Introduction .................................................................................................. 111 6.2 Pre-Processing Algorithm ............................................................................ 113 6.2.1 Signature Computation ................................................................... 115 ix 6.2.2 Deriving Candidate Delayed-Equivalent Pairs ............................... 115 6.2.3 Delay Compensation ....................................................................... 117 6.3 Experimental Results ................................................................................... 118 6.4 Summary .....................................................................................................
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