Book of Abstracts Ii Contents
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TWEPP-09 Topical Workshop on Electronics for Particle Physics Monday, 21 September 2009 - Friday, 25 September 2009 Institut des Cordeliers 15, rue de l’Ecole de Médecine (Métro Odéon) Paris, France Book of Abstracts ii Contents A flash high-precision Time-to-Digital Converter implemented in FPGA technology . 1 Commissioning of the CSC Level 1 Trigger Optical Links at CMS ............. 1 Simple parallel stream to serial stream converter for Active Pixel Sensor readout. 1 A facility and a web application for real-time monitoring of the TTC backbone status . 2 Radiation Hardness of Graded-index Optical Fibre in Sub-Zero Temperature Environments ................................................ 3 The GCT μTCA Matrix Card and its Applications ...................... 4 CMD-3 First Level Trigger Infrastructure ........................... 4 A low-cost multi-channel analogue signal generator ..................... 5 Commissioning and performance of the Preshower off-detector readout electronics in the CMS experiment ...................................... 6 Design of a module providing trigger information from the CMS Tracker at SLHC . 7 About 10000 frames per second readout MAPS for the EUDET beam telescope . 8 Trigger Platforms for CMS at the SLHC ............................ 9 Gossipo-3: a prototype of a Front-end Pixel Chip for Read-out of Micro-Pattern Gas Detec- tors. ............................................. 10 The First Vertically Integrated MPW Run forHEP ...................... 11 Detector Control System for the Electromagnetic calorimeter in CMS Experiment . 12 ARadiation Tolerant 4.8 Gb/s Serializer for the Giga-Bit Transceiver . 12 Novel charge sensitive amplifier design methodology suitable for large detector capacitance applications ......................................... 13 Readout and Data Processing Electronics for the Super-Belle Silicon Vertex Detector . 14 BAO radio electronic system .................................. 15 The ATLAS ReadOut System - improved performance with the switch-based architecture 16 Development of a high resolution transient recorder .................... 17 iii e-link: A Radiation-Hard Low-Power Electrical Link for Chip-to-Chip Communication . 17 A Zero Suppression Micro-Circuit for Binary Readout CMOS Pixel Sensors . 18 A Digitally Calibrated 12 bits 35 MS/s Pipelined ADC with a 32 input multiplexer for CAL- ICE Integrated Readout ................................... 19 System Integration Issues of DC to DC converters in the sLHC Trackers . 20 A digital calorimetric trigger for the COMPASS experiment at CERN . 21 Wafer Screening of ABCN-25 readout ASIC ......................... 22 A 12 µm pitch CMOS Pixel Sensor Designed in the 3DIT for the ILC Vertex Detector . 23 Charge Pump Clock Generation PLL for the Data Output Blocks of the Upgraded ATLAS Front-End in 130nm CMOS ................................. 24 On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS) .................................... 25 Standalone radiation monitors for electronics in High Energy Physics . 26 Performance and comparison of custom serial powering regulators and architectures for SLHC silicon trackers .................................... 26 A programmable 10 Gigabit injector for the LHCb DAQ and its upgrade . 27 Construction and Performance of a Double-Sided Silicon Detector Module using the Origami Concept ........................................... 28 Low power discriminator for ATLAS pixel chip ....................... 29 Data acquisition system for a proton imaging apparatus . 29 ALICE TPC CONTROL AND READOUT SYSTEM ...................... 31 An integrated DC-DC step-up charge pump and step-down converter in 130 nm technology ................................................ 31 Error-free 10.7 Gb/s digital transmission over 2 km optical link using an ultra-low-voltage electro-optic modulator ................................... 32 Design of the CMS-CASTOR sub detector readout system by reusing existing designs . 33 Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC 33 The design of a low power, high speed phase locked loop . 34 High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers . 35 Development of a 16:1 serializer for data transmission at 5 Gbps . 36 Smart Analogue Sampler for the Optical Module of a Cherenkov Neutrino Detector . 37 Analogue Input Calibration of the ATLAS Level-1 Calorimeter Trigger . 38 iv Experimental studies towards a DC-DC conversion powering scheme for the CMS silicon strip tracker at SLHC .................................... 38 The Control System for a new Pixel Detector at the sLHC . 39 Measurement of the performances of a Low-Power Multi-Dynamics Front-End for Neutrino Underwater Telescope Optical Modules .......................... 40 Front-End Electronics for Pixel Detector of the PANDA MVD. 40 Replacing full custom DAQ test system by COTS DAQ components on example of ATLAS SCT readout ......................................... 41 Prototype flex hybrid and module designs for the ATLAS Inner Detector Upgrade utilising the ABCN-25 readout chip and Hamamatsu large area Silicon sensors. 42 ATLAS Silicon Microstrip Tracker Operation ......................... 43 The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHCexperi- ments ............................................. 44 Design of High Dynamic Range Digital to Analog Converters for Calibration of the CALICE readout electronics ..................................... 44 A 5 Gb/s Radiation Tolerant Laser Driver in 0.13 um CMOS technology . 45 The GBT project ......................................... 46 Upgrade of the Cold Electronics of the ATLAS HEC Calorimeter for sLHC: Generic Studies on Radiation Hardness and Temperature Dependence. 47 A latchup topology to investigate novel particle detectors . 49 LHCb Level 0 Decision Unit .................................. 49 3D electronics for hybrid pixel detectors ........................... 50 Buffer Control Chip (BCC) for the ATLAS Tracker Upgrade . 51 The 8 bits 100 MS/s pipe line ADC for the INNOTEP project . 52 Feasibility studies of a Level-1 Tracking Trigger for ATLAS . 53 Implementing the GBT data transmission protocol in FPGAs . 53 DEPFET Mini-matrix Readout System ............................. 54 An FPGA-based Emulation of the G-Link Chip-Set for the ATLAS Level-1 Barrel Muon Trigger ............................................ 54 Integrated Trigger and Data Acquisition system for the NA62 experiment at CERN . 55 Integrated test environment for a part of the LHCb calorimeter . 56 KM3NeT Power and Submarine Cable Systems for the kilometre cube Neutrino Telescope 57 Advanced Pixel Architectures for Scientific Image Sensors . 58 v Performance of the ABCN-25 readout chip for ATLAS Inner Detector Upgrade . 59 A new paradigm using GPUs for fast triggering and pattern matching at the CERN experi- ment NA62 ......................................... 60 Deep-sea data transfer at the KM3NeT neutrino telescope . 61 PARISROC, a photomultiplier array integrated readout chip . 62 A self triggered amplifier/digitizer chip for CBM ....................... 63 STUDY OF RADIATION HARDNESS OF PIN AND VCSEL ARRAYS . 63 DIRAC v2: a DIgital Readout Asic for hadronic Calorimeter . 64 Design Considerations for an Upgraded Track-Finding Processor in the Level-1 Endcap Muon Trigger of CMS for SLHC Operations ....................... 65 Framework for Testing and Operation of the ATLAS Level-1 MUCTPI and CTP . 65 Commissioning of the DT electronics under magnetic field. 66 ASIC buck converter prototypes for LHC upgrades ..................... 67 Precise Timing Adjustment for the ATLAS Level1 Endcap Muon Trigger System . 68 PERFORMANCE OF THE CMS REGIONAL CALORIMETER TRIGGER . 69 A 40 MHz trigger-free readout architecture for the LHCb experiment . 70 The Prompt Trigger of the Silicon Pixel Detector for the ALICE Experiment . 71 HARDROC, Readout chip of the Digital Hadronic Calorimeter of ILC . 72 Progress on DC-DC converters for SiTracker for SLHC ................... 72 SuperNemo Absolute Time Stamper, a high resolution and large dynamic range TDC for SuperNemo experiment ................................... 73 Passive Optical Networks in Particle Physics Experiments . 74 The Fast Tracker Architecture for the LHC baseline luminosity . 76 Hardware studies for the upgrade of the ATLAS Central Trigger Processor . 76 FPGA-based Bit-Error-Ratio Tester for SEU-hardened Optical Links . 77 ASPIC: LSST camera readout chip Comparison between DSI and C&S . 78 Silicon Photomultiplier integrated readout chip (SPIROC) for the ILC: characterization and mesurements ........................................ 79 Presentation of the “ROC” chips readout ........................... 79 Characterization of Semiconductor Lasers for Radiation Hard High Speed Transceivers . 80 Position Measurements with Micro-Channel Plates and Transmission Lines using Pico- second Timing and Waveform Analysis .......................... 81 vi Reduction techniques of the back gate effect in the SOI Pixel Detector . 81 Thin, Fully Depleted Monolithic Active Pixel Sensor with Binary Readout basedon3D Integration of Heterogeneous CMOS Layers ....................... 83 The Versatile Transceiver Proof of Concept .......................... 84 The GBTIA, a 5 Gbit/s radiation-hard optical receiver for the SLHC upgrades . 85 A SiGe ASIC Prototype for the ATLAS LAr Calorimeter Front-End Upgrade . 85 Radiation hardness studies of a 130