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IBM PC Interrupt Structure and 8259 DMA Controllers

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IBM PC Interrupt Structure and 8259 DMA Controllers ELEC 464 : MICROCOMPUTER SYSTEM DESIGN 1996/97 WINTER SESSION TERM 1 IBM PC Interrupt Structure and 8259 DMA Controllers This lecture covers the use of interrupts and the vectored interrupt mechanism used on the IBM PC using the Intel 8259 Programmable Interrupt Controller (PIC). After this lecture you should be able to: decide and explain why interrupts should (or should not) be used to service a particular peripheral, describe how the 8259 PIC is connected to handle multiple interrupt sources, and write 8088 assembly language code to initialize and service interrupts generated by the 8259 PIC. 1 Review of Interrupts an interrupt is a large percentage of the time available to service the device. Many peripheral devices such as serial interfaces, Exercise: Data is arriving on a serial interface at 4000 keyboards and real-time clocks need to be serviced characters per second. If this device is serviced by polling, periodically. For example, incoming characters or and each character must be read before another one is re- keystrokes have to be read from the peripheral or the ceived, what is the maximum time allowed between polls? current time value needs to be updated from a peri- If each poll requires 10 microseconds to complete, what odic clock source. fraction of the CPU time is always being used up even The two common ways of servicing devices are by when the serial port is idle? What if there were 8 similar polling and by using interrupts. Polling means that devices installed in the computer? a status bit on the interface is periodically checked Exercise: Data is being read from a tape drive interface to see whether some additional operation needs to be at 100,000 characters per second. The overhead to ser- performed, for example whether the device has data vice an interrupt and return control to the interrupted pro- ready to be read. A device can also be designed to gram is 20 microseconds. Can this device use an ISR to generate an interrupt when it requires service. This transfer each character? interrupt interrupts normal ¯ow of control and causes It is also possible to use a mixture of interrupt and an interrupt service routine (ISR) to be executed to polled devices. For example, devices can be polled service the device. by an ISR that executes periodically due to a clock Polling must be done suf®ciently fast that data is interrupt. It is also common for devices to buffer not lost. Since each poll requires a certain number of multiple bytes and issue an interrupt only when the operations, this creates a certain minimum overhead buffer is full (or empty). The ISR can then transfer (fraction of available CPU cycles) for servicing each the buffer without an ISR overhead for each byte. device. In addition, these polling routines must be in- In applications where loss of data cannot be tol- tegrated into each program that executes on the pro- erated (e.g. where safety would be affected) the de- cessor. signer must ensure that all of the devices serviced On the other hand, since the ISR is only exe- by interrupts can be properly serviced under worst- cuted once for each interrupt there is no ®xed over- case conditions. Typically this involves a sequence head for servicing interrupt-driven devices. How- of nested interrupts happening closely one after an- ever, responding to an interrupt requires some addi- other in a particular order. In some of these systems tional overhead to save the processor state, fetch the it may be easier to use polling to help ensure correct interrupt number and then the corresponding inter- worst-case behaviour. rupt vector, branch to the ISR and later restore the processor state. In general, it is advantageous to use interrupts 2 Maskable and Non-Maskable In- when the overhead required by polling would con- terrupts sume a large percentage of the CPU time or would complicate the design of the software. It is advanta- Like most other processors, the 8088 has two types geous to use polling when the overhead of servicing of interrupts: non-maskable and maskable. Mask- 1 able interrupts (the INTR pin) can be disabled by 8 plus the particular interrupt signal (e.g. if IR3 clearing the IF bit (¯ag) in the processor status word. was asserted the CPU would read the value 11 Non-maskable interrupts (NMI pin) cannot be dis- from the PIC during the interrupt acknowledge abled. An maskable interrupt causes an interrupt ac- cycle). knowledge cycle which is used to fetch an interrupt type (number) while an NMI always uses the inter- The PIC has two control registers that can be read rupt vector for interrupt type 2. or written. On the IBM PC the address decoder Exercise: Where is the interrupt vector for NMI? for PIC places these two registers in the I/O address space at locations 20H and 21H. Unlike many other microprocessors both INT and 3 The 8259 in the IBM PC Architec- IRx are active-high signals and on the IBM PC the ture IRx inputs are con®gured to be edge-triggered. The interrupt inputs to the PIC are connected as The 8088 CPU only has one interrupt request pin. Al- follows: though simple systems may only have one interrupt interrupt device source, more complex systems must have some way 0 timer of dealing with multiple interrupt sources. The In- 1 keyboard tel ªway of doing thingsº is to use a chip called a 2 reserved programmable interrupt controller (PIC). This chip 3 serial port 2 takes as inputs interrupt request signals from up to 8 4 serial port 1 peripherals and supplies a single INTR signal to the 5 hard disk CPU as shown below: 6 ¯oppy disk 8088 CPU 8259 PIC 7 printer 1 INTR INT Exercise: When the a key on the keyboard is pressed, IR0 which input on the 8259 will be asserted? What will the sig- INTA INTA IR1 nal level be? What value will the 8088 read from the PIC IR2 . during the interrupt acknowledge cycle? What addresses . data bus . will the CPU read to get the starting address of the key- IR7 from peripherals board ISR? address decoder CS On the IBM AT and later models there are more than 8 interrupt sources and there are two PIC. The The PIC has 3 purposes: slave PIC supports an additional 8 interrupt inputs and requests an interrupt from the master PIC as if it 1. It allows each of the individual interrupts to be were an interrupting peripheral on IR2. enabled or disabled (masked). Exercise: What is the maximum number of interrupt sources that could be handled using one master and mul- 2. It prioritizes interrupts so that if multiple inter- tiple slave PICs? rupts happen simultaneously the one with the highest priority is serviced ®rst. The priorities of the interrupts are ®xed, with input IR0 hav- 4 Programming the 8259 Interrupt ing the highest priority and IR7 the lowest. In- Controller terrupts of lower priority not handled while an ISR for a higher-level interrupt is active. The initialization of the PIC is rather complicated be- cause it has many possible operating modes. The 3. It provides an interrupt type (number) that the PIC's operating mode is normally initialized by the CPU reads during the interrupt acknowledge cy- BIOS when the system is booted. We will only con- cle. This tells the CPU which of the 8 possible sider the standard PIC operating used on the IBM PC interrupts occured. The PIC on the IBM PC is and only a system with a single (master) PIC. programmed to respond with an interrupt type of 2 In it's standard mode the PIC operates as follows: process returns from the ISR via the IRET instruc- tion. This means that ISRs can't be interrupted (not If a particular interrupt source is not masked even by a higher-level interrupt) unless interrupts are then a rising edge on that interrupt request line is explicitly re-enabled in the ISR. captured and stored (ªlatchedº). Multiple inter- Interrupt routines should be kept as short as pos- rupt requests can be ªpendingº at a given time. sible to minimize the interrupt latency (see below). Typically this involves having the ISR store values in if not ISR for the same or a higher level is active a buffer or set ¯ags and then having the bulk of the the interrupt signal to the CPU is asserted processing performed outside the ISR. if the CPU's interrupt enable ¯ag is set then an It's possible to allow the CPU to interrupt an ISR interrupt acknowledge cycle will happen and the (resulting in nested interrupts)by setting the interrupt interrupt number for the highest pending inter- enable bit with the STI instruction. rupt is supplied by the PIC to the CPU Exercise: How many levels deep could interrupts be at the end of the ISR a command byte (20H) nested on the IBM PC? In the worst case, how much space must be written to the PIC register at address would be required on the interrupted program's stack to 20H to re-enable interrupts at that level again. hold the values pushed during the interrupt acknowledge This is called the `EOI' (end-of interrupt) com- cycle? mand. Sample 8088/8259 ISR During normal operation only two operations need to be performed on the PIC: The code below shows an 8088 assembly language program that includes an ISR. The program sets up an 1. Disabling (masking) and enabling interrupts ISR for interrupt number 8 (the timer interrupt on the from a particular source.
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