Benchmarking Real-Time Operating Systems for Use in Radio Base Station Applications Master of Science Thesis
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Demystifying the Real-Time Linux Scheduling Latency
Demystifying the Real-Time Linux Scheduling Latency Daniel Bristot de Oliveira Red Hat, Italy [email protected] Daniel Casini Scuola Superiore Sant’Anna, Italy [email protected] Rômulo Silva de Oliveira Universidade Federal de Santa Catarina, Brazil [email protected] Tommaso Cucinotta Scuola Superiore Sant’Anna, Italy [email protected] Abstract Linux has become a viable operating system for many real-time workloads. However, the black-box approach adopted by cyclictest, the tool used to evaluate the main real-time metric of the kernel, the scheduling latency, along with the absence of a theoretically-sound description of the in-kernel behavior, sheds some doubts about Linux meriting the real-time adjective. Aiming at clarifying the PREEMPT_RT Linux scheduling latency, this paper leverages the Thread Synchronization Model of Linux to derive a set of properties and rules defining the Linux kernel behavior from a scheduling perspective. These rules are then leveraged to derive a sound bound to the scheduling latency, considering all the sources of delays occurring in all possible sequences of synchronization events in the kernel. This paper also presents a tracing method, efficient in time and memory overheads, to observe the kernel events needed to define the variables used in the analysis. This results in an easy-to-use tool for deriving reliable scheduling latency bounds that can be used in practice. Finally, an experimental analysis compares the cyclictest and the proposed tool, showing that the proposed method can find sound bounds faster with acceptable overheads. 2012 ACM Subject Classification Computer systems organization → Real-time operating systems Keywords and phrases Real-time operating systems, Linux kernel, PREEMPT_RT, Scheduling latency Digital Object Identifier 10.4230/LIPIcs.ECRTS.2020.9 Supplementary Material ECRTS 2020 Artifact Evaluation approved artifact available at https://doi.org/10.4230/DARTS.6.1.3. -
Interrupt Handling in Linux
Department Informatik Technical Reports / ISSN 2191-5008 Valentin Rothberg Interrupt Handling in Linux Technical Report CS-2015-07 November 2015 Please cite as: Valentin Rothberg, “Interrupt Handling in Linux,” Friedrich-Alexander-Universitat¨ Erlangen-Nurnberg,¨ Dept. of Computer Science, Technical Reports, CS-2015-07, November 2015. Friedrich-Alexander-Universitat¨ Erlangen-Nurnberg¨ Department Informatik Martensstr. 3 · 91058 Erlangen · Germany www.cs.fau.de Interrupt Handling in Linux Valentin Rothberg Distributed Systems and Operating Systems Dept. of Computer Science, University of Erlangen, Germany [email protected] November 8, 2015 An interrupt is an event that alters the sequence of instructions executed by a processor and requires immediate attention. When the processor receives an interrupt signal, it may temporarily switch control to an inter- rupt service routine (ISR) and the suspended process (i.e., the previously running program) will be resumed as soon as the interrupt is being served. The generic term interrupt is oftentimes used synonymously for two terms, interrupts and exceptions [2]. An exception is a synchronous event that occurs when the processor detects an error condition while executing an instruction. Such an error condition may be a devision by zero, a page fault, a protection violation, etc. An interrupt, on the other hand, is an asynchronous event that occurs at random times during execution of a pro- gram in response to a signal from hardware. A proper and timely handling of interrupts is critical to the performance, but also to the security of a computer system. In general, interrupts can be emitted by hardware as well as by software. Software interrupts (e.g., via the INT n instruction of the x86 instruction set architecture (ISA) [5]) are means to change the execution context of a program to a more privileged interrupt context in order to enter the kernel and, in contrast to hardware interrupts, occur synchronously to the currently running program. -
UG1046 Ultrafast Embedded Design Methodology Guide
UltraFast Embedded Design Methodology Guide UG1046 (v2.3) April 20, 2018 Revision History The following table shows the revision history for this document. Date Version Revision 04/20/2018 2.3 • Added a note in the Overview section of Chapter 5. • Replaced BFM terminology with VIP across the user guide. 07/27/2017 2.2 • Vivado IDE updates and minor editorial changes. 04/22/2015 2.1 • Added Embedded Design Methodology Checklist. • Added Accessing Documentation and Training. 03/26/2015 2.0 • Added SDSoC Environment. • Added Related Design Hubs. 10/20/2014 1.1 • Removed outdated information. •In System Level Considerations, added information to the following sections: ° Performance ° Clocking and Reset 10/08/2014 1.0 Initial Release of document. UltraFast Embedded Design Methodology Guide Send Feedback 2 UG1046 (v2.3) April 20, 2018 www.xilinx.com Table of Contents Chapter 1: Introduction Embedded Design Methodology Checklist. 9 Accessing Documentation and Training . 10 Chapter 2: System Level Considerations Performance. 13 Power Consumption . 18 Clocking and Reset. 36 Interrupts . 41 Embedded Device Security . 45 Profiling and Partitioning . 51 Chapter 3: Hardware Design Considerations Configuration and Boot Devices . 63 Memory Interfaces . 69 Peripherals . 76 Designing IP Blocks . 94 Hardware Performance Considerations . 102 Dataflow . 108 PL Clocking Methodology . 112 ACP and Cache Coherency. 116 PL High-Performance Port Access. 120 System Management Hardware Assistance. 124 Managing Hardware Reconfiguration . 127 GPs and Direct PL Access from APU . 133 Chapter 4: Software Design Considerations Processor Configuration . 137 OS and RTOS Choices . 142 Libraries and Middleware . 152 Boot Loaders . 156 Software Development Tools . 162 UltraFast Embedded Design Methodology GuideSend Feedback 3 UG1046 (v2.3) April 20, 2018 www.xilinx.com Chapter 5: Hardware Design Flow Overview . -
Microkernel Mechanisms for Improving the Trustworthiness of Commodity Hardware
Microkernel Mechanisms for Improving the Trustworthiness of Commodity Hardware Yanyan Shen Submitted in fulfilment of the requirements for the degree of Doctor of Philosophy School of Computer Science and Engineering Faculty of Engineering March 2019 Thesis/Dissertation Sheet Surname/Family Name : Shen Given Name/s : Yanyan Abbreviation for degree as give in the University calendar : PhD Faculty : Faculty of Engineering School : School of Computer Science and Engineering Microkernel Mechanisms for Improving the Trustworthiness of Commodity Thesis Title : Hardware Abstract 350 words maximum: (PLEASE TYPE) The thesis presents microkernel-based software-implemented mechanisms for improving the trustworthiness of computer systems based on commercial off-the-shelf (COTS) hardware that can malfunction when the hardware is impacted by transient hardware faults. The hardware anomalies, if undetected, can cause data corruptions, system crashes, and security vulnerabilities, significantly undermining system dependability. Specifically, we adopt the single event upset (SEU) fault model and address transient CPU or memory faults. We take advantage of the functional correctness and isolation guarantee provided by the formally verified seL4 microkernel and hardware redundancy provided by multicore processors, design the redundant co-execution (RCoE) architecture that replicates a whole software system (including the microkernel) onto different CPU cores, and implement two variants, loosely-coupled redundant co-execution (LC-RCoE) and closely-coupled redundant co-execution (CC-RCoE), for the ARM and x86 architectures. RCoE treats each replica of the software system as a state machine and ensures that the replicas start from the same initial state, observe consistent inputs, perform equivalent state transitions, and thus produce consistent outputs during error-free executions. -
Process Scheduling Ii
PROCESS SCHEDULING II CS124 – Operating Systems Spring 2021, Lecture 12 2 Real-Time Systems • Increasingly common to have systems with real-time scheduling requirements • Real-time systems are driven by specific events • Often a periodic hardware timer interrupt • Can also be other events, e.g. detecting a wheel slipping, or an optical sensor triggering, or a proximity sensor reaching a threshold • Event latency is the amount of time between an event occurring, and when it is actually serviced • Usually, real-time systems must keep event latency below a minimum required threshold • e.g. antilock braking system has 3-5 ms to respond to wheel-slide • The real-time system must try to meet its deadlines, regardless of system load • Of course, may not always be possible… 3 Real-Time Systems (2) • Hard real-time systems require tasks to be serviced before their deadlines, otherwise the system has failed • e.g. robotic assembly lines, antilock braking systems • Soft real-time systems do not guarantee tasks will be serviced before their deadlines • Typically only guarantee that real-time tasks will be higher priority than other non-real-time tasks • e.g. media players • Within the operating system, two latencies affect the event latency of the system’s response: • Interrupt latency is the time between an interrupt occurring, and the interrupt service routine beginning to execute • Dispatch latency is the time the scheduler dispatcher takes to switch from one process to another 4 Interrupt Latency • Interrupt latency in context: Interrupt! Task -
Efficient Interrupts on Cortex-M Microcontrollers
Efficient Interrupts on Cortex-M Microcontrollers Chris Shore Training Manager ARM Ltd Cambridge, UK [email protected] Abstract—The design of real-time embedded systems involves So, assuming that we have a system which is powerful a constant trade-off between meeting real-time design goals and enough to meet all its real-time design constraints, we have a operating within power and energy budgets. This paper explores secondary problem. how the architectural features of ARM® Cortex®-M microcontrollers can be used to maximize power efficiency while That problem is making the system as efficient as possible. ensuring that real-time goals are met. If we have sufficient processing power, it is relatively trivial to conceive and implement a design which meets all time-related Keywords—interrupts; microcontroller; real-time; power goals but such a system might be extremely inefficient when it efficiency. comes to energy consumption. The requirement to minimize energy consumption introduces another set of goals and I. INTRODUCTION constraints. It requires us to make use of sleep modes and low A “real-time” system is one which has to react to external power modes in the hardware, to use the most efficient events within certain time constraints. Wikipedia says: methods for switching from one event to another and to maximize “idle time” in the design to make opportunities to “A system is real-time if the total correctness on an use low power modes. operation depends not only on its logical correctness but also upon the time in which it is performed.” The battle is between meeting the time constraints while using the least amount of energy in doing so. -
OPERATING SYSTEMS.Ai
Introduction Aeroflex Gaisler provides LEON and ERC32 users with a wide range of popular embedded operating systems. Ranging from very small footprint task handlers to full featured Real-Time Operating System (RTOS). A summary of available operating systems and their characteristics is outlined below. VxWorks The VxWorks SPARC port supports LEON3/4 and LEON2. Drivers for standard on-chip peripherals are included. The port supports both non-MMU and MMU systems allowing users to program fast and secure applications. Along with the graphical Eclipse based workbench comes the extensive VxWorks documentation. • MMU and non-MMU system support • SMP support (in 6.7 and later) • Networking support (Ethernet 10/100/1000) • UART, Timer, and interrupt controller support • PCI, SpaceWire, CAN, MIL-STD-1553B, I2C and USB host controller support • Eclipse based Workbench • Commercial license ThreadX The ThreadX SPARC port supports LEON3/4 and its standard on-chip peripherals. ThreadX is an easy to learn and understand advanced pico-kernel real-time operating system designed specifically for deeply embedded applications. ThreadX has a rich set of system services for memory allocation and threading. • Non-MMU system support • Bundled with newlib C library • Support for NetX, and USBX ® • Very small footprint • Commercial license Nucleus Nucleus is a real time operating system which offers a rich set of features in a scalable and configurable manner. • UART, Timer, Interrupt controller, Ethernet (10/100/1000) • TCP offloading and zero copy TCP/IP stack (using GRETH GBIT MAC) • USB 2.0 host controller and function controller driver • Small footprint • Commercial license LynxOS LynxOS is an advanced RTOS suitable for high reliability environments. -
Thread Verification Vs. Interrupt Verification
Thread Verification vs. Interrupt Verification John Regehr School of Computing University of Utah ABSTRACT to verifiers for thread-based programs that per- Interrupts are superficially similar to threads, but there are mit them to also check interrupt-based programs. subtle semantic differences between the two abstractions. A secondary goal is to exploit the semantics of This paper compares and contrasts threads and interrupts interrupts to make checking faster and more pre- from the point of view of verifying the absence of race con- cise. ditions. We identify a small set of extensions that permit Of course, threads come in many flavors. In this paper thread verification tools to also verify interrupt-driven soft- we’ll assume POSIX-style threads [5]: preemptively sched- ware, and we present examples of source-to-source trans- uled blocking threads, scheduled either in the kernel or at formations that turn interrupt-driven code into semanti- user level. cally equivalent thread-based code that can be checked by a thread verifier. 2. THREADS AND INTERRUPTS 1. INTRODUCTION The following are some significant ways in which threads For programs running on general-purpose operating sys- differ from interrupts. tems on PC-class hardware, threads are probably the most important abstraction supporting concurrent programming. Blocking. Interrupt cannot block: they run to completion On the other hand, interrupts are the dominant method for unless preempted by other interrupts. The inability to block expressing concurrency in embedded systems, particularly is very inconvenient, and it is one of the main reasons that those based on small microcontroller units (MCUs). All complex logic should not be implemented in interrupt code. -
Real-Time Operating System Modelling and Simulation Using Systemc
Real-Time Operating System Modelling and Simulation Using SystemC Ke Yu Submitted for the degree of Doctor of Philosophy Department of Computer Science June 2010 Abstract Increasing system complexity and stringent time-to-market pressure bring chal- lenges to the design productivity of real-time embedded systems. Various System- Level Design (SLD), System-Level Design Languages (SLDL) and Transaction- Level Modelling (TLM) approaches have been proposed as enabling tools for real-time embedded system specification, simulation, implementation and verifi- cation. SLDL-based Real-Time Operating System (RTOS) modelling and simula- tion are key methods to understand dynamic scheduling and timing issues in real- time software behavioural simulation during SLD. However, current SLDL-based RTOS simulation approaches do not support real-time software simulation ade- quately in terms of both functionality and accuracy, e.g., simplistic RTOS func- tionality or annotation-dependent software time advance. This thesis is concerned with SystemC-based behavioural modelling and simu- lation of real-time embedded software, focusing upon RTOSs. The RTOS-centric simulation approach can support flexible, fast and accurate real-time software tim- ing and functional simulation. They can help software designers to undertake real- time software prototyping at early design phases. The contributions in this thesis are fourfold. Firstly, we propose a mixed timing real-time software modelling and simula- tion approach with various timing related techniques, which are suitable for early software modelling and simulation. We show that this approach not only avoids the accuracy drawback in some existing methods but also maintains a high simu- lation performance. Secondly, we propose a Live CPU Model to assist software behavioural timing modelling and simulation. -
Simulation and Comparison of Various Scheduling Algorithm for Improving the Interrupt Latency of Real –Time Kernal
Journal of Computer Science and Applications. ISSN 2231-1270 Volume 6, Number 2 (2014), pp. 115-123 © International Research Publication House http://www.irphouse.com Simulation And Comparison of Various Scheduling Algorithm For Improving The Interrupt Latency of Real –Time Kernal 1.Lavanya Dhanesh 2.Dr.P.Murugesan 1.Research Scholar, Sathyabama University, Chennai, India. 2.Professor, S.A. Engineering College, Chennai, India. Email:1. [email protected] Abstract The main objective of the research is to improve the performance of the Real- time Interrupt Latency using Pre-emptive task Scheduling Algorithm. Interrupt Latency provides an important metric in increasing the performance of the Real Time Kernal So far the research has been investigated with respect to real-time latency reduction to improve the task switching as well the performance of the CPU. Based on the literature survey, the pre-emptive task scheduling plays an vital role in increasing the performance of the interrupt latency. A general disadvantage of the non-preemptive discipline is that it introduces additional blocking time in higher priority tasks, so reducing schedulability . If the interrupt latency is increased the task switching delay shall be increasing with respect to each task. Hence most of the research work has been focussed to reduce interrupt latency by many methods. The key area identified is, we cannot control the hardware interrupt delay but we can improve the Interrupt service as quick as possible by reducing the no of preemptions. Based on this idea, so many researches has been involved to optimize the pre-emptive scheduling scheme to reduce the real-time interrupt latency. -
Debugging Threadx RTOS Applications Using Tracex Contents
Application Note Renesas Synergy™ Platform R20AN0404EJ0112 Debugging ThreadX RTOS Applications Rev.1.12 Using TraceX Sep 10, 2018 ThreadX® is an RTOS from Express Logic which is based on a high-performance embedded kernel. This application note provides procedures to check ThreadX thread and object states (referred to as resources) during the development of applications in e2 studio for Renesas Synergy™. The procedure for starting TraceX® is also explained. For the ThreadX specifications and functions, visit the Express Logic (http://rtos.com/) website. For TraceX specifications and functions, visit the Synergy Software (https://www.renesas.com/us/en/products/synergy.html) page. Under the Development Tools tab, select TraceX. This application note explains examples using a project called Blinky with ThreadX that is available after installing the Renesas Synergy™ Software Package (SSP). For procedures covering operations with Blinky with ThreadX, see the Renesas Synergy™ e2 studio v6.2 or Greater Getting Started Guide available on the Synergy Solutions Gallery (https://www.renesas.com/us/en/products/synergy/gallery.html). This document describes general usage of e2 studio. This application note supports SSP version 1.4.0 and later and e2 studio version 6.2.0 and later. Target Environment The operations covered in this document were confirmed in the following environment. • Renesas SynergyTM Software Package (SSP) v1.4.0 or later • e2 studio for Renesas Synergy™ v6.2.0 or later • ThreadX (requires development/production license, see section 5.1, Licenses for ThreadX) • Development Kit for DK-S7G2 Synergy MCU Group R20AN0404EJ0112 Rev.1.12 Page 1 of 23 Sep 10, 2018 Renesas Synergy™ Platform Debugging ThreadX RTOS Applications Using TraceX Contents 1. -
Integrated Task and Interrupt Management for Real-Time Systems
Integrated Task and Interrupt Management for Real-Time Systems LUIS E. LEYVA-DEL-FOYO, Universidad Aut´onoma Metropolitana—Unidad Cuajimalpa PEDRO MEJIA-ALVAREZ, CINVESTAV-IPN DIONISIO DE NIZ, Carnegie Mellon University Real-time scheduling algorithms like RMA or EDF and their corresponding schedulability test have proven to be powerful tools for developing predictable real-time systems. However, the traditional interrupt man- agement model presents multiple inconsistencies that break the assumptions of many of the real-time scheduling tests, diminishing its utility. In this article, we analyze these inconsistencies and present a model that resolves them by integrating interrupts and tasks in a single scheduling model. We then use the RMA theory to calculate the cost of the model and analyze the circumstances under which it can provide the most value. This model was implemented in a kernel module. The portability of the design of our module is discussed in terms of its independence from both the hardware and the kernel. We also discuss the imple- mentation issues of the model over conventional PC hardware, along with its cost and novel optimizations for reducing the overhead. Finally, we present our experimental evaluation to show evidence of its temporal determinism and overhead. Categories and Subject Descriptors: D.4.7 [Operating Systems]: Organization and Design—Real-time systems and embedded systems; D.4.1 [Operating Systems]: Process Management—Scheduling, threads; D.4.4 [Operating Systems]: Communications Management—Input/output; D.4.8 [Operating Systems]: Performance—Modeling and prediction General Terms: Algorithms, Design, Experimentation, Performance Additional Key Words and Phrases: Predictability, interrupt scheduling, programmable interrupt controller ACM Reference Format: Leyva-del-Foyo, L.