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Providing Bi-Directional, Analog, and Differential Signal Transmission Capability to an Electronic Prototyping Platform

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Providing Bi-Directional, Analog, and Differential Signal Transmission Capability to an Electronic Prototyping Platform UNIVERSITÉ DE MONTRÉAL PROVIDING BI-DIRECTIONAL, ANALOG, AND DIFFERENTIAL SIGNAL TRANSMISSION CAPABILITY TO AN ELECTRONIC PROTOTYPING PLATFORM WASIM HUSSAIN DÉPARTEMENT DE GÉNIE ÉLECTRIQUE ÉCOLE POLYTECHNIQUE DE MONTRÉAL THÈSE PRÉSENTÉE EN VUE DE L’OBTENTION DU DIPLÔME DE PHILOSOPHIAE DOCTOR (GÉNIE ÉLECTRIQUE) DÉCEMBRE 2015 © Wasim Hussain, 2015. UNIVERSITÉ DE MONTRÉAL ÉCOLE POLYTECHNIQUE DE MONTRÉAL Cette thèse intitulée : PROVIDING BI-DIRECTIONAL, ANALOG, AND DIFFERENTIAL SIGNAL TRANSMISSION CAPABILITY TO AN ELECTRONIC PROTOTYPING PLATFORM présentée par : HUSSAIN Wasim en vue de l’obtention du diplôme de : Philosophiae Doctor a été dûment acceptée par le jury d’examen constitué de : M. SAWAN Mohamad, Ph. D., président M. SAVARIA Yvon, Ph. D., membre et directeur de recherche M. BLAQUIÈRE Yves, Ph. D., membre et codirecteur de recherche M. AUDET Yves, Ph. D., membre M. NABKI Frédéric, Ph. D., membre externe iii DEDICATION To my beloved parents. iv ACKNOWLEDGEMENTS I would like to express my deepest gratitude to my supervisor Professor Yvon Savaria and Professor Yves Blaquière for their insightful guidance and constant support throughout this research. I feel extremely privileged to have been able to work under their supervision. They provided me with a healthy research environment with full freedom to develop my work as well as adequate supervision to lead me in the right direction. I am indebted to them. I would like to express my deep gratitude to Gestion Technocap, the Natural Sciences and Engineering Reseach Council of Canada and the Mitacs program for supporting my research. I am grateful to CMC Microsystems for the products and services that facilitated this research (CAD tools by Cadence, fabrication services using 0.13 µm CMOS technology from IBM, and packaging services). I am grateful to Omar Al Terkawi for his help in CAD tools and laying out the test chip. I thank Bryan Tremblant for helping me with the PCB. I thank Rejean Lepage for keeping the lab computers up and running all times, particularly before tape-out deadlines. Special thanks to Marie Yannick Laplante of the Electrical Engineering Department for being so friendly and supportive, even with last minute requests. It has been a great pleasure for me to be a part of the Groupe de Recherche en Microèlectronique et Microsystèmes (GRM). Last but surely not least, I am grateful to my family for their endless care and support throughout the long path of my academic endeavour. v RÉSUMÉ Les réseaux d’interconnexions programmables (FPIN) se retrouvent largement utilisés dans plusieurs structures bien connues telles que les FPGA, les plateformes de prototypages ainsi que dans plusieurs architectures de réseaux intégrés. Le but de la présente thèse est d’amé- liorer la structure actuelle des FPIN ainsi que les plateformes de prototypages se basant sur cette technologie afin d’y intégrer d’autres fonctionnalités telles que des interfaces pour les signaux bidirectionnels de type drain-ouvert, les signaux analogiques ou bien les signaux différentiels. Cette thèse présente trois différents circuits qui ont été implémentés dans cette optique. Les interconnexions de ces trois circuits peuvent être reconfigurées pour supporter une interface de type bidirectionnelle drain-ouvert, de type analogique ou différentielle, le tout au travers un réseau d’interconnexions configurable numérique unidirectionnel, ou FPIN. Le besoin d’une telle interface fut tout d’abord envisagé dans le contexte du WaferBoard, qui consiste en une plateforme reconfigurable de prototypage pour les systèmes électroniques. Le cœur de ce WaferBoard consiste en un circuit intégré à l’échelle d’une tranche entière de silicium, qui est constitué d’une matrice bidimensionnelle de cellules. Une large partie de la surface disponible s’en retrouve déjà utilisée par des plots configurables (CIO), l’aiguillage des multiplexeurs du FPIN, des registres dédiés à la chaine JTAG et d’autres circuiteries de contrôle. De ce fait, il en devient primordial que les interfaces bidirectionnelle drain-ouvert, analogique et différentielle soit les plus compactes possibles. Puisque ces circuits d’interfaces seront dédiés pour une plateforme utilisant une tranche de silicium (wafer-scale), l’architec- ture de ces derniers doit être robuste en regard des variations de procédé, de la température ainsi que de l’alimentation. La première contribution de cette thèse est l’élaboration et la conception d’une interface de type drain-ouvert ainsi que de son support d’interconnexion bidirectionnel utilisant un réseau numérique unidirectionnel à signalisation asymétrique (à l’opposé de la signalisation différentielle) FPIN. L’interface proposée peut interconnecter plusieurs nœuds d’un FPIN. À l’aide de cette interface, le réseau d’interconnexions peut imiter le comportement et le fonctionnement d’un bus de type drain-ouvert (ou collecteur-ouvert) (tel qu’utilisé par le protocole I2C). De ce fait, plusieurs plots de type drain-ouvert provenant d’une multitude de circuits-intégrés (ICs) différents peuvent y être connectés au travers le FPIN à l’aide de l’interface proposée. Cette interface a été fabriquée en technologie CMOS 0.13 µm et occupe une surface de 65 µm × 22 µm par plot. Les résultats expérimentaux démontrent que plusieurs instances de cette interface peuvent être interconnectées entre eux en utilisant l’architecture d’interconnexions proposée. Cette architecture combinant six plots de type drain-ouvert a été vi testée. Les délais de propagation sur cette interconnexion sont approximés par 0.26·n+51 ns et 0.26·n+94 ns pour les fronts montants et descendants lorsque chaque plot a une charge capacitive de 15 pF à sa sortie, où n est le nombre d’interfaces connectées. Ces délais, combinés au délai de propagation du FPIN, sont les facteurs limitant le nombre maximal d’interfaces pouvant y être connectées simultanément pour une vitesse de communication donnée. À titre d’exemple, le prototype d’interface peut supporter plus de 20 unités de type I2C Mode Rapide Plus (3.4 Mbit/s). La deuxième contribution de cette thèse de doctorat décrit une interface analogique qui comprend un convertisseur analogique/numérique (A/N) (transmetteur) et un convertisseur numérique/analogique (NA) (récepteur) afin de permettre la propagation d’un signal ana- logique au travers une plateforme de prototypage de type FPIN. Le circuit intégré (uIC) transmetteur fournit le signal au convertisseur A/N. Ce dernier convertit le dit signal dans le domaine numérique pouvant se propager dans la plateforme FPIN jusqu’au récepteur. Un convertisseur N/A se situant du côté de la réception effectue la conversion afin de repro- duire le signal analogique original pour le transmettre à l’uIC de destination. Cependant, les contraintes de surface de silicium de la plateforme de prototypage visée étant extrêmes, une conception très compacte fut requise pour les deux types de convertisseurs. Les convertisseurs de type sur-échantillonnage ne peuvent être utilisés dû aux performances exigées par ce type de convertisseurs pour les composantes analogiques (i.e. amplificateurs, comparateurs, résis- tances, sources de courant ou capacités) en plus du filtrage numérique requérant une surface de silicium relativement grande. La seconde contribution de cette thèse se situe donc dans l’élaboration et le développement d’un circuit très compact utilisant une version asynchrone d’un modulateur de type D (asynchonous D modulator - ADM) pour effectuer la conversion du domaine analogique vers le numérique. Ce convertisseur est proposé comme un moyen de transmettre un signal analogique à l’aide d’un réseau numérique d’interconnexions. Une analyse détaillée du mécanisme de conversion A/N du circuit ADM est également présentée dans cette thèse. Une méthode d’analyse graphique a été utilisée pour évaluer la fréquence d’oscillation de l’ADM afin de paramétrer le dit circuit. L’équivalence du spectre fréquentiel du signal d’entrée modulé ainsi que le spectre basse fréquence de la sortie de l’ADM, obtenu en utilisant un simple filtre de type passe-bas, peut être utilisé en guise de convertisseur N/A pour effectuer la reconstruction du signal analogique d’entrée. Le circuit ADM a été fabriqué dans une technologie CMOS 0.13 µm. Les mesures effectuées sur le circuit montrent des SNR et SNDR de 57 et 47 dB respectivement pour une bande passante de 2 MHz. L’ADM occupe une surface active de silicium de 45 µm × 22 µm. L’ensemble des convertisseurs A/N et N/A demande un courant total de 0.15 mA avec une alimentation de 3.3V pour une surface totale de 45 µm × 46 µm. Lorsque comparé avec des convertisseurs A/N similaires, le circuit ADM vii peut supporter des signaux de bande passante modérée pour une résolution moyenne mais occupe une surface de silicium très réduite. Une interface différentielle de reconfiguration spatiale a également été développée pour sup- porter la logique dite en mode courant (CML) pour la transmission de signaux au travers un réseau numérique unidirectionnel à signalisation asymétrique d’une plateforme de type FPIN (WaferBoard). Cette interface a été développée en collaboration avec Oliver Valorge, un stagiaire postdoctoral de l’École Polytechnique de Montréal. Deux types d’étages d’entrée pour l’interface différentielle ont été investiguées. Le premier type est basé sur un tampon de gain unitaire utilisant des multiplexeurs et a été entièrement développé et élaboré par Olivier Valorge. L’étage d’entrée de ce premier circuit occupe une surface de silicium relativement grande, c’est pourquoi une seconde alternative a été développée et élaborée par l’auteur de cette thèse afin de réduire le coût en surface de l’étage d’entrée. Cette thèse de doctorat comporte donc une troisième contribution en lien avec le développement d’un étage d’entrée différentiel basé sur des multiplexeurs à transistors passifs. Cet étage a été dessiné pour une technologie CMOS 0.13 µm et des validations après le dessin des masques ont été effectuées pour établir la faisabilité du concept.
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