An Efficient Power Consumption of VITERBI Decoder for TCM System D
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ISSN 2319-8885 Vol.05,Issue.28 September-2016, Pages:5991-6002 www.ijsetr.com An Efficient Power Consumption of VITERBI Decoder for TCM System D. KEERTHY1, R. ASHOK KUMAR2 1PG Scholar, Dept of ECE(VLSI), Ananthalakshmi Institute of Technology and Sciences, Anantapur, AP, India, E-mail: [email protected]. 2Assistant Professor, Dept of ECE, Ananthalakshmi Institute of Technology and Sciences, Anantapur, AP, India. Abstract: High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of trellis coded modulation decoders. We propose a pre-computation architecture incorporated with T-algorithm for Viterbi decoder, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 Convolutional code used in a TCM system shows that compared with the full trellis VD, the pre-computation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible. Now-a-days we have lots of troubles with the channels for transmission, due to strong noise and interference while transmission. So we are here using some efficient “Viterbi Decoding Technique” for correcting the corrupted signal while transmission. The main objective of the project is that to correct the corrupted signal in communication channel due to strong noise and interference. For any digital communication channel it can be applied, the transmitted data is presented in binary form that is modulated to analog waveforms and transmitted through a channel to a receiver. In the channel the noise and interference corrupt the transmitted signal, which is mapped back to binary bits in the receiver. Some bit errors may occur if the interference is too strong so channel coding is often used to prevent these errors. The channel coding occurs in High-speed, low-power design of Viterbi Decoders for Trellis Coded Modulation (TCM) systems without performance loss, while the degradation in clock speed is negligible. There are many different methods for channel coding like linear block codes and convolution codes, where block codes are better suited for error detection and Convolutional codes are mainly used for error correction. But in this project we are going to correct the corrupted signal at the decoder, which was generated from the encoder due to strong interference in communication channel in order to get the actual signals using Verilog. So that the codes for the encoder are considered to be conventional this generates the input signals to the decoder. In this the decoder is designed by using the “Viterbi Algorithm” for getting the actual transmitted signals at the output. Keywords: TCM, Viterbi Decoding Technique. I. INTRODUCTION split up into Front-end design using HDLs, Verification, The expansion of VLSI is „Very Large Scale Integration‟. and Back-end Design or Physical Design. Front-end includes It is the process of designing, verifying, fabricating and design specification, architectural description, logic design, testing of a VLSI IC .A VLSI chip is an IC, which has verification, synthesis. Back-end includes Floor planning, transistors in excess of 40,000. The active devices used for placement,clock tree synthesis, routing, physical verification, fabricating an IC are CMOS FETs. Producing a VLSI chip is GDS II generation. an extremely complex task. It has number of design and verification steps. A design team comprising hundreds of In integrated circuit design, physical design is a step in engineers, scientists and technicians has to work on a modern the standard design cycle which follows after the circuit VLSI project. It is important that each member of the team design. At this step, circuit representations of the components has clear understanding of his or her part of the contribution (devices and interconnects) of the design are converted into for the design. This is accomplished by means of the design geometric representations of shapes which, when hierarchy. Any complex digital system may be broken down manufactured in the corresponding layers of materials, will into gates and memory elements by successively subdividing ensure the required functioning of the components. This the system in a hierarchical manner. Highly automated and geometric representation is called integrated circuit layout. sophisticated tools are commercially available to achieve this This step is usually split into several sub-steps, which include decomposition. Each design domain may be specified at a both design and verification and validation of the layout. various levels of abstraction such as circuit, logic and Modern day Integrated Circuit (IC) design is split up architectural. Modern day Integrated Circuit (IC) design is into Front-end design using HDLs, Verification, and Back- Copyright @ 2016 IJSETR. All rights reserved. D. KEERTHY, R. ASHOK KUMAR end Design or Physical Design. The next step after Physical Design is the Manufacturing process or Fabrication Process that is done in the Wafer Fabrication Houses. Fab-houses fabricate designs onto silicon dies which are then packaged into ICs. Each of the phases mentioned above have Design Flows associated with them. These Design Flows lay down the process and guide-lines/framework for that phase. Physical Design flow uses the technology libraries that are provided by the fabrication houses. These technology files provide information regarding the type of Silicon wafer used, the standard-cells used, the layout rules (like DRC in VLSI), etc. Fig.1. Convolutional Encoder. T-algorithm has been shown to be very efficient in The stream of information bits flows in to the shift reducing the power consumption. However, searching for register from one end and is shifted out at the other end. The the optimal PM in the feedback loop still reduces the location of stages as well as the number of memory elements decoding speed. To overcome this drawback, two variations determines the minimum hamming distance. Minimum of the T-algorithm have been proposed: the relaxed adaptive Hamming distance determines the maximal number of VD, which suggests using an estimated optimal PM, instead correctable bits. Interconnection functions for different rates of finding the real one each cycle and the limited-search and different number of memory elements and their parallel state VD based on scarce state transition. In our minimum hamming distances are available. preliminary work, we have shown that when applied to high- rate Convolutional codes, the relaxed adaptive VD suffers a severe degradation of bit-error-rate performance due to the inherent drifting error between the estimated optimal PM and the accurate one. In this work, we further analyze the pre- computation algorithm. A systematic way to determine the optimal pre-computation steps is presented, where the minimum number of steps for the critical path to achieve the theoretical iteration bound is calculated and the computational complexity overhead due to pre-computation is evaluated. Then, we discuss a complete low-power high- speed VD design for the rate-3/4 Convolutional code. Finally ASIC implementation results of the VD are reported, which have not been obtained in our previous work. II. CONVOLUTIONAL ENCODER A. Convolutional Coding Fig.2.State Diagram for the Convolutional Encoder. Convolutional coding has been used in communication systems including deep space communications and wireless The operation of a Convolutional encoder can be easily communications. Convolutional codes offer an alternative to understood with the aid of a state diagram. The state diagram block codes for transmission over a noisy channel. is a graph of the possible states of the encoder and the Convolutional coding can be applied to a continuous input transitions from one state to another state. Fig.2 represents stream (which cannot be done with block codes), as well as the state diagram of the encoder shown in .1. Fig.2 depicts blocks of data. A Convolutional encoder is a Mealy machine, state transitions and the corresponding encoded outputs. As where the output is a function of the current state and the there are two memory-elements in the circuit, there are four current input. It consists of one or more shift registers and possible states that the circuit can assume. These four states multiple XOR gates. XOR gates are connected to some are represented as S0 through S3. Each state‟s information stages of the shift registers as well as to the current input to (i.e. the contents of flip-flops for the state) along with an generate the output. The encoder in Fig.1 produces two bits input generates an encoded output code. For each state, there of encoded information for each bit of input information, so it can be two outgoing transitions; one corresponding to a „0‟ is called a rate 1/2 encoder. A Convolutional encoder is input bit and the other corresponding to a „1‟ input. generally characterized in (n, k, m) format with a rate of k/n, B. 64-Bit Convolutional Encoder Calculations where We have concluded that two-step pre-computation is the N is number of outputs of the encoder optimal choice for the rate-3/4 code VD. For convenience of K is number of inputs of the encoder discussion, we define the left-most register in Fig.3 as the M is number of flip-flops of the longest shift register of most-significant-bit (MSB) and the right-most register as the the encoder least-significant-bit (LSB). International Journal of Scientific Engineering and Technology Research Volume.05, IssueNo.28, September-2016, Pages: 5991-6002 An Efficient Power Consumption of VITERBI Decoder for TCM System scheme which allows highly efficient transmission of information over band-limited channels such as telephone lines.