BDD Based Synthesis Flow for Design of DPA Resistant Cryptographic Circuits
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BDD Based Synthesis Flow for Design of DPA Resistant Cryptographic Circuits A thesis submitted to the Division of Research and Advanced Studies University of Cincinnati In partial fulfillment of the requirements for the degree of Master of Science in the School of Electronics and Computing Systems of the College of Engineering and Applied Science University of Cincinnati February 2012 By Manoj Chakkaravarathy B.E. (Hons) Electrical and Electronics Engineering BITS, Pilani, India May 2008 Thesis Advisor and Committee Chair: Dr. Ranga Vemuri Abstract The revolution brought by the advancement in Integrated Circuits (IC) technology has resulted in an exponential increase in the use of smartcards and other cryptographic devices for several security-centric applications like digital signatures, identification and secure communication. This growing dependency on electronic devices for critical applications has led to increased sophistication of hardware attacks on ICs, resulting in the need for effective hardware implementation of cryptographic algorithms. Cryptographic algorithms, in spite of being mathematically secure, lose their potency when implemented in hardware due to data leakage at the hardware level through channels like power consumption, timing delay and Electromagnetic emanation. Attacks based on such leakage channels are commonly referred to as Side Channel Attacks (SCA). Differential Power Analysis (DPA) is a sophisticated SCA method that breaks a cryptographic circuit by correlating the power consumption and the applied inputs. DPA based attacks exploit a fundamental weakness in current ASIC design methodologies (SCMOS), where the power consumption is dependent on the applied inputs. Several countermeasures have been proposed at the circuit level to prevent DPA attacks. Secure Differential Multiplexer based Logic using Pass Transistors (SDMLp) is one such countermeasure designed at Digital Design and Environments Lab at University of Cincinnati. In this thesis, we propose a Synthesis Flow for DPA resistant circuits using Binary Decision Diagrams for the SDMLp logic style. Using the proposed design flow, we achieve an average area reduction of 35% and power saving of 30% albeit with a delay penalty of 20% compared to existing secure libraries. We also show that the maximum instantaneous current variance (security metric) is 40 times better for the proposed synthesis flow than existing synthesis techniques for other secure libraries (WDDL). To my dearest Parents Acknowledgments I would sincerely like to thank Prof. Ranga Vemuri for his guidance and support throughout my research work. It has been a great learning curve working with him and a memorable ride over the past couple of years. Thank you, Sir for giving me the opportunity to work at DDEL. I would also like to thank Prof. Wen Ben Jone and Prof. Carla Purdy for agreeing to be on my thesis committee. I would like to thank all DDEL members especially Mike Borowczak who has been a great mentor over the course of my research work. Thank you, Mike. The discussions with Lakshmi and Arun have been very helpful and informative for my research work. Wishing you guys continued success. UC wouldn‟t have been memorable without my excellent roommates, Karthi, Madhan, Rathna, KP and Vignesh. It‟s been a great ride together and wish you guys the best of luck in all your endeavors. And Sindhu. A constant source of strength, support and inspiration to me, without whom this wouldn‟t have materialized. Thanks a ton, Sindhu. Je t‟aime. I would like to thank my parents for giving me their unwavering support and freedom to pursue my interests ever since my childhood. I would like to dedicate this work to them. Table of Contents 1. Introduction ..................................................................................................................................3 1.1 Security of Embedded Devices ..................................................................................................... 4 1.2 Types of Cryptography Attacks ..................................................................................................... 5 1.3 Side Channel Attacks .................................................................................................................... 6 1.4 Existing DPA Countermeasures ................................................................................................... 10 1.5 Thesis Proposal .......................................................................................................................... 12 1.6 Thesis Outline ............................................................................................................................ 13 2. SDMLp – An Overview ................................................................................................................. 14 2.1 Dynamic and Differential Logic (DDL) ......................................................................................... 15 2.2 Existing DDL Methodologies ....................................................................................................... 17 2.3 Secure Differential Multiplexer based Logic using Pass Transistors (SDMLp) ............................... 19 2.4 Experimental Analysis - Cell Level Performance .......................................................................... 22 2.5 Chapter Summary ...................................................................................................................... 24 3. Binary Decision Diagram (BDD) Based Synthesis ........................................................................... 25 3.1 Introduction to Binary Decision Diagrams ................................................................................... 25 3.2 Impact of Variable Order ............................................................................................................ 27 3.3 Mapping SDMLp to BDD ............................................................................................................. 29 3.4 Complementary Nodes Optimization ......................................................................................... 32 3.5 Impact of BDDs on SDML based designs ..................................................................................... 34 3.6 Chapter Summary ...................................................................................................................... 36 4. Proposed Synthesis Flow for SDMLp ............................................................................................ 37 4.1 Motivation ................................................................................................................................. 37 4.2 Related Work ............................................................................................................................. 38 4.3 Proposed Synthesis Flow ............................................................................................................ 39 4.3.1 Variable Order Generator (VOG) ....................................................................................... 40 4.3.2 BDD Reduction Unit (BRU) ................................................................................................ 42 4.4 Chapter Summary ...................................................................................................................... 45 5. Experimental Results and Analysis ............................................................................................... 46 1 5.1 Experimental Platform ............................................................................................................... 46 5.2 Circuitry for Handling Differential Signals ................................................................................... 47 5.3 Design Verification Setup ........................................................................................................... 49 5.4 Performance Evaluation of SDMLp using Proposed Flow ............................................................ 50 5.4.1 Data Encryption Standard (DES) ........................................................................................ 50 5.4.2 DES S-boxes Design ........................................................................................................... 52 5.4.3 DES Hardware Design........................................................................................................ 55 5.4.4 Advanced Encryption Standard (AES) ................................................................................ 57 5.4.5 AES S-boxes Design ........................................................................................................... 58 5.4.6 AES Hardware Design ........................................................................................................ 59 5.6 Security Evaluation of Proposed Flow ......................................................................................... 61 5.6.1 Maximum Instantaneous Current Variance ....................................................................... 61 5.6.2 DPA Attack on DES ............................................................................................................ 62 5.7 Conclusion and Analysis ............................................................................................................. 67 6. Future Work and Conclusion ........................................................................................................ 68 6.1 Future Work ..............................................................................................................................