An Introduction to GPU Computing
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The Importance of Data
The landscape of Parallel Programing Models Part 2: The importance of Data Michael Wong and Rod Burns Codeplay Software Ltd. Distiguished Engineer, Vice President of Ecosystem IXPUG 2020 2 © 2020 Codeplay Software Ltd. Distinguished Engineer Michael Wong ● Chair of SYCL Heterogeneous Programming Language ● C++ Directions Group ● ISOCPP.org Director, VP http://isocpp.org/wiki/faq/wg21#michael-wong ● [email protected] ● [email protected] Ported ● Head of Delegation for C++ Standard for Canada Build LLVM- TensorFlow to based ● Chair of Programming Languages for Standards open compilers for Council of Canada standards accelerators Chair of WG21 SG19 Machine Learning using SYCL Chair of WG21 SG14 Games Dev/Low Latency/Financial Trading/Embedded Implement Releasing open- ● Editor: C++ SG5 Transactional Memory Technical source, open- OpenCL and Specification standards based AI SYCL for acceleration tools: ● Editor: C++ SG1 Concurrency Technical Specification SYCL-BLAS, SYCL-ML, accelerator ● MISRA C++ and AUTOSAR VisionCpp processors ● Chair of Standards Council Canada TC22/SC32 Electrical and electronic components (SOTIF) ● Chair of UL4600 Object Tracking ● http://wongmichael.com/about We build GPU compilers for semiconductor companies ● C++11 book in Chinese: Now working to make AI/ML heterogeneous acceleration safe for https://www.amazon.cn/dp/B00ETOV2OQ autonomous vehicle 3 © 2020 Codeplay Software Ltd. Acknowledgement and Disclaimer Numerous people internal and external to the original C++/Khronos group, in industry and academia, have made contributions, influenced ideas, written part of this presentations, and offered feedbacks to form part of this talk. But I claim all credit for errors, and stupid mistakes. These are mine, all mine! You can’t have them. -
AMD Accelerated Parallel Processing Opencl Programming Guide
AMD Accelerated Parallel Processing OpenCL Programming Guide November 2013 rev2.7 © 2013 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, AMD Accelerated Parallel Processing, the AMD Accelerated Parallel Processing logo, ATI, the ATI logo, Radeon, FireStream, FirePro, Catalyst, and combinations thereof are trade- marks of Advanced Micro Devices, Inc. Microsoft, Visual Studio, Windows, and Windows Vista are registered trademarks of Microsoft Corporation in the U.S. and/or other jurisdic- tions. Other names are for informational purposes only and may be trademarks of their respective owners. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or other- wise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as compo- nents in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or envi- ronmental damage may occur. -
Delivering Heterogeneous Programming in C++
Delivering Heterogeneous Programming in C++ Duncan McBain, Codeplay Software Ltd. About me ● Graduated from Edinburgh University 3 years ago ● Postgrad course got me interested in GPU programming ● Worked at Codeplay since graduating ● Research projects, benchmarking, debuggers ● Most recently on C++ library for heterogeneous systems 2 © 2016 Codeplay Software Ltd. Contents • What are heterogeneous systems? • How can we program them? • The future of heterogeneous systems 3 © 2016 Codeplay Software Ltd. What are heterogeneous systems • By this, I mean devices like GPUs, DSPs, FPGAs… • Generally a bit of hardware that is more specialised than, and fundamentally different to, the host CPU • Specialisation can make it very fast • Can also be harder to program because of specialisation 4 © 2016 Codeplay Software Ltd. Some definitions • Host – The CPU/code that runs on the CPU, controls main memory (RAM), might control many devices • Device – A GPU, DSP, or something more exotic • Heterogeneous system – A host, a device and an API tying them together 5 © 2016 Codeplay Software Ltd. Some definitions • Kernel – Code representing the computation to be performed on the device. • Work group – A collection of many work items executing on a device. Has shared local memory and executes same instructions 6 © 2016 Codeplay Software Ltd. Some definitions ● Work item – A single thread or task on a device that executes in parallel ● Parallel for – Some collection of work items, in many work groups, executing a kernel in parallel. In general, cannot return anything, and must be enqueued asynchronously 7 © 2016 Codeplay Software Ltd. Example heterogeneous device ● CPUs today can execute instructions out-of-order, speculative execution, branch prediction ● Complexity hidden from programmer ● Contrast with e.g. -
Exploring Weak Scalability for FEM Calculations on a GPU-Enhanced Cluster
Exploring weak scalability for FEM calculations on a GPU-enhanced cluster Dominik G¨oddeke a,∗,1, Robert Strzodka b,2, Jamaludin Mohd-Yusof c, Patrick McCormick c,3, Sven H.M. Buijssen a, Matthias Grajewski a and Stefan Turek a aInstitute of Applied Mathematics, University of Dortmund bStanford University, Max Planck Center cComputer, Computational and Statistical Sciences Division, Los Alamos National Laboratory Abstract The first part of this paper surveys co-processor approaches for commodity based clusters in general, not only with respect to raw performance, but also in view of their system integration and power consumption. We then extend previous work on a small GPU cluster by exploring the heterogeneous hardware approach for a large-scale system with up to 160 nodes. Starting with a conventional commodity based cluster we leverage the high bandwidth of graphics processing units (GPUs) to increase the overall system bandwidth that is the decisive performance factor in this scenario. Thus, even the addition of low-end, out of date GPUs leads to improvements in both performance- and power-related metrics. Key words: graphics processors, heterogeneous computing, parallel multigrid solvers, commodity based clusters, Finite Elements PACS: 02.70.-c (Computational Techniques (Mathematics)), 02.70.Dc (Finite Element Analysis), 07.05.Bx (Computer Hardware and Languages), 89.20.Ff (Computer Science and Technology) ∗ Corresponding author. Address: Vogelpothsweg 87, 44227 Dortmund, Germany. Email: [email protected], phone: (+49) 231 755-7218, fax: -5933 1 Supported by the German Science Foundation (DFG), project TU102/22-1 2 Supported by a Max Planck Center for Visual Computing and Communication fellowship 3 Partially supported by the U.S. -
Programmers' Tool Chain
Reduce the complexity of programming multicore ++ Offload™ for PlayStation®3 | Offload™ for Cell Broadband Engine™ | Offload™ for Embedded | Custom C and C++ Compilers | Custom Shader Language Compiler www.codeplay.com It’s a risk to underestimate the complexity of programming multicore applications Software developers are now presented with a rapidly-growing range of different multi-core processors. The common feature of many of these processors is that they are difficult and error-prone to program with existing tools, give very unpredictable performance, and that incompatible, complex programming models are used. Codeplay develop compilers and programming tools with one primary goal - to make it easy for programmers to achieve big performance boosts with multi-core processors, but without needing bigger, specially-trained, expensive development teams to get there. Introducing Codeplay Based in Edinburgh, Scotland, Codeplay Software Limited was founded by veteran games developer Andrew Richards in 2002 with funding from Jez San (the founder of Argonaut Games and ARC International). Codeplay introduced their first product, VectorC, a highly optimizing compiler for x86 PC and PlayStation®2, in 2003. In 2004 Codeplay further developed their business by offering services to processor developers to provide them with compilers and programming tools for their new and unique architectures, using VectorC’s highly retargetable compiler technology. Realising the need for new multicore tools Codeplay started the development of the company’s latest product, the Offload™ C++ Multicore Programming Platform. In October 2009 Offload™: Community Edition was released as a free-to-use tool for PlayStation®3 programmers. Experience and Expertise Codeplay have developed compilers and software optimization technology since 1999. -
Evolution of the Graphical Processing Unit
University of Nevada Reno Evolution of the Graphical Processing Unit A professional paper submitted in partial fulfillment of the requirements for the degree of Master of Science with a major in Computer Science by Thomas Scott Crow Dr. Frederick C. Harris, Jr., Advisor December 2004 Dedication To my wife Windee, thank you for all of your patience, intelligence and love. i Acknowledgements I would like to thank my advisor Dr. Harris for his patience and the help he has provided me. The field of Computer Science needs more individuals like Dr. Harris. I would like to thank Dr. Mensing for unknowingly giving me an excellent model of what a Man can be and for his confidence in my work. I am very grateful to Dr. Egbert and Dr. Mensing for agreeing to be committee members and for their valuable time. Thank you jeffs. ii Abstract In this paper we discuss some major contributions to the field of computer graphics that have led to the implementation of the modern graphical processing unit. We also compare the performance of matrix‐matrix multiplication on the GPU to the same computation on the CPU. Although the CPU performs better in this comparison, modern GPUs have a lot of potential since their rate of growth far exceeds that of the CPU. The history of the rate of growth of the GPU shows that the transistor count doubles every 6 months where that of the CPU is only every 18 months. There is currently much research going on regarding general purpose computing on GPUs and although there has been moderate success, there are several issues that keep the commodity GPU from expanding out from pure graphics computing with limited cache bandwidth being one. -
Graphics Processing Units
Graphics Processing Units Graphics Processing Units (GPUs) are coprocessors that traditionally perform the rendering of 2-dimensional and 3-dimensional graphics information for display on a screen. In particular computer games request more and more realistic real-time rendering of graphics data and so GPUs became more and more powerful highly parallel specialist computing units. It did not take long until programmers realized that this computational power can also be used for tasks other than computer graphics. For example already in 1990 Lengyel, Re- ichert, Donald, and Greenberg used GPUs for real-time robot motion planning [43]. In 2003 Harris introduced the term general-purpose computations on GPUs (GPGPU) [28] for such non-graphics applications running on GPUs. At that time programming general-purpose computations on GPUs meant expressing all algorithms in terms of operations on graphics data, pixels and vectors. This was feasible for speed-critical small programs and for algorithms that operate on vectors of floating-point values in a similar way as graphics data is typically processed in the rendering pipeline. The programming paradigm shifted when the two main GPU manufacturers, NVIDIA and AMD, changed the hardware architecture from a dedicated graphics-rendering pipeline to a multi-core computing platform, implemented shader algorithms of the rendering pipeline in software running on these cores, and explic- itly supported general-purpose computations on GPUs by offering programming languages and software- development toolchains. This chapter first gives an introduction to the architectures of these modern GPUs and the tools and languages to program them. Then it highlights several applications of GPUs related to information security with a focus on applications in cryptography and cryptanalysis. -
The Shallow Water Equations on Graphics Processing Units
Compact Stencils for the Shallow Water Equations on Graphics Processing Units Technology for a better society 1 Brief Outline • Introduction to Computing on GPUs • The Shallow Water Equations • Compact Stencils on the GPU • Physical correctness • Summary Technology for a better society 2 Introduction to GPU Computing Technology for a better society 3 Long, long time ago, … 1942: Digital Electric Computer (Atanasoff and Berry) 1947: Transistor (Shockley, Bardeen, and Brattain) 1956 1958: Integrated Circuit (Kilby) 2000 1971: Microprocessor (Hoff, Faggin, Mazor) 1971- More transistors (Moore, 1965) Technology for a better society 4 The end of frequency scaling 2004-2011: Frequency A serial program uses 2% 1971-2004: constant 29% increase in of available resources! frequency 1999-2011: 25% increase in Parallelism technologies: parallelism • Multi-core (8x) • Hyper threading (2x) • AVX/SSE/MMX/etc (8x) 1971: Intel 4004, 1982: Intel 80286, 1993: Intel Pentium P5, 2000: Intel Pentium 4, 2010: Intel Nehalem, 2300 trans, 740 KHz 134 thousand trans, 8 MHz 1.18 mill. trans, 66 MHz 42 mill. trans, 1.5 GHz 2.3 bill. trans, 8 X 2.66 GHz Technology for a better society 5 How does parallelism help? 100% The power density of microprocessors Single Core 100% is proportional to the clock frequency cubed: 100% 85% Multi Core 100% 170 % Frequency Power 30% Performance GPU 100 % ~10x Technology for a better society 6 The GPU: Massive parallelism CPU GPU Cores 4 16 Float ops / clock 64 1024 Frequency (MHz) 3400 1544 GigaFLOPS 217 1580 Memory (GiB) 32+ 3 Performance -
Fragment Shader
Programmable Graphics Hardware Outline 2/ 49 A brief Introduction into Programmable Graphics Hardware • Hardware Graphics Pipeline • Shading Languages • Tools • GPGPU • Resources [email protected] Dynamic Graphics Project University of Toronto Hardware Graphics Pipeline 3/ 49 Hardware Graphics Pipeline From vertices to pixels ... and what you can do in between. [email protected] Dynamic Graphics Project University of Toronto Hardware Graphics Pipeline 4/ 49 Hardware Graphics Pipeline GPU Video Memory CPU Vertex Fragment Processor Processor Raster Render Screen Unit Target [email protected] Dynamic Graphics Project University of Toronto Hardware Graphics Pipeline 5/ 49 Hardware Graphics Pipeline GPU Video Memory CPU Vertex Fragment Processor Processor Raster Render Screen Unit Target [email protected] Dynamic Graphics Project University of Toronto Hardware Graphics Pipeline 6/ 49 Hardware Graphics Pipeline GPU Video Memory CPU Vertex Fragment Processor Processor Raster Render Screen Unit Target [email protected] Dynamic Graphics Project University of Toronto Hardware Graphics Pipeline 7/ 49 Hardware Graphics Pipeline GPU Video Memory CPU Vertex Fragment Processor Processor Raster Render Screen Unit Target [email protected] Dynamic Graphics Project University of Toronto Hardware Graphics Pipeline 8/ 49 Hardware Graphics Pipeline GPU Video Memory CPU Vertex Fragment Processor Processor Raster Render Screen Unit Target [email protected] Dynamic Graphics Project University of Toronto Hardware Graphics Pipeline -
GPGPU in System Simulations
Lappeenranta-Lahti University of Technology LUT School of Engineering Science Degree Programme in Computational Engineering Mikko Majamaa GPGPU in System Simulations Bachelor’s Thesis 2020 Supervisors: Arto Kaarna, Associate Professor Janne Kurjenniemi, Ph.D. TIIVISTELMA¨ Lappeenrannan-Lahden teknillinen yliopisto LUT School of Engineering Science Laskennallisen tekniikan koulutusohjelma Mikko Majamaa GPGPU in System Simulations Kandidaatintyo¨ 2020 30 sivua, 4 kuvaa, 5 taulukkoa, 2 liitetta¨ Ohjaajat: Arto Kaarna, Tutkijaopettaja Janne Kurjenniemi, Ph.D. Avainsanat: GPGPU; systeemisimulaatio; CUDA; satelliitti; tietoverkko; Systeemisimulointi voi olla laskennallisesti raskas tehtav¨ a.¨ Grafiikkaprosessorin (GPU) avus- tuksella yleisessa¨ laskennassa, voidaan hyvaksik¨ aytt¨ a¨a¨ GPU:iden massiivista rinnakkaistet- tavuutta simulointiaikojen lyhentamiseksi.¨ Tam¨ an¨ kandidaatintyon¨ tavoitteena on kirjal- lisuuskatsauksen avulla saavuttaa perustietamys¨ grafiikkaprosessoreilla tehtav¨ ast¨ a¨ yleises- ta¨ laskennasta (GPGPU). Lisaksi¨ tavoitteena on soveltaa saavutettu perustietamys¨ kayt¨ an-¨ to¨on¨ toteuttamalla GPGPU:n kaytt¨ o¨a¨ Python-pohjaiseen satelliittiverkkosimulaattoriin. Tulokset osoittavat, etta¨ GPGPU:n kayt¨ oll¨ a¨ systeemisimuloinneissa on suuri potentiaali - sen kayt¨ oll¨ a¨ saavutettiin 16.0-kertainen kokonaisnopeutus ja 45.1-kertainen nopeutus linkkibud- jettilaskelmissa peratt¨ aiseen¨ ajoon perustuvaan toteutukseen verrattuna. ABSTRACT Lappeenranta-Lahti University of Technology LUT School of Engineering Science -
Open Standards Enable Continuous Software Development in the Automotive Industry
AUTOSENS PROCEEDINGS 1 Open standards enable continuous software development in the automotive industry Markus Glaser, Charles Macfarlane, Benjamin May, Sven Fleck, Lukas Sommer, Jann-Eve Stavesand, Christian Weber, Duong-Van Nguyen, Enda Ward, Illya Rudkin, Stefan Milz, Rainer Oder, Frank Bohm,¨ Benedikt Schonlau, Oliver Hupfeld, Andreas Koch Abstract—Until recently, the automotive industry was primarily focused on design, development of electronics and mechanics, and manufacturing. Nowadays the software component of new vehicles has become a large portion of the development cost, driven by adding numerous new sensors, intelligent algorithms, very powerful and specialized processors and a highly complex user experience to the vehicle. In addition, requirements for high-performance and real-time processing as well as the vehicle’s distributed architecture bring challenges, but moreover supply chains further complicate development. In this article a high-level overview of vehicle development is provided, followed by a deep dive in the different software development processes, languages and tools that are required for efficient development of the next generation of intelligent vehicles. This paper especially explores SYCLTM, an open standard from The KhronosTM Group for high-performance programming of heterogeneous multicore processor system. Index Terms—Automotive, continuous development, open standards, SYCL, CUDA, AI driven, software driven, ADAS, heterogeneous computing, AI, Machine Learning F 1 INTRODUCTION ing open standards (e.g. SYCL). To this end an overview of the automotive landscape is given, where functional safety Modern cars utilize 100+ ECUs and reached 100M lines standards are now the norm and where open standards of code by 2015 [1], [2]. Code complexity is expected to for software are becoming the solution for the automotive increase exponentially, resulting in over 650M lines of code industry, achieving the demands of ADAS developers and by 2025 [3] for every vehicle and over 1bn lines to achieve a overcoming software development challenges. -
SYCL for CUDA
DPC++ on Nvidia GPUs DPC++ on Nvidia GPUs Ruyman Reyes Castro Stuart Adams, CTO Staff Software Engineer IXPUG/TACC Products Markets High Performance Compute (HPC) Integrates all the industry C++ platform via the SYCL™ Automotive ADAS, IoT, Cloud Compute standard technologies needed open standard, enabling vision Smartphones & Tablets to support a very wide range & machine learning e.g. of AI and HPC TensorFlow™ Medical & Industrial Technologies: Artificial Intelligence Vision Processing The heart of Codeplay's Machine Learning compute technology enabling Big Data Compute OpenCL™, SPIR-V™, HSA™ and Vulkan™ Enabling AI & HPC to be Open, Safe & Company Customers Accessible to All Leaders in enabling high-performance software solutions for new AI processing systems Enabling the toughest processors with tools and middleware based on open standards Established 2002 in Scotland with ~80 employees And many more! 3 © 2020 Codeplay Software Ltd. Summary • What is DPC++ and SYCL • Using SYCL for CUDA • Design of SYCL for CUDA • Implementation of SYCL for CUDA • Interoperability with existing libraries • Using oneMKL on CUDA • Conclusions and future work 4 © 2020 Codeplay Software Ltd. What is DPC++? Intel’s DPC++ • Data Parallel C++ (DPC++) is an open, standards-based alternative to single-architecture proprietary languages, part of oneAPI spec. SYCL 2020 • It is based on C++ and SYCL, allowing developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and also perform custom tuning for SYCL 1.2.1 a specific accelerator. 5 © 2020 Codeplay Software Ltd. Codeplay and SYCL • Codeplay has been part of the SYCL community from the beginning • Our team has helped to shape the SYCL open standard • We implemented the first conformant SYCL product 6 © 2020 Codeplay Software Ltd.