University of Cincinnati

UNIVERSITY OF CINCINNATI

DATE: 7th March, 2002

I, Prashant R. Bhadri , hereby submit this as part of the requirements for the degree of: Master of Science in: Electrical Engineering It is entitled: Implementation of a Silicon Control Chip for Si/SiC Hybrid Optically Activated High Power Switching Device

Approved by:

Dr Fred Beyette Jr.

Dr Harold W Carter

Dr Marc Cahay

Implementation of a Silicon Control Chip for a Si/SiC Hybrid Optically Activated High Power Switching Device

A thesis submitted to the

Division of Graduate Studies and Research of the University of Cincinnati

in partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

in the Department of

Electrical & Computer Engineering and Computer Science

of the College of Engineering

March 2002 By Prashant R. Bhadri

B.S., (ECE), Birla Institute of Technology,

Ranchi, India, 1999

Thesis Advisor and Committee Chair: Dr. Fred R. Beyette Jr.

IMPLEMENTATION OF SILICON CONTROL CHIP FOR A SI/SIC HYBRID OPTICALLY ACTIVATED HIGH POWER SWITCHING DEVICE

Prashant R. Bhadri

ABSTRACT

In avionic systems, data integrity and high data rates are necessary for stable flight

control. Unfortunately, conventional electronic control systems are susceptible to

electromagnetic interference (EMI) that can reduce the clarity of flight control signals.

Fly-by-Light systems that use optical signals to actuate the flight control surfaces of an

aircraft have been suggested as a solution to the EMI problem in avionic systems. Fly-

by-Light in avionic systems reduces electromagnetic interference hence improving the

clarity of the control signals. Fly-by-Light technology development involves creation of

building blocks like computers, fiber optic sensors and interfaces, fiber actuator loops,

an integrated system etc. The development of this technology exploits fiber optic sensor

and control technology. This thesis demonstrates a hybrid approach that combines a

smart silicon photoreceiver module with a SiC power transistor. The resulting device

uses a 5mW optical control signal to produce a 150A current that is suitable for driving

an electric motor. This is the first attempt to integrate silicon carbide devices with a

smart silicon chip.

The first part of the thesis deals with the various high power technologies that are in use

today. Different approaches are discussed and emphasis is stressed on the silicon/silicon

i carbide hybrid design. Briefly discussed is the use of silicon carbide for optical switching

application. Second part of the thesis involves the design, simulation and analysis of the

silicon smart chip. Individual components of the smart silicon are characterized and

results shown. Finally, we report the performance evaluation of this smart silicon

realized in a 1.5 micron CMOS process using MOSIS1 foundry service.

1 MOSIS http://www.mosis.org

iii ACKNOWLEDGEMENTS

I wish to express my heartfelt gratitude to Dr. Fred Beyette Jr. for his guidance and for providing me funds to work on this project. I feel happy and was gifted to be blessed with his guidance, which was based on thorough knowledge. Deep appreciation goes to Dr.

Harold Carter for his assistance with the various aspects of the project. It certainly had been a great opportunity to meet, truly remarkable teacher Dr. Marc Cahay whose doors were always open to me to discuss the issues related to the project and I thank him for accommodating me in his busy schedule whenever he could.

It is of paramount importance to convey my gratitude to my parents whose ultimate ambition was to see their children reach the pinnacle of education. This journey wouldn’t have been possible if not for them and my wonderful brother Prasad Bhadri, who I always praised for his teaching ability, had been a great teacher in my learning work and am thankful to him for his time.

I am profoundly thankful to my colleagues their mentoring, in and out of the laboratory which helped in a very big way in this project. They were always there for me, especially in those moments where I needed his guidance the most. Working with them at Photonics

Systems Development Laboratory (PSDL) has been a great pleasure for me. Thanks are also due to my colleagues Jianjing Tang, Sunil Konanki, Prosenjit Mal and Deepti Sukumaran for their help with the circuit design issues.

In particular I like to thank Aniruddha Puntambekar and Sukirti Gupta from the MEMS lab for helping me out with the packaging and layout issues. I also would like to thank Shekar

Menon, Avinash Joshi, Nitish Mathur, Nitin Auluck and Shilpa Trisal for their encouragement and support. I would also like to acknowledge Chris Isbell, Rob Montjoy and

Roger Kirschner for helping me during various phases during my research.

v TABLE OF CONTENTS

LIST OF FIGURES ...... ix

LIST OF TABLES...... xii

1. INTRODUCTION ...... 1

1.1 Motivation and Research ...... 1 1.2 Device Approach ...... 2

1.2.1 Silicon Carbide Single Transistor ...... 2 1.3.2 Silicon Carbide Darlington Configuration ...... 4 1.3.3 Silicon/Silicon Carbide Hybrid ...... 6

1.3 General Research Objectives ...... 7 1.4 Expected Contributions to the Research ...... 8 1.5 Overview of the Thesis...... 8

2. BACKGROUND AND RELATED RESEARCH...... 10

2.1 Characteristics of Smart Silicon...... 10 2.2. Components of Smart Silicon ...... 10

2.2.1 Photodiode Structure ...... 11 2.2.2 Photoreceiver Circuit ...... 12 2.2.3 Current Source/Sink Circuit...... 12 2.2.4 Bipolar Junction Transistor ...... 12 2.2.5 Failure Detection Circuits ...... 13

2.3 Technology used for Fabrication ...... 14 2.4 Related Research ...... 16

2.4.1 CMOS Technology………………………………………... 16 2.4.2 Bipolar and BiCMOS Technology...... 19 2.4.3 High Voltage CMOS Technology...... 22

2.5 Summary...... 22

vi 3. SIMULATED SILICON DEVICE STRUCTURE...... 25

3.1 PHOTODETECTORS...... 25

3.1.1 Technology Overview...... 25 3.1.2 Selected Devices...... 26 3.1.2.1 P-diffusion to N-well Photodetector...... 28 ......

3.2 PHOTORECEIVER ...... 31

3.2.1 Technology Overview...... 31 3.2.2 Selected Approach...... 32

3.3. CURRENT SOURCES AND SINK CIRCUITS...... 38

3.3.1. Technology Overview...... 38 3.3.2 Selected Devices ...... 40

3.3.2.1 Basic Current Sink...... 40 3.3.2.2 Basic Current Source ...... 41 3.3.2.3. Cascode Current Source...... 42

3.3.3 Simulations of the Current Source...... 44

3.4 BIPOLAR JUNCTION TRANSISTOR ...... 47

3.4.1. Technology Overview...... 47 3.4.2 Device Analysis...... 48 3.5.3 Simulations of the Bipolar Junction Transistor ...... 50

3.5 DETECTION CIRCUITS ...... 53

3.5.1 Override Circuit...... 53

3.5.1.1 Circuit Analysis ...... 53 3.5.1.2 Simulation of the Override Circuit...... 54

vii 3.5.2. Short Circuit Circuitry...... 55

3.5.2.1. Circuit Analysis ...... 55 3.5.2.2 Simulation of the Short Circuitry...... 56

3.6 PADS AND PAD FRAME IMPLEMENTATION...... 58

3.6.1. Technology Overview...... 59 3.6.2. Description of Pad...... 59

3.6.2.1 VDD and VSS Pads...... 59 3.6.2.2 Input Pads...... 60 3.6.2.3 Input / Output Pads...... 62 3.6.2.4 Analog Pads...... 63

4. PERFORMANCE EVALUATION...... 64

4.1 Test Set up ...... 64 4.2 Photodetector Testing ...... 67 4.3 Photoreceiver Testing...... 69 4.4 Current Source Testing...... 70 4.5 Bipolar Junction Transistor Testing...... 71 4.6 Detection Circuit Testing...... 73

4.6.1 Override Testing...... 74 4.6.2 Current Sink Testing...... 75 4.6.3 Short Circuitry Testing ...... 75

4.7 Layout Design...... 76 4.8 Layout of the chip incorporated in the pad ...... 77

5. CONCLUSION7...... 79

5.1 Summary...... 79

BIBLIOGRAPHY...... 81

APPENDIX 1...... I

viii LIST OF FIGURES

1. INTRODUCTION 1.2 Silicon Carbide Single Transistor Configuration with an optical input.. 4 1.3 Silicon Carbide Darlington Pair Configuration with an optical input ...... 5 1.4 Silicon/Silicon Carbide Hybrid Configuration...... 6

2. BACKGROUND AND RELATED RESEARCH

2.1 Cross section of a Metal Oxide Semiconductor FET ...... 17 2.2 Simplified cross section of BiCMOS process realization of NMOS, PMOS and n-p-n device ...... 19

3. SIMULATED SILICON DEVICE STRUCTURE

3.1 P - Diffusion N -well structure...... 28 3.2 Layout of a P-diffusion N-well photodetector ...... 29 3.3 Photocurrent vs. Finger Spacing curve ...... 29 3.4 Transient Response of P-diffusion N-well photodetector ...... 30 3.5 Photoreceiver circuit design ...... 32 3.6 Push Pull Amplifier Design...... 33 3.7 Analysis of different sizing of PMOS load transistor...... 34 3.8 Simulation results of the photoreceiver circuit ...... 35 3.9 Simulations showing the Tplh delay ...... 35 3.10 Simulations showing the Tphl delay ...... 36 3.11 Power Dissipation in the photoreceiver circuit ...... 37 3.12 A Basic current sink schematic...... 40 3.13 A basic current source circuit ...... 41 3.14 A cascode current source circuit...... 42 3.15 Simulation of the output current (I source)...... 44

ix 3.16 Simulation showing the operation of the current source...... 45 3.17 Power dissipation curve...... 46 3.18 Circuit diagram of the BiCMOS circuit...... 48 3.19 Circuit of a NPN BJT...... 50 3.20 Ic vs. Vce Curve for Ib = 70uA...... 51 3.21 Output current from the BJT stage...... 51 3.22 Power Analysis curve for the BJT stage...... 52 3.23 Override circuit ...... 53 3.24 a) Input Override ...... 54 3.24 b) Optical Input ...... 54 3.25 Output override signal...... 54 3.26 Vce short circuit circuitry ...... 55 3.27 Simulation results of the short circuit circuitry ...... 56 3.28 Power variation curve ...... 58 3.29 a) Layout of the ground pad ...... 59 3.29 b) Layout of the Vdd pad ...... 59 3.30 ESD Protection Circuitry...... 60 3.31 Layout of input pad circuit ...... 61 3.32 Circuit design of an I/O pad ...... 62 3.33 a) Conventional analog pad...... 63 3.33 b) Redesigned analog pad...... 63

4. PERFORMANCE EVALUATION

4.1 Optical test set up for testing the silicon chip...... 64 4.2 Power variations at different positions in the optical setup ...... 65 4.3 Semiconductor Parametric Analyzer ...... 66 4.4 Photodetector testing set up...... 67 4.5 Photodetector current vs. Optical input power...... 67 4.6. Photoreceiver testing results...... 69 4.7 Testing results of the current sources...... 70 4.8 Layout of a bipolar junction transistor...... 72 4.9 Ic vs. Vce curve of the bipolar junction transistor...... 73

x 4.10 Output voltage curve with variable override conditions ...... 74 4.11 Output current with variable override conditions ...... 75 4.12 Layout of the Optically Activated High Power Silicon Chip...... 77 4.13 Design of the chip incorporated in a pad frame ...... 78

LIST OF TABLES

1. INTRODUCTION

1.1 Comparison of Properties of Silicon, GaAs and Silicon Carbide ...... 3

3. SIMULATED SILICON DEVICE STRUCTURE

3.1 Simulation results of all the photodetector structures...... 27

xii CHAPTER 1

INTRODUCTION

1.1 MOTIVATION AND RESEARCH

Fiber optic component technology has been under development by the government and industry laboratories for over 20 years. Over the same period, the ever-increasing performance and economy of operation requirements placed on commercial and military transport aircraft have led to a very avionic complex system. To reduce system complexity and simplify manufacturing requirements, it has been suggested that fiber optic components could be incorporated into the flight control systems of modern aircraft [1]. The often-cited benefits of this so-called Fly-by-Light technology are high data throughput, immunity to

EMI, reduced certification and maintenance costs and reduced weight features.

With an optically activated switch, it is possible to use control signals that are transmitted using optical fibers which are much lighter than the copper wires used in conventional switches. In addition to this weight benefit, optical fibers allow high bandwidth and increased data integrity which ultimately leads to simplification of the avionic system design.

Fly-by-Light (FBL) technology revolves primarily on the replacement of electronic data transmission, mechanical control linkages, and electronic sensors with optical components

1 and subsystems. Current fly-by-light systems are limited by the lack of optically activated high-power switching devices. Installing these technologies on the aircraft will lower initial acquisition and direct operating costs, reduce weight and increase aircraft performance and reliability. Specific fuel consumption is also reduced as a result of lower aircraft weight and improved thrust specific fuel consumption.

In this thesis, we focus on the development of a control circuitry for a high power silicon carbide switching device.

1.2 DEVICE APPROACH

Project specifications require designing a prototype optically activated high power switch, which is capable of switching 150A of drive current from a 135V power supply with a one micro-second switching speed using a 5mW of optical control signal. Initially, three approaches were considered:

Silicon carbide single transistor approach.

Silicon carbide Darlington configuration approach.

Silicon/Silicon carbide hybrid approach

1.2.1 SILICON CARBIDE SINGLE TRANSISTOR

Most of the current high power switching technology relies on silicon power devices.

Unfortunately, when using silicon for high power devices it is necessary to insure that junction temperatures are kept below 200 degrees centigrade [2]. This imposes restrictions for operating at high temperature and high voltage environments.

2 As shown in Table 1.1, Silicon Carbide has a significantly higher breakdown field strength and thermal conductivity when compared with other common semiconductors. Further, with band gap energy 3 times larger than Silicon, SiC p-n junctions have significantly lower leakage currents. Perhaps most importantly Silicon Carbide electronic devices have been shown to provide reliable operation at temperatures up to 600 °C. Hence the complexities of providing a heat sink are avoided and the device yields electronic subsystems with dramatic weight reduction. By allowing stable operation in high temperature environments,

SiC based device will enable distributed control systems that could eliminate 90% of the wiring and connectors in conventional electronic control systems.

Properties Si GaAs 6H SiC Band gap (eV) 1.1 1.42 3.0 Breakdown Field (MV/cm) @ 1017 0.6 0.6 3.2 Electron Mobility (cm2/V-s) @ 1016 1100 6000 370 Saturated Electron Drift Velocity (cm/s) 107 107 2 × 107 Thermal Conductivity (W/cm-K) 1.5 0.5 4.9 Hole Mobility (cm2/V-s) @1016 420 320 90

Table 1.1 Comparisons of properties of Silicon, GaAs and Silicon Carbide [3]

Like silicon, silicon carbide is an optically active material that enables the development of the

fly by light avionic systems. As figure 1.2 indicates that the device must support 135V and

produce a switching current of 150 A. The device simulation of a SiC transistor structure

was performed using a simulation tool MEDICI. Initial simulation indicates if silicon carbide

bipolar junction is fabricated, 5 Watts of input optical power is required to produce 150A of

drive current [1]. With common solid-state light sources producing an optical power in the

3 range of few hundred milliwatts, a 5-Watt optical power requirement is too large to be feasible.

100 V

5 W

150 A

Figure 1.2 Silicon Carbide single transistor configuration with an optical input [4]

1.2.2 SILICON CARBIDE DARLINGTON CONFIGURATION

A Darlington Pair configuration can be used to significantly reduce the input optical power to the switch. For large currents it is standard practice to use a darlington pair of transistors, rather than a single transistor. A Darlington pair effectively acts like a single transistor with ß that is the product of the two ß’s of the individual transistors. It makes sense that a transistor, which can operate with very little base current, can handle only a reasonably small collector current. And likewise a transistor, which can deliver larger collector currents, requires a larger base current to cause it to operate over its entire active region. As figure 1.3 shows, 50mW of optical control required to produce a 150A of

4 current. This is significantly lower than 5W of optical power required for the single

transistor configuration [2].

100 V

50 mW

150 A

Figure 1.3 Silicon Carbide Darlington Pair Configuration with an optical input [4]

While this approach reduces the optical power requirement to a practical level, it cannot

address a fundamental problem faced by SiC optoelectronics .The problem with this design is that, silicon carbide material is optically active only at wavelengths less than 420nm. As a result the device is transparent to most of the visible spectrum and the entire infrared spectrum. Thus, it is not compatible with commercial wavelength division multiplexing technologies which operate in the near infrared region of the optical spectrum. Further, it

does not satisfy the 835nm specification posed for this project.

5 1.2.3 SILICON/SILICON CARBIDE HYBRID

The design of a Silicon/Silicon Carbide hybrid is the core topic of this thesis. To address the

difficulties described above, we have proposed a single hybrid device package. The hybrid approach involving silicon/silicon carbide devices fabricated individually and packaged together. With this approach a silicon photodetector can easily be designed that’s active in all

Figure 1.4 Silicon/ Silicon Carbide Hybrid Configuration [5]

of the visible and near infrared regions of the optical spectrum. Secondly input to the silicon

carbide is electrical not optical reducing significantly compatibility issues.

As figure 1.4 shows “smart silicon” driving the silicon carbide Darlington Pair. The silicon

device consists of photodiode, receiver circuit, and current drive /sink circuit and diagnostic

circuit. All chip circuitry is referenced to a common ground.

6 1.3 GENERAL RESEARCH OBJECTIVE

While a variety of technologies have been suggested for implementing an optical switching device, this is the first time a hybrid approach has been considered for avionic applications.

In the present application, the device has to work for a specific optical wavelength. As a result the control of the hybrid device, has to be designed to meet both the wavelength and the optical power criteria. Hence, a smart silicon chip must consist of photodetector components, analog circuitry and digital circuitry.

The CMOS technology is available to implement the above design specification. In this thesis we investigate the use of a smart silicon approach incorporated into the present technology. The technical objectives for this research are summarized below:

Design of an optically activated control chip for a high power, high temperature SiC

switch to be used in a motor actuation system. The project implementation can be

broken down into several subtasks.

Development of smart silicon CMOS chip suitable for driving the silicon carbide

Darlington Pair transistor. The chip should consist of control modules as per

specifications of the project.

Characterization of individual components of the smart silicon chip.

Perform chip testing and determine performance characteristics over the design

operating environment specification range.

Analysis of simulation and test result of the of the silicon chip

Make conclusions about the device behavior.

Suggest future improvement in designing of the smart silicon.

7 1.4 EXPECTED CONTRIBUTIONS TO THE RESEARCH

The research is expected to make inroads into use of hybrid devices for high performance applications. As this provides a new opportunity to exploit silicon and silicon carbide based hybrid devices for high power, high temperature application, it also lays the groundwork for various future applications in various fields related to optically activated control. As indicated above various aspects of multi-technology design have been introduced including incorporating optical devices, BiCMOS, high power design and analog pad design.

1.5 OVERVIEW OF THE THESIS

The remainder of the thesis has been organized into five chapters. Section below provides a brief overview of these chapters.

Chapter 2: This chapter provides background information for this research. Specifically

the chapter highlights the different technologies being used in the implementation of

this thesis work . Additionally it provides an overview of the fabrication processes and

various other associated technologies which could have been used to implement the

optically activated high power switch.

Chapter 3: This chapter deals with the individual components used in the design of the

silicon chip. Individual sections have been dedicated to describe the circuitry involved

in the design. The optical section specifically emphasizes on the optical part of the

smart silicon and illustrates the different types of photodetectors evaluated for this

particular application. The opto-electronic section presents approaches of designing a

8 photoreceiver circuit including details of design and characterization of the specific

photoreceiver designed. The analog section emphasizes the design of current sources

and sinks. The digital design section deals with the intelligent part of the smart silicon.

It describes in detail the detection circuits incorporated in the silicon module as

Optical, Short and Override circuitry. The driver section provides the information of

the bipolar junction transistor. Details have been illustrated with respect to the PNP

and NPN silicon bipolar design. The final section in this chapter provides information

about the Pad frame and Pad design. As the driver outputs a 15mA of current detail

analysis is performed with respect to the pad design .As it’s a multitechnology chip the

pad frames design and analysis have been discussed in detail. Spice Analysis and

modeling parameters with simulations have been described in detail for each sections.

Chapter 4: This chapter provides the performance evaluation of the fabricated silicon

chip. Extensive test analysis and results are shown with respect to the components in

the chip. The chapter also provides a detailed discussion of both simulated and test

results. Various layout design techniques incorporated in this mixed signal chip have

been illustrated.

Chapter 5: Significant results are summarized in this chapter along with in depth

suggestion for future work to be carried in this area.

9 CHAPTER 2

BACKGROUND AND RELATED RESEARCH

2.1 CHARACTERISTICS OF SMART SILICON

The silicon circuit design described in the thesis is the fundamental component of the

optically activated silicon carbide high power, high temperature switch. As described in

section 1.2.3 and shown in figure 1.4, the silicon in the hybrid device structure acts as optical

receiver and a current driver for the silicon carbide Darlington pair transistor. Although

power semiconductor technology has conventionally used silicon based devices it is limited to operation at junction temperatures below 200°C. Further, silicon based devices can only

be used in circuits where the voltage blocking capability do not exceed a few kilovolts [3].

These physical limitations impose restrictions on the use of silicon power devices in very

high-temperature, high-power environments.

There are number of benefits using silicon devices as a fabrication material. They include its

stable atomic structure, high melting point, relatively high breakdown fields and a very high

intrinsic carrier concentration [4]. Other advantages include its optical compatibility with the

present day IR technology, well-established technology for analog, digital and mixed signal

design. As a result the silicon technology is more cost effective and reliable.

10 2.2. COMPONENTS OF SMART SILICON CHIP

The smart silicon chip consists of multiple modules in its design. The modules incorporated

in the smart silicon are:

• Photodiode Structure

• Photoreceiver Structure

• Current source/sink circuit

• Bipolar junction transistor

• Failure detection circuit

The following subsections describe each of these components.

2.2.1 PHOTODIODE STRUCTURE

The photodiode structure [5] is used to detect optical signals. The operational parameters of the photodiode depend on its optical range of operation from the visible spectrum to the far-infrared . It can be inferred that a photodiode has some basic functions as described below : Generation of carriers when light in its spectral range is incident on the detected active area . Each photodiode structure has an optical responsivity based on the transportation of carriers the electrical leads of the device . Thus the amount of optically generated carriers depend on factors assosiated with the light source . A detail analysis of the photodiode performance is reviewed in Chapter 3.

2.2.2 PHOTORECEIVER CIRCUIT

The function of a photoreceiver is to amplify the signal received from the photodiode [6].

The design of the photoreceiver is essential to the optical/electronic interface in the circuit.

Photoreceiver design depends on the application requirements such as switching speed, and

optical sensitivity. Detail analysis of the photoreceiver is provided in Chapter 3.

2.2.3 CURRENT SOURCE/ SINK CIRCUIT

Current source/sink circuits are basic building blocks in a CMOS integrated circuit design

and are used extensively in the design of analog CMOS circuits. The importance of using a current source in the design of this chip is based on the requirement that the chip source current to the silicon carbide device. A current sink is also used to remove extra charges from the base of the second transistor of the Darlington pair silicon carbide device during the turn off phase of the switch operation. In an ideal case, the output impedance of a current source/sink is infinite and has the capability of generating or drawing a constant current over a wide range of voltages. Unfortunately, the finite resistance and limited output swing of CMOS device, operating in saturation lead to performance degradation from this ideal [7]. As the design of the current source and current sink is a determining factor in the switch performance, design, simulation and layout issues must be properly analyzed. Details regarding the design of the sink and source building blocks are discussed in Chapter 3.

12 2.2.4 BIPOLAR JUNCTION TRANSISTOR

Two PN junctions together lead to a creation of a bipolar transistor. Germanium is favoured for the PNP device while silicon for NPN device. The thin and lightly doped central region is known as the base and has majority charge carriers of opposite polarity to those in the surrounding material. The two outer regions are known as the emitter and the collector . Under the proper operating conditions the emitter will inject some of its majority charge carriers into the base region, because the base is very thin, most of the injected carriers move through the base to the collector. The emitter is highly doped to reduce resistance and the collector is lightly doped to reduce the junction capacitance of the collector-base junction. The device is operated in the forward active mode where the emitter-base junction is forward biased while the collector-base junction is reversed biased leading to a higher gain . Hence in a BJT, if the base-emitter diode becomes conducting, then a significant current can flow from collector to emitter. In other words, by adjusting the base-emitter voltage, the collector-emitter current can be controlled. This behavior has been used to construct an amplifier in the smart silicon design. In the design of a smart silicon we use a NPN BJT ( Bipolar Junction Transistor) as a driver circuit . Detail analysis is presented in Chapter 3 .

2.2.5 FAILURE DETECTION CIRCUITS

In addition to the drive circuitry, the silicon chip has several circuits which monitor the

operating conditions of the switch .The basic function of these circuits is to detect when

failure in a motor drive controller that might lead to a potentially fatal over biasing condition

for the switch itself. If a failure condition is detected the switch is then disabled. There are

three detection circuits are:

• Optical On circuit

• Short detection circuit

• Override circuit

The functionality of these is described in Chapter 3.

2.3 TECHNOLOGY USED FOR FABRICATION

The Metal-Oxide-Silicon Field-Effect-Transistor (MOSFET) is the prevailing device in

microprocessors and memory circuit design. In addition, the MOSFET is increasingly used

in areas as diverse as mainframe computers and power electronics. The MOSFET’s

advantages over other types of electronic devices are its mature fabrication technology, its

successful scaling characteristics and the fact that a combination of complementary

MOSFET’s yielding low power dissipation CMOS circuits.

The fabrication process of silicon devices has evolved over the last 25 years into a mature,

reproducible and reliable integrated circuit manufacturing technology. While the focus is on

14 individual devices, one must realize that the manufacturability of millions of such devices on a single substrate is a minimum requirement in today’s industry. Silicon has evolved as the material of choice for such devices, for a large part because of its stable oxide, silicon dioxide

(SiO2), which is used as an insulator, as a surface passivation layer and as a superior gate dielectric.

The scaling of MOSFET’s started in the seventies when the initial 10 micron gate length of the devices were gradually reduced by about a factor two every five years. Today (2002)

MOSFET’s with sub-micron gate lengths are manufactured on a large scale. This scaling is expected to continue well beyond the year 2004, as devices with a gate length smaller than 10 nm have already been demonstrated. While the size reduction is a minimum requirement when scaling MOSFET’s, successful scaling also includes the reduction of all the other dimensions of the device so that the device indeed delivers superior performance. Devices with record gate lengths are typically not fully scaled, so that several years go by until the large-scale production of such device takes place.

The combination of complementary MOSFET’s (CMOS) in logic circuits has the unique advantage that carrier’s only flow through the devices when the logic circuit changes its logic state. Therefore there is virtually no associated power dissipation if the logic state must not be changed. Since less than one out of ten gates of a large logic circuit switch at any given time, the use of CMOS circuits immediately reduces the overall power dissipation by a factor ten. Analysis of the individual CMOS technologies is illustrated in the remainder of this chapter.

15 2.4 RELATED RESEARCH

The use of a silicon/silicon carbide device is a novel and innovative approach for the design

of a high power switch. Although there are several power devices commercially available

design of a hybrid device is a first attempt to integrate mixed signal/mixed technology high

power switching device application. As stated in the previous chapter, the objective is to

develop an optically controlled switch suitable for driving an electric actuator motor. Various

research groups are working in the field of high power device design. In this research we

have tried to incorporate optical, digital and analog design with silicon carbide fabricated

device for designing a prototype device. There are number of technologies we will discuss

which illustrate different device technologies suitable for implementing the proposed design.

Different technologies offer advantages and disadvantages for the design of chips for

application specific operation. The dominant technologies available to date are CMOS,

BiCMOS and GaAs (MESFET and HEMT). CMOS has been exhaustively used in many

designs. The addition of bipolar transistors in BiCMOS processes, though advantageous in

achieving better matching properties and higher speeds, is not easily justifiable when

comparing other factors in the design. Commercial grade CMOS processes are accessible

through fabrication brokers, such as MOSIS and CMP. The following subsections review several of the most common CMOS based technologies.

2.4.1 CMOS TECHNOLOGY

MOSFET circuit technology has dramatically changed over the last three decades. Starting

with a ten-micron PMOS process with an aluminum gate and a single Metallization layer

around 1970, the technology has evolved into a tenth-micron self-aligned-gate CMOS

16 process with up to five metallization levels. The transition from dopant diffusion to ion implantation, from thermal oxidation to oxide deposition, from a metal gate to a poly-silicon gate, from wet chemical etching to dry etching and more recently from aluminum (with 2% copper) wiring to copper wiring has provided vastly superior analog and digital CMOS circuits [8].

Figure 2.1 Cross section of a Metal Oxide Semiconductor FET [8]

As figure 2.1 shows, complementary Metal-Oxide-Silicon circuits utilize both NMOS and

PMOS transistor technology fabricated on the same substrate. To this end, an n-type well is provided in the p-type substrate. Alternatively one can use a p-well or both an n-type and p- type well in a low-doped substrate. The gate oxide, poly-silicon gate and source-drain contact metal are typically shared between the PMOS and NMOS technology, while the source-drain implants must be done separately. Since CMOS circuits contain PMOS devices, which are affected by the lower hole mobility, CMOS circuits are not faster than their all-NMOS

17 counter parts. Even when scaling the size of the NMOS devices so that they provide the

same current, the larger PMOS device has a higher capacitance. The CMOS advantage is that the output of a CMOS inverter can be as high as the power supply voltage and as low as ground. This large voltage swing and the steep transition between logic high and low yield large operation margins and therefore also a high circuit yields.

In addition, there is no static power dissipation in either logic state. Instead the power dissipation occurs only when a transition is made between logic states. CMOS circuits are therefore not faster than NMOS circuits but are more suited for very/ultra large-scale integration (VLSI/ULSI). CMOS circuits have one property, which is very undesirable,

namely latch up. Latch up occurs when four alternating p and n-type regions are brought in

close proximity. Together as shown in figure 2.1, they form two bipolar transistors, one

NPN and one PNP transistor. The base of each transistor is connected to the collector of

the other, forming a cross-coupled thyristor-like combination. As a current is applied to the

base of one bipolar transistor, the current is amplified by the transistor and provided as the

base current of the other one. If the product of the current gain of both transistors is larger

than unity, the current through both devices increases until the series resistances of the

circuit limits the current. Latch up therefore results in excessive power dissipation and faulty

logic levels in the gates affected. In principle, separating n-type and p-type device can

eliminate this effect. A more effective and less space-consuming solution is the use of

trenches, which block the minority carrier flow. A deep and narrow trench is etched between

all n-type and p-type wells, passivated and refilled with an insulating layer.

18 2.4.2 BIPOLAR AND BICMOS PROCESSES

BiCMOS technology is a combination of Bipolar and CMOS technology. CMOS technology

offers less power dissipation, smaller noise margins, and higher packing density. Bipolar

technology, on the other hand, ensures high switching and I/O speed and good noise

performance. It follows that BiCMOS technology accomplishes both - improved speed over

CMOS and lower power dissipation than bipolar technology. The main drawback of

BiCMOS technology is the higher costs due to the added process complexity. Impurity

profiles have to be optimized to both NPN and CMOS issues. This greater process

complexity results in a cost increase compared to conventional CMOS technology.

Figure 2.2 Simplified cross section of BiCMOS process realization of NMOS, PMOS and N-P-N device [9]

19 As figure 2.2 shows, the P+ substrate is replaced by a P- substrate material to incorporate

the NPN device into the N-well of the PMOS device. This lower doped substrate increases the susceptibility for latchup. To improve latchup immunity retrograde N-well doping is used. The retrograde doping can be either achieved by high energy ion implantation or by using buried layers. With the first approach no epitaxial layer is required, but ion implantation damage has to be considered. By using buried layers a relatively thick and expensive epitaxial layer has to be grown on top of the substrate. This epitaxial layer hosts the collector of the NPN as well as the P-well and the N-well of the

CMOS devices. The epitaxial deposition process must be optimized to reduce material defects and minimize autodoping.

Due to the usage of the buried layers the well drive-in has to be optimized for bipolar collector requirements. From the bipolar point of view the collector profile should consist of a thin heavily doped collector region (buried N+ layer) and a thick lightly doped collector region on top. The first one minimizes the Kirk effect, where the second one ensures higher

collector-base breakdown voltage. The CMOS device on the other hand requires a

sufficiently high concentration below the surface to avoid punchtrough, especially as device

dimensions are shrinking. Practically, the various conflicting requirements have to be

balanced. This leads to steeper collector N-well profiles which cause an increase of the

collector series resistance. To improve the collector series resistance a deep subcollector N+

diffusion is used.

Finally, the same polysilicon material is used for the fabrication of the NMOS and PMOS

gates as well as for the bipolar polysilicon emitter. The doping for the emitter junction is

usually provided by a N-type implant into the polysilicon, which forms the emitter-base

20 contact during the source-drain anneal of the CMOS device by outdiffusion. The N-type

polysilicon gates result in a surface channel NMOS device and a buried channel PMOS

device.

The major process decisions when a BiCMOS device is designed can be classified as follows:

• Type of N+ buried layer

• P epitaxial layer design

• Choice of isolation technique

• CMOS well and bipolar collector design

• Bipolar polysilicon technology

The N+ buried layer is typically the first doping related process step in BiCMOS technology

and, hence, the thermal budget associated with this process does not affect the later fabricated CMOS devices. Generally, arsenic or antimony can be chosen for the N+ buried layer implantation. Antimony has the advantage of exhibiting less autodoping during epitaxy and the following heat cycles, but has a lower solubility limit compared to arsenic, which necessitate higher anneal temperatures to activate the antimony.

Vertical and lateral autodoping effects must be considered for N-well and P-well regions during the epitaxial growth of the EPI-layer to achieve shallow well profiles . Otherwise excessive counterdoping has to be performed.The redistribution of the boron P+ buried layer doping can be controlled by the epitaxy process temperature.

An accurate approach is required for the isolation technique of the active device regions, since standard LOCOS technology encroaches to much active area. It is also of vital importance to keep the thermal budget as low as possible for BiCMOS technology to preserve the buried layer dopings. To limit the active area encroachment a poly buffered locos

21 (PBL) [10] technique is suitable. The polysilicon serves as additional stress relief layer and

allows the usage of thicker nitride layers, which reduce encroachment . The PBL technology

can still be used for 0.5 micron BiCMOS technology , but moving towards smaller feature

sizes requires trench isolation. An oxide-isolated polysilicon filled trench penetrates the N+

buried layers between the PMOS and NPN device to minimize sidewall capacitance and to

prevent latchup. A compromise is required for the design of the wells in BiCMOS

technology to include the bipolar device requirements . Compared to conventional CMOS technology N-well and P-well exhibit a steeper gradient for the above presented twin-well fabrication process. This leads to a higher collector series resistance. However, a deep N+ diffusion is typically used to provide a low resistance path to the N+ buried layer. For the

CMOS devices sufficient N-well doping at the field oxide-silicon interface is required to provide adequately field oxide threshold voltages for the PMOS transistor. Generally, several approaches for the BiCMOS well design can be found in literature .The single-polysilicon non-self-aligned bipolar transistor presented above can be changed into a double-polysilicon emitter-base self-aligned NPN transistor with considerable small increase in process technology. This change results in a smaller base resistance, a lower base-collector capacitance and a higher cut-off frequency.

2.4.3 HIGH VOLTAGE CMOS TECHNOLOGY

During the past two decades several approaches have been explored in the development of

the high voltage integrated circuit design. Typically two approaches have taken prominence.

One approach involves starting with an optimized high voltage device structure and building

low voltage control devices around it .The other approach involves starting with a low

voltage CMOS technology and incorporates high voltage devices around it [11]. The first

22 approach has gained more prominence. The low voltage devices are typically bipolar and

CMOS but involves minimizing the total mask count, process complexity and hence leading

to cost effectiveness.

One of the most important criteria during the design of high voltage IC’s is to prevent

circuit interaction between key components in the design. Basically there are 3 types of

isolation techniques involved. The bipolar processes involve junction Isolation, CMOS

processes involve self-isolation and the SOI (Silicon on insulator) involves dielectric isolation

scheme. Most attention in the industry has been towards the self-isolation [12] and junction

isolation techniques. There are four voltage ranges considered. They are voltages: < 50V; 50-

100V; 100-150V; and above 500V. This commonly employed technology in the industry include electronic ballasts for fluorescent lamp, automotive electronics etc. The problems associated with the high power involve its cost and limited purpose application. Its been observed that PIC (Power Integrated Circuits) have a cost 5 –10 times more than corresponding discrete and electromechanical solutions [13]. Secondly, with the advances in device physics and technologies, cost of discrete power devices has decreased rapidly resulting in severe competition for the PIC’s. Thirdly, only a limited number of special purpose applications have been explored and general-purpose high volume standard products such as a memory chips in conventional IC’s has not emerged.

2.5 SUMMARY

Most of the technologies described in this chapter have been incorporated in this field of

research. Some common features of the previously described results are worth discussing. As

the smart silicon and the silicon carbide device are designed as separate components, one

23 finds that a great deal of creativity has been applied in implementation of both the devices.

The essence of this research deals with the design and the implementation of the smart silicon. Thus, more emphasis is given to silicon chip rather than silicon carbide device. For the details of the silicon carbide design see Reference [14]. Indeed it is appropriate to note that extremely high performance silicon module is possible only if adequate technology is implemented. The silicon design requires a CMOS design involving various areas of research including optoelectronics, digital circuits and analog VLSI. Effort has been made to optimize the device and incorporate photodetector structures into a conventional CMOS fabrication.

As research indicates, groups are working to integrate this technology into the mainstream of microelectronics industry.

24 CHAPTER 3

SIMULATED SILICON DEVICE STRUCTURE

This chapter describes the various components analyzed during the design of the silicon

chip. It incorporates analysis, design and simulations of the individual components.

3.1 PHOTODETECTORS

3.1.1 TECHNOLOGY OVERVIEW

Photodetectors structures are an integral part of an electro-optic system as they convert

optical power to an electrical signal. The photodetector receives the incident light and

converts it into a measured output response. An example of a visible radiation detector is

one that produces a current as a result of visible radiant energy striking its surface. The

optical source under observation may produce a transient optical signal for a short duration, nonrecurring event or a repetitive phenomenon. One of the main considerations in building a system to record the signal from such a source is the choice of a proper detector to meet

certain requirements. In choosing an optical detector, we must consider many factors that

may influence the measurement. Manufacturers of photodetectors have in general followed

international standards of measurement in describing these characteristics. Some of the more

important characteristics will be defined and described in this chapter. The design of the

photodetector can be implemented in various methods by using the CMOS process design.

The application specific nature of the photodetector is key to its design.

25 The different types of photodetectors are vacuum-tube devices, semiconductor photodiodes, semiconductor photoconductive devices, thermocouples etc. The choice of a particular detector depends on the requirements of a specific application. These include the wavelength of the light, the sensitivity needed, the speed of response required, and so forth.

Wavelength is especially significant because many photodetectors respond only in certain parts of the optical spectrum. There are several other properties like Responsivity, Spectral response, Quantum efficiency etc. To understand the descriptions of detector performance and to be able to pick a detector for a specific application is a part of the research goal.

Operation of a photodetector depends on its speed. The speed on the other hand relies on the diffusive transport of the carriers, generated in the silicon substrate. It is been observed that the carriers develop a slow fall time during the impulse response. In a photodetector, the surface generated electric field has to penetrate deep into the surface leading to a generation of number of photo carriers. The design should take into account the doping level of the substrate. Research indicates that a number of photodetector have been designed such as BICMOS design, MSM structures and CCD’s. The following section discusses in detail the operation of the photodetector incorporated into the chip design.

3.1.2. SELECTED DEVICES

The photodetectors analyzed for the design of the smart silicon chip are:

• P-diffusion to N-well Photodetector

• N-Well to P-substrate Photodetector

• P-diffusion to N-well and N-well to P-substrate Photodetector

• BJT Phototransistor

Photodiode Dark Normalized Normalized Rise Fall Structures Current Responsivity Responsivity at Time Time A/µm2 at 853nm (A/W.µm2) (ns) (ns) 632.6nm(A/W. µm2) N-well to P- 0.1e-12 0.0196 0.0179 <0.2 15 substrate P-diffusion to 0.5E-13 2E-3 6.4E-4 <0.1 <0.1 N-well Combined 0.1e-12 0.032 0.0315 <0.1 15

Phototransistor 1.60e-12 6.9 5.1 500 850

Table 3.1 Simulation results of all the photodetector structures.[13]

As table 3.1 indicates, from the general evaluation comparison between the photodetector it

is inferred that the P diffusion to N-well photodiode has fastest speed. Hence, the following

section describes, the photodetector incorporated in the design of the silicon chip.

27 3.1.2.1 P-DIFFUSION TO N-WELL PHOTODETECTOR

N+ Guard Guard Ring Ring P +

N-Well

P - Substrate

Ground

Figure 3.1 P - Diffusion N -well structure [4]

This photodiode is implemented using P+ diffusion to N-well structure. The design is

implemented with number of p+ regions biased in parallel. As shown in figure 3.1, a reverse

bias voltage is applied across the P+ contact and N+ contact. Simulations have been

performed [13] using the MEDICI 2D semiconductor materials simulation software tool

[15] for various finger spacings. The incorporation of a guard ring in the circuit is to isolate the devices from each other [16]. Simulations also indicate that there is a weak photo response due to the shallow nature of the diode and long absorption length of Si, (around

15u at 850nm) where almost all the light is absorbed deep inside the substrate.

Simulation of spectral responsivity indicates an increase in the responsivity with the increase in wavelength until it reaches a value of 850nm and decrease there after. When the wavelength increases significantly, photo generation takes place in the substrate decreasing

the photocurrent and thereby reducing the responsivity.

Figure 3.2 Layout of a P-diffusion N-well photodetector

The P+ to N-well photodiode is implemented with a fingered design as shown in figure 3.2. using the Magic layout tool [17].In the layout design of this photodiode, the number of fingers and the finger spacing are important design criteria. An increase in the number of p+ fingers results in an increase in the active device area. In addition, the photocurrent is slightly higher when the finger spacing is close to the depletion width region of the p-n junction.

Photo current Vs Finger Spacing

8.00E-09

7.00E-09

6.00E-09

5.00E-09

4.00E-09

3.00E-09 Photocurrent (A/micron Photocurrent 2.00E-09 1234567 Finger Spacing (micron)

Figure 3.3 Photocurrent vs Finger Spacing curve [13]

As shown in figure 3.3, the photocurrent decreases at 3-4 µm and increases thereafter until

7-8µm and is almost constant (beyond which the diffusion length of diodes are far apart

29 from each other). Hence, we can achieve maximum photocurrent by having the fingers

spaced 7-8 µm apart from each other.

Figure 3.4 Transient Response of P-diffusion N-well photodetector [13]

As figure 3.4 shows, the simulated P-diffusion N-well photodetector’s transient response.

The transit time required moving the carriers to the P+ to N+ contact regions is small. Also

the fall time is due to very short time for the carriers being swept out of the N-well region.

While free carriers are being generated deep in the silicon substrate, the reverse biased N- well to P-substrate diode effectively prevents these carriers from contributing to the photocurrent flowing through the P+ contact.

30 3.2 PHOTORECEIVER CIRCUIT

3.2.1 TECHNOLOGY OVERVIEW

The ability to produce high performance photoreceiver’s integrated into the CMOS

technology enables greater use in the field of optoelectronics industry. Receivers for this application have to be compatible with the photodetector and the high volume CMOS process [18]. Fully integrated high performance monolithic silicon based photoreceiver have

had significant impact in the optical telecommunications industry. Ability to realize a high

performance silicon based photodetector/photoreceiver in a production of a CMOS process is a challenge to design engineers. The challenge lies in combining an optical device in with an electronic component on a common silicon substrate. There have been a number of photo receivers implemented for various applications. Low cost, high-reliability, and high- performance photo receivers are essential to support the growth of 780–850-nm applications. The application of photoreceivers in several optical applications has led to an increase research in this field. Hence high cost of fabricating photoreceiver implemented in

III–V materials, which have long been used for high-performance long-haul communications systems, prevents their acceptance in these new applications [19].

Hybrid schemes that employ III–V photodetector bonded to silicon circuitry provide an alternative, but the processing is more complex and cost will probably still be excessive.

Today, silicon MOS technology provides a very encouraging option to implement monolithic photoreceiver for various applications. The most challenging aspect of fabricating a high-performance monolithic silicon MOS photoreceiver is to implement a photodiode structure with the required performance without adding complexity to the

31 existing process flow and compromising the electrical performance of the chip. Recently, silicon-on-insulator (SOI) technology has been attracting more attention from both research institutions and industry. Various top silicon layer thickness, ranging from a few hundred nanometers to several micrometers, are commercially available. By carefully choosing the

SOI substrate, high-speed detectors with reasonable responsivity can be fabricated. There have been several reports of photodiodes fabricated on SOI [20]-[21]. However, only one group has reported an integrated SOI photoreceiver, which was fabricated on a 50-nm-thick

SIMOX substrate [21].

3.2.2 SELECTED APPROACH

The function of the photoreceiver is to amplify small signals in either voltage or current variable. The photoreceiver incorporated in the design of smart silicon has an operating range of 0-15 volts and hence application specific.

Figure 3.5 Photoreceiver circuit design

32 As shown in figure 3.5, the photoreceiver consists of a photodiode and a two-stage

amplification circuit. The optical input is approximately 1mW, responsivity of the

photodetector of 0.02A/W producing a current of 20uA. The voltage swing is from 15 V to

ground . Transistor M1 acts as an active load turning the photocurrent into a voltage level.

The transistor M1 has a length and width dimensions of 15 um and 4 um respectively. The dimensions of the active load were determined by detail analysis using SPICE simulations.

After the load transistor M1,the circuit uses 2 push pull amplifiers produce an output voltage

swing from ground to the power supply. The sizing of the the PMOS tansistors and

NMOS transistors is critical to achieve the maximum voltage swing. The push pull amplifier consists of two transistors connected in an inverter confirugation. When the optical signal is

OFF the voltage across Node C in figure 3.5 is low. When the optical signal is turned ON

the output swings to Vdd.

Figure 3.6 Push Pull Amplifier Design [22]

15.00 14.00 13.00 l2 w22 12.00 11.00 l2 w11 10.00 l2 w6 9.00 8.00 l2 w3 7.00 l3 w3 6.00 5.00 l5 w3 4.00 no fet 3.00 2.00 1.00 0.00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Figure 3.7 Analysis of different sizing of Pmos load transistor

As figure 3.7 shows, the sizing analysis of the device where the sizing of the inverter stage is

essential when designing a push pull amplifier. The PMOS transistor has a length of 9

microns and a width of 3 microns while the NMOS transistor has a length of 3 microns and a width of 3 microns. To obtain a transition at the output of the photoreceiver, the sizing of the PMOS load M4 and M7 is important. Simulations indicate that to obtain a stable output, those transistors should have a length of 5 um and a width of 3 um for 2-stage push pulls amplifier design. In the figure “no fet” refers to ideal resistors. As described earlier the amount of optical power shown on the device is 1 mW and the responsivity of the photodiode is of 0.02A/W. Ideally the amount of current produced by the photodiode is

20uA.

Figure 3.8 Simulation results of the photoreceiver circuit

As figure 3.8 shows, when the optical power is concentrated on the photodiode and a output transition from ground to Vdd occurs at 20uA. The simulation indicates three curves corresponding to voltage values at Node A, B and C.

Figure 3.9 Simulations showing the Tplh delay

35 Frequency response figure of merit of the photoreceiver circuit. The frequency response

(Ft) is calculated by using equation 3.1 .

Ft = 1/(Tplh + Tphl) ------eq (3.1)

The delay in a circuit is directly propotional to the load capacitance, inversely propotional to the supply voltage and transconductance values .Simulation results in figure 3.9 indicate that the value of Tplh is 1.53ns.

Figure 3.10 Simulations showing the Tphl delay

Simulations shown in figure 3.10 the value of Tphl is 1.73ns . Hence the frequency response

of the simulated photoreceiver is 0.31Ghz.

Figure 3.11 Power Dissipation in the photoreceiver circuit

Power consumption is a major issue in CMOS devices. As figure 3.11 shows, the average power consumed by the component is constant ~14.5 mW . This relative large power

consumption is explained by the fact that there is a direct path between Vdd and ground due

to the presence of the load transistors M4 and M7.

3.3 CURRENT SOURCE AND SINK CIRCUITS

3.3.1 TECHNOLOGY OVERVIEW

The current sink and source’s are fundamental building blocks of analog circuit design.

Although bipolar circuitry could be used, CMOS mirrors and gain stages have been

emphasized because modern mixed signal designs typically depend on this approach. A

current sink or a current source is a two terminal component whose current at any instant is independent of the voltage across its terminals. When a MOSFET operates in the saturation region, it behaves as a current source. For high performance analog circuit applications, the accuracy and the output impedance is the most important parameters to determine the

performance of the current source and sink [23]. Although CMOS process have become

dominant in applications requiring large amount of digital circuitry on the chip, BJT circuits

in either BICMOS or bipolar processes remain popular for high speed applications due to

very high unity gain frequencies attainable with modern bipolar transistors. Unfortunately, in

bipolar transistors, the base control terminal draws a non-zero current. Specially, for lateral

transistor, the base current in some processes may be large as 20%. So to avoid the use of

the bipolar process altogether the analog CMOS community is trying to innovate a

technology where a conventional FET’s can replace the bipolar circuits.

Another compelling reason for current-mode circuits is decreasing power supply voltage

for digital microelectronics thus making it suitable for mixed signal mode applications. In

analog circuit design, the current mirror is widely used in biasing or loading elements. In the

38 configuration, current sources and sink can reduce the current variation due to power and temperature variation. The two important factors that determine the operation of a current mirror are accuracy and output impedance parameters. Recent researches in this field have focused on cascode current mirrors and RGC current mirrors [24] that increase the output impedance.

The operational accuracy of the current mirror is highly dependent on the matching of the transistor pair [25]. However, the transistor mismatch resulting from a non-uniformity of the physical parameters in silicon is unavoidable. As a result, designs of the current mirrors involve detail analysis. In addition, the current flowing through the transistor heavily depends on the mode of operation of the transistor. If the transistor is operating in the weak inversion region, the mismatch could cause significant malfunctioning of the circuit.

Therefore, various compensation techniques have to be incorporated in the layout design.

In this section, we discuss in detail the circuit design of the current source and sink component.

39 3.3.2 SELECTED DEVICES

3.3.2.1 BASIC CURRENT SINK

The basic current sink schematic used in the design is shown in figure 3.12. The design of the current sink only involves NMOS transistors .The current flows through the transistor

M1 that has a corresponding gate voltage of VGS. Transistors M1 and M2 have the same

gate voltage hence ideally the same current flows through the devices. For equal amount of

current to flow, the transistors M1 and M2 must operate in the saturation region. In the

analysis , the body effect and the channel modulation have been ignored . Equation 3.2

describes the relationship between the current ID1 and ID2

I D2 β2 W2 L1 = = Equation 3.2 I D1 β1 W1L2

Figure 3.12 A basic current sink schematic [22]

40 As indicated by the equation, the current flowing through both the transistors depends on

their respective widths and length sizing. Finally, the value of the current ID1 is set by the setting the resistor value and the power supply voltage.

3.3.2.2. BASIC CURRENT SOURCE

Figure 3.13 A basic current source circuit [22]

The basic current source schematic incorporated in the chip design is shown in figure 3.13.

The design of the current source only involves PMOS transistors. The analysis is similar to that illustrated of the current sink, where the current flowing through the device depends solely on the device dimension assuming no body effect or channel modulation occurs.

The other factors that play an important role in the design are threshold voltage variations, process parameter variations and the channel modulation variations. As a result, it’s

41 important for the designer to concentrate on only known parameters during initial phase of

the design and later consider the parametric variations.

3.3.2.3. CASCODE CURRENT SOURCE

Figure 3.14 A cascode current source circuit

With the basic building blocks described in the earlier sections, the cascode current source

shown in figure 3.14 is designed to obtain a stable output current over a wide range of

operational voltage [25]. The basic configuration consists of a common source connected

with a common gate transistor. A regulated cascode current mirror is used to increase the

output resistance of the current source. As a result a constant current flows (Isource) when the transistor’s are operating in the saturation region. The magnitude of the current flowing through the current source is controlled by the input bias potential and the sizing of the

transistor.

42 There are two main reason for the popularity of cascode stages. The first is that they can have a large gain for a single stage due to the large impedance at the output. To enable this high gain, the current sources connected to the output nodes are realized using the quality current mirror design. Normally the high gain is obtained without any degradation in speed.

The second major reason for the use of the cascode is that they limit the voltage across the input drive transistor . This minimizes any short channel effects which becomes more important with modern technologies having very short channel transistors.

43 3.3.3. SIMULATION OF THE CURRENT SOURCE

Figure 3.15 Simulation of the output current (I source)

As shown in figure 3.15, an input bias voltage is swept from 0 – 15 volts resulting in the change in the output current . Keeping the supply voltage at 15 V, the output current is seen to vary from 0uA to 72 uA. For the proper operation of the current source , the source transistor has to be in saturation . Simulations show that the change in the dimensions of the transistor leads to change in the current .

Figure 3.16 Simulation showing the operation of the current source

As figure 3.16 shows that when the input voltage bias to the current source is 15V the

current Isource is ~ 70uA , when the bias is 0V then source current Isource drops to ~0uA.

45 One of the major issues associated with the analog circuitry is power dissipation. As discussed earlier, the change of the bias voltage changes the operational behavior of the device. As shown in figure 3.17, when the input voltage is swept from 0 to 15 volts, the output power follows the current curve. The power results indicate that the maximum power dissipation is 8.0 mW while the average power is 4.4 mW. The leakage current associated with the current source circuit is 0.41 pW.

Figure 3.17 Power dissipation curve

46 3.4. BIPOLAR JUNCTION TRANSISTOR

3.4.1. TECHNOLOGY REVIEW

The bipolar transistor is the backbone of analog semicustom design. Most semi-custom

analog arrays are made with a bipolar process. Although some vendors often offer JFET's

on some arrays, the vast majority of active devices found on the analog semicustom arrays

are NPN and PNP transistors. Bipolar transistors have excellent output driving capability

and can be readily ratioed and scaled by simply paralleling devices. Also the frequency ranges

from 300 MHz to a more than a GHz, depending on the process and manufacturer.

In recent years standard analog bipolar processes have been designed to satisfy the

requirements of matched pair NPN transistors for the telecommunication and high voltage applications. Since the process is a complete BJT process, the degree of matching of various device characteristics are dependent on collector current, temperature and layout design dependent. Protection diodes and biasing resistors are also integrated for demanding custom applications. The analog bipolar process for matched pair NPN transistors employs N type silicon epitaxial layer on P type silicon substrate. In the standard process up to 8 masks are used [26]. They are the buried layer (sub collector), isolation, base, emitter, contact mask, thin film resistor mask, metal mask, pad mask. As process options are made available with the analog bipolar process, process option-enhancements are added to increase the integrated circuit designer's flexibility in designing with analog bipolar process.

The process employed to integrate a bipolar with the CMOS process is termed as BiCMOS.

For mixed signal application, the full swing BiCMOS outputs allow unrestricted mix of

CMOS and BiCMOS core cells and interfacing capability. The technology offers a high

47 driving capability and also with fully differential ECL cell design noise immunity [27]. The

circuit design of the silicon chip incorporates a bipolar CMOS process. This section deals with the design, simulation and analysis of the BJT structure.

3.4.2. DEVICE ANALYSIS

Vdd

Input Ground Current to SiC signal

Current to sink Figure 3.18 Circuit diagram of the BiCMOS circuit

As described earlier, the silicon carbide device must produce a stable 150 A of drive current.

Thus, it is necessary to drive the SiC Darlington pair with a stable current drive source. As shown in figure 3.18, the CMOS circuit that is used to provide a stable 15 mA drive current in the ON state and a constant sink current in the OFF state. As suggested in figure 3.18, the circuit has three major components: a dual port current source, a pair of Bipolar Junction

Transistors, and a current sink for discharging both transistors in the Darlington Pair

The current generated by each output port of the current source is driven into the base of a bipolar junction transistor (BJT) that is biased in a common emitter configuration. The

48 BJT’s are used for their high current capability that leads to an increase in speed when

driving large capacitive loads and a decrease in problems associated with noise. A BiCMOS process is used to fabricate the device. A vertical NPN BJT is implemented which uses the n-well as a collector, a p-base diffusion for the base and the n+ implant for the emitter.

From the drive circuit shown in figure 3.18, a 70uA current flows into the base of each BJT

producing ~7.5mA flowing out of each BJT emitter. The total current from the two BJT is

15 mA that is sufficient drive current to produce 150A from the SiC Darlington pair.

Finally, as shown in figure 3.18, two PMOS transistors are used to control the Darlington

pair discharge path. By connecting the bases of both Darlington transistors to a current

sink, it is possible to insure that the switch can be turned OFF quickly. With out a

mechanism for removing charge from the bases of the Darlington transistors, the frequency

characteristics of the switch would slowed by long tails in the turn-off phase. To prevent the discharge path from affecting the ON characteristics of the switch the PMOS transistors is

controlled by the same voltage that is used to control the dual port current source. Thus,

when the current source is ON, the PMOS transistors are turned off and the source current

is driven through the BJT’s to the SiC Darlington. When the current source is OFF, the

PMOS transistors are turned ON and the current sink pulls charge out of the bases of the

Darlington transistors.

49 3.4.3. SIMULATIONS OF THE BIPOLAR JUNCTION TRANSISTOR

The circuit symbol of the NPN transistor with current and voltage polarities marked is shown in figure 3.19.

Collector + Base + VCE IB VBE IE - Emitter

Figure 3.19. Circuit of a NPN BJT

The characteristic curves of BJT are only helpful in studying the behavior of the transistor but also in determining the region of operation for the transistor. As operation of the transistor should be in the cut off or the forward active region, the design must application specific. In the active region, the collector current is independent of the value of the collector voltage and hence the transistor behaves as an ideal current source where the current is determined by VBE. Hence, the BJT should be operating in either cut off of forward active region.

Figure 3.20 Ic vs. Vce Curve for Ib = 70uA

As figure 3.20 shows, the simulated Ic vs. Vce characteristic of the bipolar junction transistor. The output is measured by sweeping an input current at the base of the BJT ranging from 0-70uA. The results from the simulations indicate a current of 7.5 mA flowing from an identical single BJT.

Figure 3.21 Output current from the BJT stage

51 As shown in figure 3.18, the two BJT‘s emitter are connected in parallel. Hence the total current flowing out of the bipolar stage is the sum of the individual stages. As figure 3.21 shows, the total current flowing out of the stage is 15 mA .

Figure 3.22 Power Analysis curve for the BJT stage

As figure 3.22 shows, the maximum power dissipated by the BJT stage is 450 mW. The total power dissipated is the product of the supply voltage and the drawn current. The value is greater than expected because combining the BJT with the other stages increases the power consumption.

3.5. DETECTION CIRCUITS

In addition to the drive circuitry, the silicon chip has several circuits which monitor the

operating conditions of the switch .The basic function of these circuits is to detect when

failure in a motor drive controller that might lead to a potentially fatal over biasing condition

for the switch itself .If a failure condition is detected the switch is then disabled. There are

three detection circuits

3.5.1 OVERIDE CIRCUIT

3.5.1.1 CIRCUIT ANALYSIS

Figure 3.23 Override circuit

The override circuit shown in figure 3.23 provides the user with the control option. The

input to the overide circuit is an optical and a overide signal. The optical signal refers to the photoreceiver output and the overide signal is the user control input signal .

53 3.5.1.2 SIMULATION OF THE OVERRIDE CIRCUIT

Figure 3.24 a) Input Override Figure 3.24 b) Optical Input

Figure 3.25 Output override signal

As figure 3.25 shows, the output override signal goes low if the input override is high, hence shutting the circuit off. As the results show the override output does not depend on the input optical signal. As the override circuit is a digital circuit, minimum size transistors were incorporated during the design.

54 3.5.2 VCE SHORT CIRCUITRY

3.5.2.1. CIRCUIT ANALYSIS

Figure 3.26 Vce short circuit circuitry

Failure of the SiC power transistors results in a short circuit condition that can be detrimental to both the silicon chip and the motor control system .This condition is detected by comparing the collector emmiter voltage of the SiC device to 12 V. When the SiC

Collector-Emitter voltage exceeds 12 volts for more than a few usec, a failure condition is recognized. As figure 3.26 shows, the smart silicon consists of a comparator circuit used to monitor the system for short circuit failures.

55 3.5.2.2 SIMULATION OF THE SHORT CIRCUITRY

Figure 3.27 Simulation results of the short circuit circuitry

The12 Volt supply was designed using a voltage divider , and is swept from 0-15 volts. In the design of the MOSFET only voltage divider , the designer has an option to only change the dimension of the transistor to generate a voltage reference. As shown in figure 3.27, at

12 volts the output falls to zero volts hence isolating the silicon with the silicon carbide. The time delay is 1 microsecond hence resulting in the isolation of the smart silicon with the silicon carbide .

Figure 3.28 Power variation curve

The change in the output of the vceshort circuit leads to the change in power consumption of the circuit. As figure 3.28 shows, as the output decreases the power also decreases.

Simulation result show the average power consumed by the circuit is 18 mW.

57 3.6 PAD AND PAD-FRAME DESIGN

3.6.1 OVERVIEW

The bonding pad is at the interface between the die and the package or the outside world.

Physically, pads are the squares of metal, generally 100-150 ohm square, that are connected

to the pins of the package with bonding wires. The word pad is often used to also include

the circuitry that is used to interface the CMOS logic within the IC (typically composed of

near minimum-geometry transistors) to the outside world. Pads in the circuit will be used to

connect the chip to the VDD and VSS power supply lines, while other pad is used for input

connections and output connections. Some pads may also be required to be bi-directional,

(for use both with input signal and output signals). In such cases there is usually a control

connection to determine the direction of signal transfer. The analog pads are used for analog

or mixed signal circuit design. An important function for all pad driver circuitry is the

protection of the chip circuitry against destruction due to over voltage pulses or sustained

over voltages. These may be due to electrostatic discharges or due to faults on other circuitry that cause unexpectedly high voltages to be applied to the chip pins.

Bonding pads are normally positioned near to the chip edge, although there is often a VDD

bus between the bonding pads and the chip boundary. Pad circuitry is designed for various

circuit blocks have standard physical sizes and provide regular spacing of the bond pads

around the chip when the blocks are abutted [28]. It is seen that continuous substantial

aluminum interconnect is provided to form separate VDD and VSS buses around the ring

of pads at the periphery of the circuit. These buses supply the current required by the pad

drivers, and, in small designs, may also supply power to the inner circuitry. The necessary

interconnections and crossovers are greatly facilitated by the use of double-layer metal. Pads

58 and pad driver circuitry are a major consumer of chip area and any lack of compactness here

will produce serious inefficiency in the total use of silicon area. Regular spacing of the

bonding pads is normally required to facilitate the actual bonding process, the precise pitch

and positioning being specified by the designer. For designing a mixed signal circuit, a mixed signal pad frame is required. The silicon chip consists of both the analog and the digital signals hence a hybrid pad frame was designed. The following section illustrates the pads required in the design of the hybrid pad frame.

3.6.2 SELECTED PADS

3.6.2.1 VDD AND VSS PADS

The pads incorporated in the silicon chip pad frame are Vdd and Vss pads , the input pads

the output pads and analog pads .

Figure 3.29 a) Layout of the ground pad b) Layout of the Vdd pad

59 As figure 3.29 shows the pad design of the ground and Vdd. Although it is possible to introduce over voltages onto the chip via the supply connections, it is not feasible to provide any form of protection on these lines. They are, in any case, less sensitive to over voltage than the signal connection. The important considerations for the supply connections are the current requirements of the chip. There is an advantage in using multiple power supply pads, if the area is available, because this reduces noise levels. For an adequate pad design the voltage drops should be within acceptable limits. Also the current density must be below the level that causes electro migration in the aluminum. This phenomenon can give rise to gaps in power buses unless the current density is kept below about 1mA/um.

3.6.2.2 INPUT PADS

Figure 3.30 ESD Protection Circuitry

Input pads always contain over voltage protection features, but can also contain inverting circuitry or Schmitt trigger circuitry if the input signals to be fed to the circuit are not known to be proper CMOS level signals. The capacitance of the gate is also very small, so sufficient electrostatic charge can easily be accumulated to produce a voltage high enough to cause

60 failure of the input transistor. The usual protection circuit consists of a resistance and diode clamps, as shown in figure 3.30. D1 will turn on if the voltage at X rises significantly above

VDD; similarly, D2 clamps the potential close to VSS if X is driven negative. The resistor R is normally a parallel (pdiff and ndiff) track of about 150 ohm and this is used to limit the maximum current that can flow through the diodes (in the event of the diode turning on) to a non-destructive level.

Figure 3.31 Layout of input pad circuit

The layout of the input pas is shown in figure 3.31. As the figure shows, the presence of protective circuits closely packed with each other .The protection circuits should have a capability of about 2kV and 8 kV capabilities are possible with careful design without unreasonable degradation of the speed of the circuit [29].

3.6.2.3 INPUT /OUTPUT PADS

PAD

ENABLE

R = 150 ohms

ENABLE ENABLE IN_ unbuffered

OUT

Figure 3.32 Circuit design of an I/O pad [30]

Input - output pads as shown in figure 3.32, must be capable of providing relatively large currents for off-chip wiring, perhaps the inputs to several other devices. This is done with minimum expenditure of area and without slowing down signals to an unacceptable extent.

In general, the faster a circuit is required to run, the higher the output current drive capability must be because charge must be delivered more rapidly to the device being driven.

The driver circuit must act as a buffer so that changes in output loading do not affect the rest of the chip circuitry. Drivers are typically composed of logic inverters with high current drive capability. Often an even number of inverters may be connected in cascade if a non- inverting driver structure is required. The operation of the pad in figure 3.32 is described briefly].

• When enable (EN) is high (VDD), the OUT pin drives the output PAD.

• When enable (EN) is low (GND), the PAD is high-impedance

• Input IN_unbuffered (IN_unbuffered) always follows the PAD level

• Input INbar (IN) always follows the PAD level with 1 inversion

• Input IN always follows the PAD level with 2 inversions

3.6.2.4 ANALOG PADS

a) b)

Figure 3.33 a) Conventional analog pad b) Redesigned analog pad

As described earlier, the silicon chip has to source 15 mA of current . The conventional pad frames available with MOSIS [14] can only sustain 2mA – 3mA of current. The width of the metal line carrying the current in the pad as shown in figure 3.33a) is 3um. Hence the analog pads were redesigned to carry 15 mA of current from the bipolar junction transistor. The redesigned pad as shown in figure 3.33b) has a metal width of 20um allows increased current carrying capability.

CHAPTER 4

PERFORMANCE EVALUATION

This chapter describes the performance evaluation of the optically activated silicon chip.

Also included are layout design and comparison of the testing and simulation results.

4.1 TEST SET-UP

The testing of the silicon chip involves optical and electrical testing. The optical test bench set up is shown in figure 4.1. The figure shows a laser diode controlled by the laser driver (LD).

Laser Diode Cubicle Splitter Optical Power Meter P1 P3 LD Drive P2

Fiber Coupler

P4 Optical Fiber Detector/Receiver

Multi-meter Power Source Computer Lab VIEW Program)

Figure 4.1 Optical test set up for testing the silicon chip

64 The output power (P1) of the laser diode has a linear dependency on the driving laser current as shown in figure 4.2.

Power at various positions vs Laser Driving Current

1.20E-01

1.00E-01

8.00E-02

Power at 1 Power at 2 6.00E-02 Power at 3 Power at 4 power (2+3)

Power at Various Positions Positions Various at Power 4.00E-02

2.00E-02

0.00E+00 0.00E+00 2.00E+01 4.00E+01 6.00E+01 8.00E+01 1.00E+02 1.20E+02 1.40E+02 1.60E+02 1.80E+02 2.00E+02 Laser Driving Current

Figure 4.2 Power variations at different positions in the optical setup

In an ordinary beam splitter, the curve of power P2 and P3 does not follow the P1 at high laser drive current values. As a result to have a better linearity of the curve as shown in figure

4.2, a cubicle beam splitter is used. As shown in figure 4.2, input power (P4) on the silicon chip is half the input coupler power (P2). Summing up the power at the coupler (P2), the power on the chip (P4) and the approximated power losses, the total power is approximated to the laser power (P1).

Figure 4.3 Semiconductor Parametric Analyzer [31]

The electrical testing is performed with the Agilent 4155C and 4156C semiconductor parametric analyzers [31] as shown in figure 4.3. The advantage of using the parametric analyzer is with the functionality of the sweep analyzer, the instrument also is a reliability tester, a powerful failure analysis tool, and an automated incoming-inspection station built into it.

66 4.2 PHOTODETECTOR TESTING

Photodetector

Optical fiber

Elliptical output light

Figure 4.4 Photodetector testing set up

The photodetector structure as described in figure 3.1 is a P- diffusion N-well structure. The

area of the photodetector is 80 um squared. The input power to the chip is fed using an

single mode optical fiber. The output light from the optical fiber is circular in shape as

shown in figure 4.3. As a result during the testing, the detector window should be at close proximity the optical fiber so that the maximum optical power is coupled into the detector window.

Figure 4.5 Photodetector current vs. Optical input power [32]

Figure 4.3 shows the detector current vs. optical power characteristics for the P+ to N-well diode when illuminated with a near infrared light source (λ= 853 nm). The measured responsivity is 0.09 A/W. This is significantly below the theoretical maximum of ~0.3 A/W that is achievable for silicon photodiodes operating in the near infrared. The simulation results performed using the Medici software tool show, that the responsivity is .02 A/W. As a result the test results are significantly better than the simulation result for the same device structure but comparatively less than standard photo detectors available.

68 4.3 PHOTORECEIVER TESTING

Figure 4.6. Photoreceiver testing results

The measured photoreceiver characteristic is shown in figure 4.5.For this measurement,

Node A as shown in figure 3.5 was driven with a current source at a level similar to that of

the photo generated optical current coming from the photodiode. As shown in figure 4.5,

optically generated currents less than 90 uA produce negligible output voltage. For currents

greater than 90 uA (corresponding to an optical input power of ~1 mW) the photoreceiver output voltage increases linearly. A 1.9 mW optical signal illuminating the photodetector leads to a 170 uA optically generated current that produces a fully on output voltage from the photoreceiver. For currents greater than 170 uA, the photoreceiver output voltage is

fixed at the power supply voltage. The testing was performed at 10 V and 15 V. As shown in

the figure, the output results are consistent with different voltage sources.

69 4.4. CURRENT SOURCE TESTING

Figure 4.7 Testing results of the current sources

The circuit design as shown in figure 3.14 consists of 2 current sources. The current source testing was performed using a variable current source and analyzing the output results. As the circuit in figure 3.18 indicates, the current source control voltage is generated by combining the receiver output voltage with an override signal. When the over ride signal is

ON, the current source control voltage goes to the ground potential. When the override signal is OFF, the current source control voltage tracks with the photoreceiver output voltage. As figure 4.7 shows, the output current from one of the current source ports for both states of the override signal. The current generated by each output port of the current source is driven into the base of a bipolar junction transistor (BJT) that is biased in a common emitter configuration.

In figure 4.6, the current sources are sourcing different amount of currents. Current source1 sources 70 uA but current source2 sources approximately 100uA. Analysis performed indicates a problem in the layout design, where variable dimensions of the transistors has

70 lead to unequal current flowing out of the circuit [33]. The results indicate that the simulated current source and the tested values of the chip are nearly equal.

4.5 BIPOLAR JUNCTION TRANSISTOR TESTING

The function of the bipolar junction transistor is to produce 15 mA of current to the silicon carbide darlington pair transistor. The BJT layout is shown in figure 4.8, where the emitter and the collector have wider metal lines as it carries high currents. As the BJT is an analog component in the chip, it is laid out in a separate well to prevent unwanted coupling of signals between analog and digital components.

Base

Emitter

Collector

Figure 4.8 Layout of a bipolar junction transistor

As shown in Appendix 1,the output of the BJT is connected to an analog pads that has high current capabilities. The bipolar device is tested using the semiconductor analyzer. The voltage is swept at the collector keeping the emitter common. For different base currents the

71 collector current is measured. The BJT output curve as shown in figure 4.9 indicates that the device exhibits early breakdown at 3 V for various input base currents. Analyses of the BJT show that the problem is in the layout design. One end of the collector is connected to a voltage source while the other end is connected via the n-well to the ground. Hence there is a resistor between the supply and the ground which prevents the chip from proper operation. At low currents the BJT operates as required producing a gain of 113A/A hence matching the simulation results.

Figure 4.9 Ic vs. Vce curve of the bipolar junction transistor

72 4.6 DETECTION CIRCUITS TESTING

Failure of the SiC power transistors results in a short circuit condition that can be

detrimental to both the silicon chip and the motor controller that uses these optically

controlled high power switches to control a large electric motor. Since the controller uses

six switched to control drive current for a three phase motor, it is possible to use the

collector-emitter voltage across a working SiC Darlington pair to detect the failure of the other switches. As discussed in Chapter 3, the detection circuits incorporated in this chip are override circuit, a circuit for short-circuit-detection and current sink. The following section describes the testing results of these individual components.

4.6.1. OVERRIDE CIRCUIT TESTING

Figure 4.10 Output voltage curve with variable override conditions

The results in figure 4.10 shows the control voltage is generated by combining the receiver

output voltage with an override signal. When the override signal is high, irrespective of the

input, the output control voltage goes low. Under normal operating conditions, the input

override signal is low and the control voltage will vary with respect to the input optical

signal.

73 4.6.2. CURRENT SINK CIRCUIT TESTING

Figure 4.11 Output current with variable override conditions

As discussed in Chapter 3, the current sink is connected to the base of the silicon carbide by two PMOS transistors. These transistors are used to control the Darlington pair discharge path. By connecting the bases of both Darlington transistors to a current sink, it is possible to insure that the switch can be turned OFF quickly. With out a mechanism for removing charge from the bases of the Darlington transistors, the frequency characteristics of the switch would slowed by long tails in the turn-off phase.

As figure 4.11 shows, when the override signal is high, the current flowing out of the chip is negligible leading to the current sink turning ON hence sinking approximately 10 mA of current. As the override signal goes low, the silicon chip sources current hence the sink circuitry turns off.

74 4.6.3. SHORT CIRCUITRY TESTING

The testing results of short circuitry circuit could not incorporate due to electro migration problems in the layout design. The output value of the circuit was stuck up at a 10 V

irrespective of the change in input. As a result the test results have not been incorporated.

75 4.7. LAYOUT DESIGN

Detector

Override BJT Source

Short Circuit Sink Circuit

Figure 4.12 Layout of the Optically Activated High Power Silicon Chip

The silicon chip layout shown in figure 4.12 has dimensions of 1096 λ ×550 λ. The layout

shows various components incorporated in the design of the silicon chip. The chip is

designed using the MOSIS AMI 1.5 micron process using the model parameters as described in Appendix 1. The design was implemented on a 2.2mm squared tiny chip module.

76 4.8 LAYOUT OF THE CHIP INCORPORATED IN THE PAD FRAME

Figure 4.13 Design of the chip incorporated in a pad frame

77 CHAPTER 5

CONCLUSION

This chapter summarizes what has been achieved in out efforts in designing a high power optical switching device. It also characterizes CMOS based designs incorporating optoelectronics and BiCMOS design. The chapter outlines future work areas based on the conclusions derived from this work.

5.1 SUMMARY

As the chip is mixed signal in nature, the analog circuitry is the essence of a successful chip design. In a digital design circuits the primary tradeoff is between speed and power dissipation but analog design deals with multidimensional tradeoffs consisting of speed, power dissipation, gain, precision etc. As a result, second order affects in the analog circuit’s effect the device performance. Despite tremendous progress, modeling and simulation of many effects in the analog circuits continue to pose difficulties. As a result the design of the optically activated switch required analysis from circuit to the pad level design.

In this thesis, we have described the design, characterization and evaluation of a hybrid chip design that is suitable for use as an optically activated high power switch. The proposed device is well suited for application in Fly-by-Light avionic systems where optical control signals are used to drive the electric motors that actuate the flight surfaces of a modern aircraft. The hybrid device uses a SiC Darlington pair to provide a 150 A drive current.

78 A smart silicon chip that includes a photoreceiver, drive current circuitry, and diagnostic circuits necessary for detecting of short circuit failures has been fabricated using the AMI 1.5 micron MOSIS process. Initial test results have shown that many of the critical circuit elements are working. Demonstration of a 15mA drive current from the CMOS chip and full operation of the SiC Darlington pair have yet to be completed. Reporting on the fully function optically controlled high power switch is expected once the problems with these components has been overcome.

Presently, two components of the switch circuit are not working correctly. First, due to an error in the CMOS layout, proper operation of the silicon bipolar junction transistors prevents the smart silicon chip from driving 15 mA into the SiC Darlington pair. Second, problems with ohmic contacts on the SiC have prevented the demonstration of working SiC transistors. We are currently working to overcome these problems and expect to demonstrate a fully functional optically controlled high power switch in the near future.

This research is involves the design of an optical high power switch for specific application in fly by light systems. Based on the results obtained from the implementation the chip, a

designer could implement this chip for other applications. Unfortunately, the strategies used

to design the chip could be improved with a better design.

• The layout issues relating to current source circuit component where the two

current sources produce the same amount of current.

• The circuit design and layout issues related to the bipolar transistor. As described

in Chapter 4, the collector is connected to the ground through the n-well. When

redesigning the chip, the bipolar transistor terminals should be connected to an

analog pad. Also the BJT should be laid out on a separate well.

79 • Shielding and routing techniques is to be incorporated around the analog circuits

hence isolating them from digital circuits.

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85 APPENDIX 1

MOSIS PARAMETRIC TEST RESULTS

RUN: T1CI VENDOR: AMI

TECHNOLOGY: SCNA FEATURE SIZE: 1.6 microns

INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIS test structures on each wafer of s fabrication lot. SPICE parameters obtained from similar measurements on a selected wafer are also attached.

COMMENTS: American Microsystems, Inc. 1.5 micron AB(X)

TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS

MINIMUM 4.0/1.6

Vth 0.60 -0.96 volts

SHORT 20.0/1.6

Idss 191 -77 uA/um

Vth 0.58 -0.92 volts

Vpt 10.0 -10.0 volts

WIDE 20.0/1.6

Ids0 < 2.5 < 2.5 pA/um

LARGE 50/50

Vth 0.60 -0.87 volts

Vjbkd 16.9 -14.4 volts

Ijlk <50.0 <50.0 pA

I Gamma 0.64 0.47 V^0.5

K' (Uo*Cox/2) 36.5 -12.1 uA/V^2

Low-field Mobility 649.02 215.15 cm^2/V*s

COMMENTS: Poly bias varies with design technology. To account for mask and etch bias use the appropriate value for the parameter XL in your SPICE model card.

Design Technology XL

SCN (lambda=0.6) 0.00

SCN (lambda=0.8) 0.00

AMI_ABN 0.00

POLY2 TRANSISTORS W/L N-CHANNEL P-CHANNEL UNITS

MINIMUM 4.8/3.2

Vth 0.91 -1.20 volts

SHORT 9.6/3.2

Vth 0.90 -1.16 volts

LARGE 28.8/28.

Vth 0.90 -1.13 volts

K' (Uo*Cox/2) 22.5 -7.1 uA/V^2

FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS

Vth Poly >15.0 <-15.0 volts

BIPOLAR PARAMETERS W/L NPN UNITS

2X1 2X1

Beta 135

V_early 42.9 volts

Vce,sat 0.2 volts

2X2 2X2

Beta 135

V_early 42.8 volts

Vce,sat --- volts

2X4 2X4

Beta 136

V_early 42.3 volts

Vce,sat --- volts

2X8 2X8

Beta 137

V_early 42.1 volts

Vce,sat --- volts

BVceo 12.1 volts

III BVcbo 29.1 volts

BVebo 8.0 volts

PROCESS N+ACTV P+ACTV POLY POLY2 PBASE MTL1 MTL2 UNITS

Sheet Resistance 54.3 77.7 27.6 23.0 2135.7 0.05 0.03 ohms/sq

Contact Resistance 61.5 46.6 31.3 19.1 0.05 ohms

Gate Oxide Thickness 307 angstrom

PROCESS PARAMETERS N_WELL UNITS

Sheet Resistance 1697 ohms/sq

Contact Resistance -- ohms

CAPACITANCE N+ACTV P+ACTV POLY POLY2 M1 M2 N_WELL UNITS

Area (substrate) 291 294 36 24 15 57 aF/um^2

Area (N+active) 1126 711 49 26 aF/um^2

Area (P+active) 1109 704 aF/um^2

Area (poly) 592 44 22 aF/um^2

Area (poly2) 45 aF/um^2

Area (metal1) 39 aF/um^2

Fringe (substrate) 94 161 30 39 aF/um

Fringe (poly) 58 9 aF/um

Fringe (metal1) 63 aF/um

IV Overlap (N+active) 179 aF/um

Overlap (P+active) 218 aF/um

CIRCUIT PARAMETERS UNITS

Inverters K

Vinv 1.0 1.84 volts

Vinv 1.5 2.15 volts

Vol (100 uA) 2.0 0.29 volts

Voh (100 uA) 2.0 4.57 volts

Vinv 2.0 2.34 volts

Gain 2.0 -15.69

Ring Oscillator Freq.

DIV64 (31-stg,5.0V) 38.92 MHz

Ring Oscillator Power

DIV64 (31-stg,5.0V) 1.56 uW/MHz/gate

T1CI SPICE LEVEL3 PARAMETERS

* DATE: Feb 11/02

* LOT: T1CI WAF: 7203

* DIE: N_Area_Fring DEV: N3740/10

* Temp= 27

.MODEL CMOSN NMOS ( LEVEL = 3

+ TOX = 3.07E-8 NSUB = 1.193197E16 GAMMA = 0.7332181

+ PHI = 0.7 VTO = 0.6106854 DELTA = 0.7182342

V + UO = 601.9269801 ETA = 9.998816E-4 THETA = 0.070571

+ KP = 7.428765E-5 VMAX = 1.894035E5 KAPPA = 0.5

+ RSH = 0.08379 NFS = 6.785188E11 TPG = 1

+ XJ = 3E-7 LD = 5.698171E-12 WD = 6.874538E-7

+ CGDO = 1.79E-10 CGSO = 1.79E-10 CGBO = 1E-10

+ CJ = 2.880268E-4 PB = 0.905851 MJ = 0.5

+ CJSW = 1.233954E-10 MJSW = 0.05 )

* DATE: Feb 11/02

* LOT: T1CI WAF: 7203

* DIE: P_Area_Fring DEV: P3740/10

* Temp= 27

.MODEL CMOSP PMOS ( LEVEL = 3

+ TOX = 3.07E-8 NSUB = 1E17 GAMMA = 0.4801562

+ PHI = 0.7 VTO = -0.8727748 DELTA = 0.4180493

+ UO = 102.7119278 ETA = 0.5 THETA = 0.1315069

+ KP = 2.434199E-5 VMAX = 4.111656E5 KAPPA = 100

+ RSH = 34.9751774 NFS = 4.868265E11 TPG = -1

+ XJ = 2E-7 LD = 6.937406E-14 WD = 1E-6

+ CGDO = 2.18E-10 CGSO = 2.18E-10 CGBO = 1E-10

+ CJ = 2.914778E-4 PB = 0.7457159 MJ = 0.4262351

+ CJSW = 1.613212E-10 MJSW = 0.1035851 )

VI VII T1CI SPICE BSIM3 VERSION 3.1 PARAMETERS

SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8

* DATE: Feb 11/02

* LOT: T1CI WAF: 7203

* Temperature_parameters=Default

.MODEL CMOSN NMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 3.07E-8

+XJ = 3E-7 NCH = 7.5E16 VTH0 = 0.5544519

+K1 = 0.9063691 K2 = -0.0619884 K3 = 6.1250753

+K3B = -2.4831929 W0 = 2.365777E-6 NLX = 8.98551E-8

+DVT0W = 0 DVT1W = 0 DVT2W = 0

+DVT0 = 0.7360219 DVT1 = 0.5118028 DVT2 = -0.5

+U0 = 657.7608769 UA = 1.486927E-9 UB = 1.001993E-18

+UC = 1.773058E-11 VSAT = 1.139805E5 A0 = 0.6701019

+AGS = 0.1140703 B0 = 2.040301E-6 B1 = 5E-6

+KETA = -4.979384E-3 A1 = 0 A2 = 1

+RDSW = 3E3 PRWG = -0.0117244 PRWB = -0.0377373

+WR = 1 WINT = 7.29389E-7 LINT = 2.175484E-7

+XL = 0 XW = 0 DWG = -1.769233E-8

+DWB = 3.562538E-8 VOFF = -0.0581985 NFACTOR = 0.6071665

+CIT = 0 CDSC = 0 CDSCD = 0

+CDSCB = 4.499823E-5 ETA0 = -0.9932729 ETAB = -0.4866833

VIII +DSUB = 0.9682892 PCLM = 1.2069566 PDIBLC1 = 7.786764E-3

+PDIBLC2 = 1.9292E-3 PDIBLCB = -0.1 DROUT = 0.0537248

+PSCBE1 = 2.186201E9 PSCBE2 = 5E-10 PVAG = 0.2284775

+DELTA = 0.01 RSH = 54.3 MOBMOD = 1

+PRT = 0 UTE = -1.5 KT1 = -0.11

+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9

+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4

+WL = 0 WLN = 1 WW = 0

+WWN = 1 WWL = 0 LL = 0

+LLN = 1 LW = 0 LWN = 1

+LWL = 0 CAPMOD = 2 XPART = 0.5

+CGDO = 1.79E-10 CGSO = 1.79E-10 CGBO = 1E-9

+CJ = 2.86621E-4 PB = 0.9311814 MJ = 0.5067058

+CJSW = 1.318636E-10 PBSW = 0.99 MJSW = 0.1

+CJSWG = 6.4E-11 PBSWG = 0.99 MJSWG = 0.1

+CF = 0 )

.MODEL CMOSP PMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 3.07E-8

+XJ = 3E-7 NCH = 2.4E16 VTH0 = -0.8476404

+K1 = 0.4513608 K2 = 2.379699E-5 K3 = 13.3278347

+K3B = -2.2238332 W0 = 9.577236E-7 NLX = 3.786303E-7

+DVT0W = 0 DVT1W = 0 DVT2W = 0

+DVT0 = 0.5919872 DVT1 = 0.4737888 DVT2 = -0.2723265

IX +U0 = 236.8923827 UA = 3.833306E-9 UB = 1.487688E-21

+UC = -1.08562E-10 VSAT = 1.332024E5 A0 = 0.7111727

+AGS = 0.2390091 B0 = 3.001946E-6 B1 = 3.802664E-6

+KETA = -0.0100438 A1 = 0 A2 = 0.364

+RDSW = 3E3 PRWG = 0.1593382 PRWB = -0.1554976

+WR = 1 WINT = 7.565065E-7 LINT = 7.084069E-8

+XL = 0 XW = 0 DWG = -2.13917E-8

+DWB = 3.857544E-8 VOFF = -0.0877184 NFACTOR = 0.2508342

+CIT = 0 CDSC = 2.924806E-5 CDSCD = 1.497572E-4

+CDSCB = 1.091488E-4 ETA0 = 0.15903 ETAB = 4.806723E-3

+DSUB = 0.2873 PCLM = 4.3848211 PDIBLC1 = 0

+PDIBLC2 = 1E-3 PDIBLCB = -1E-3 DROUT = 6.07788E-3

+PSCBE1 = 3.342669E9 PSCBE2 = 5E-10 PVAG = 15

+DELTA = 0.01 RSH = 77.7 MOBMOD = 1

+PRT = 0 UTE = -1.5 KT1 = -0.11

+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9

+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4

+WL = 0 WLN = 1 WW = 0

+WWN = 1 WWL = 0 LL = 0

+LLN = 1 LW = 0 LWN = 1

+LWL = 0 CAPMOD = 2 XPART = 0.5

+CGDO = 2.18E-10 CGSO = 2.18E-10 CGBO = 1E-9

+CJ = 2.916086E-4 PB = 0.7421013 MJ = 0.4255091

+CJSW = 1.602356E-10 PBSW = 0.99 MJSW = 0.1146467

X +CJSWG = 3.9E-11 PBSWG = 0.99 MJSWG = 0.1146467

+CF = 0 )