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Hardware Support for Operating System MIPS Interrupts

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Hardware Support for Operating System MIPS Interrupts Announcements • Reminders – Lab3 and PA2 (part a) are due on today EE108B Lecture 14 Virtual Memory Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b C. Kozyrakis EE108b Lecture 14 1 C. Kozyrakis EE108b Lecture 14 2 Review: Hardware Support for Operating System MIPS Interrupts • Operating system • What does the CPU do on an exception? – Manages hardware resources (CPU, memory, I/O devices) – Set EPC register to point to the restart location • On behalf of user applications – Change CPU mode to kernel and disable interrupts – Provides protection and isolation – Set Cause register to reason for exception also set BadVaddr – Virtualization register if address exception • Processes and virtual memory – Jump to interrupt vector • Interrupt Vectors • What hardware support is required for the OS? – 0x8000 0000 : TLB refill – Kernel and user mode – 0x8000 0180 : All other exceptions • Kernel mode: access to all state including privileged state • Privileged state • User mode: access to user state ONLY – EPC – Cause – Exceptions/interrupts – BadVaddr – Virtual memory support C. Kozyrakis EE108b Lecture 14 3 C. Kozyrakis EE108b Lecture 14 4 Interrupt vectors A Really Simple Exception Handler Accelerating handler dispatch Exception xcpt_cnt: numbers • 1. Each type of interrupt has la $k0, xcptcount # get address of counter a unique exception number k lw $k1, 0($k0) # load counter codecode for for addu $k1, 1 # increment counter exceptionexception handler handler 0 0 • 2. Jump table (interrupt vector) sw $k1, 0($k0) # store counter interrupt entry k points to a function code for eret # restore status reg: enable vector code for (exception handler). exceptionexception handler handler 1 1 # interrupts and user mode 0 # return to program (EPC ) 1 codecode for for • 3. Handler k is called each time 2 ... exceptionexception handler handler 2 2 exception k occurs • Can’t survive nested exceptions n-1 ... – OK since does not re-enable interrupts • Does not use any user registers codecode for for But the CPU is much faster – No need to save them exceptionexception handler handler n-1 n-1 than I/O devices and most OSs use a common handler anyway Make the common case fast! C. Kozyrakis EE108b Lecture 14 5 C. Kozyrakis EE108b Lecture 14 6 Exception Example #1 Exception Example #2 • Memory Reference • Memory Reference – User writes to memory location – User writes to memory location int a[1000]; – That portion (page) of user’s memory is currently – Address is not valid main () not in memory int a[1000]; – Page handler detects invalid address main () { – Page handler must load page into physical { – Sends SIGSEG signal to user process a[5000] = 13; memory a[500] = 13; – User process exits with “segmentation } – Returns to faulting instruction } fault” – Successful on second try User Process OS User Process OS event page fault lw Create page and load page fault event lw return into memory Detect invalid address Signal process C. Kozyrakis EE108b Lecture 14 7 C. Kozyrakis EE108b Lecture 14 8 Review: OS ↔ User Code Switches Process Address Space • System call instructions (syscall) 0xffffffff kernel memory memory – Voluntary transfer to OS code to open a file, write data, change (code, data, heap, stack) invisible to working directory, … 0x80000000 user code user stack – Jumps to predefined location(s) in the operating system (created at runtime) – Automatically switches from user mode to kernel mode • Each process has its own $sp (stack pointer) private address space PC + 4 Branch/jump PC PC • Exceptions & interrupts Excep Vec MUX – Illegal opcode, device by zero, …, timer expiration, I/O, … EPC brk run-time heap – Exceptional instruction becomes a jump to OS code (managed by malloc) • Precise exceptions read/write segment – External interrupts attached to some instruction in the pipeline 0x10000000 (.data, .bss) loaded from the – New state: EPC, Cause, BadVaddr registers read-only segment executable file (.text) 0x00400000 unused 0 C. Kozyrakis EE108b Lecture 14 9 C. Kozyrakis EE108b Lecture 14 10 Motivations for Virtual Memory Motivation #1: DRAM a “Cache” for Disk • #1 Use Physical DRAM as a Cache for the Disk • Full address space is quite large: – Address space of a process can exceed physical memory size – 32-bit addresses: ~4,000,000,000 (4 billion) bytes – Sum of address spaces of multiple processes can exceed physical memory – 64-bit addresses: ~16,000,000,000,000,000,000 (16 quintillion) bytes • #2 Simplify Memory Management • Disk storage is ~100X cheaper than DRAM storage – Multiple processes resident in main memory. • To access large amounts of data in a cost-effective manner, the • Each process with its own address space bulk of the data must be stored on disk – Only “active” code and data is actually in memory • Allocate more memory to process as needed. • #3 Provide Protection 100 GB: ~$125 – One process can’t interfere with another. 1 GB: ~$128 • because they operate in different address spaces. 4 MB: ~$120 – User process cannot access privileged information • different sections of address spaces have different permissions. SRAM DRAM Disk C. Kozyrakis EE108b Lecture 14 11 C. Kozyrakis EE108b Lecture 14 12 Levels in Memory Hierarchy DRAM vs. SRAM as a “Cache” cache virtual memory • DRAM vs. disk is more extreme than SRAM vs. DRAM – Access latencies: • DRAM ~10X slower than SRAM C 8 Ba 32 B 8 KB • Disk ~ 100,000X slower than DRAM CPUCPU MemoryMemory disk c disk – Importance of exploiting spatial locality: regsregs h e • First byte is ~ 100,000X slower than successive bytes on disk – vs. ~4X improvement for page-mode vs. regular accesses to DRAM Register Cache Memory Disk Memory – Bottom line: size: 128 B <4MB < 16 GB > 100 GB • Design decisions made for DRAM caches driven by enormous Speed(cycles): 0.5-1 1-20 80-100 5-10 M cost of misses $/Mbyte: $30/MB $0.128/MB $0.001/MB line size: 8 B 32 B 8 KB SRAM DRAM larger, slower, cheaper Disk C. Kozyrakis EE108b Lecture 14 13 C. Kozyrakis EE108b Lecture 14 14 Impact of These Properties on Design Locating an Object in a “Cache” • If DRAM was to be organized similar to an SRAM cache, how would • SRAM Cache we set the following design parameters? – Tag stored with cache line – Line size? – Maps from cache block to memory blocks • Large, since disk better at transferring large blocks and minimizes miss rate • From cached to uncached form – Associativity? – No tag for block not in cache • High, to mimimize miss rate – Write through or write back? – Hardware retrieves information • Write back, since can’t afford to perform small writes to disk • can quickly match against multiple tags “Cache” Tag Data Object Name 0: D 243 X = X? 1: X 17 • • • • • • N-1: J 105 C. Kozyrakis EE108b Lecture 14 15 C. Kozyrakis EE108b Lecture 14 16 Locating an Object in a “Cache” (cont.) A System with Physical Memory Only • DRAM Cache • Examples: – Each allocate page of virtual memory has entry in page table – most Cray machines, early PCs, nearly all embedded systems, etc. – Mapping from virtual pages to physical pages Memory • From uncached form to cached form 0: Physical 1: – Page table entry even if page not in memory Addresses • Specifies disk address – OS retrieves information CPU Page Table “Cache” Location Data Object Name D: 0 0: 243 X J: On Disk 1: 17 • • N-1: • • • • X: 1 N-1: 105 Addresses generated by the CPU point directly to bytes in physical memory C. Kozyrakis EE108b Lecture 14 17 C. Kozyrakis EE108b Lecture 14 18 A System with Virtual Memory Page Faults (Similar to “Cache Misses”) • Examples: Memory • What if an object is on disk rather than in memory? – workstations, servers, modern PCs, etc. 0: – Page table entry indicates virtual address not in memory Page Table 1: – OS exception handler invoked to move data from disk into memory Virtual Physical Addresses 0: Addresses • current process suspends, others can resume 1: • OS has full control over placement, etc. CPU Before fault After fault Memory Memory Page Table Page Table P-1: Virtual Physical N-1: Addresses Addresses Virtual Physical Addresses Addresses CPU CPU Disk Address Translation: Hardware converts virtual addresses to physical addresses via an OS-managed lookup table ( page table ) Disk Disk C. Kozyrakis EE108b Lecture 14 19 C. Kozyrakis EE108b Lecture 14 20 Servicing a Page Fault Motivation #2: Memory Management (1) Initiate Block Read • Processor Signals ProcessorProcessor Controller • Multiple processes can reside in physical memory. Reg (3) Read – Read block of length P • How do we resolve address conflicts? Done starting at disk address – what if two processes access something at the same address? X and store starting at CacheCache memory address Y memory invisible to kernel virtual memory • Read Occurs user code $sp stack – Direct Memory Access Memory-I/O bus (DMA) Memory-I/O bus – Under control of I/O (2) DMA Transfer controller I/OI/O the “brk” ptr controller runtime heap (via malloc) • I / O Controller Signals MemoryMemory controller Completion uninitialized data (.bss) – Interrupt processor initialized data (.data) – OS resumes diskDisk Diskdisk program text (.text) forbidden suspended process 0 C. Kozyrakis EE108b Lecture 14 21 C. Kozyrakis EE108b Lecture 14 22 Solution: Separate Virtual Addr. Spaces Motivation #3: Protection • Page table entry contains access rights information – Virtual and physical address spaces divided into equal-sized blocks – hardware enforces this protection (trap into OS if violation occurs) • blocks are called “pages” (both virtual and physical) Page Tables – Each process has its own virtual address space Memory • operating system controls how virtual pages as assigned to physical Read? Write? Physical Addr 0: memory VP 0: Yes No PP 9 1: 0 Process i: VP 1: Yes Yes PP 4 Virtual 0 Address Translation Physical Address VP 1 PP 2 Address VP 2: No No XXXXXXX VP 2 • • • Space for ..
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