APPENDIX 1 Boolean algebra
AU RULES Boolean algebra is the name given to the algebra of two-state variables, and it provides a more compact way of representing a logic function than does a truth table. Below are given the rules, laws and identities of Boolean algebra; their validity may be checked by the use of truth tables. The three basic operators AND, OR and NOT are used to construct logical expressions, where 1. A· B represents AND(A, B) (logical product), 2. A + B represents OR(A, B) (logical sum), 3. A represents NOT(A) (INVERT A or complement of A).
Equality If A has the same logical properties as B (i.e. the same truth table), then A = Band B = A. If A = B and A = C, then B = C. Sets If A and B are subsets of k, then A· B and A + B are subsets of k. o is the empty set and 1 is the complete set. Laws Boolean algebra is commutative A·B=B·A and A+B=B+A Boolean algebra is associative A + B + C=A + (B + C) = (A + B)+C A·B·C = A ·(B·C) = (A·B)·C Boolean algebra is distributive A ·(B + C) = (A· B) + (A· C) A +(B·C)=(A + B)·(A + C) Algebraic minimization 179
Identities AND OR INVERT A'O=O A+O=A A+A=l A·l =A A + 1 = 1 A'A=O A·A=A A+A=A A=A A'A=O A+A=l
Auxiliary identities
A + (A' B) = A and A + (A- B) = A + B De Morgan's theorem states that if, in any Boolean function, each logical sum is replaced by a logical product, each logical product by a logical sum and each variable is replaced by its complement, the result is the complement of the original function. Therefore A·B···· =A+B+ ...
A+B+···=A-B····. Note that, conventionally, the logical product symbol is implied, so that, AND(A, B) is represented by AB. The symbol has been used explicitly above to show the symmetry in the algebra between the AND and OR functions.
Al.2 ALGEBRAIC MINIMIZATION The Quine-McClusky method for minimization is described here with the aid of an example to illustrate each step. The method minimizes a function into a sum-of-products form. The equivalent action in Karnaugh map minimization is indicated.
Consider the function f = A·jj·C·jj + A-B'C'D + B·C·(A + D)+ A·B·D. 1. Expand to the sum-of-products canonical form. That is, expand all product terms (using X = X' Y + X' Y) so that they contain all variables explicitly, and remove all multiple occurrences of the same term (using X' Y + X' Y = X' Y). (Plot the function on the Karnaugh map.)
f = A-B'C'D + A-B'CD + A-B'C'D + A·B·C·D + A·B·C·jj + A·jj·C·jj. 180 Appendix 1 Boolean algebra
2. Write out a list of the product terms and compare each term with every other term looking for pairs of the form W· X . y. Z and W- X· y. Z. That is, terms which differ in the state of only one variable. Mark both members of the pair and draw up a new list of the reduced terms W· X· Y. Do not remove marked terms from further comparisons. Remove any multiple occurrences from the new list. Save the unmarked terms; they are called prime implicants. Repeat the procedure until no further reductions are possible. (Loop all single 1s that cannot be looped in pairs, then pairs that cannot be looped in fours, etc. The prime implicants correspond to the loops on the map.) A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·fj A·Ii·cfj 2 1 3 1 2 4 3 45 6 5 6 A·B·D B·C·D B·C·D A·B·D A·B·C A·C·fj 1 2 2 1 B·D (B·D). The terms which can be reduced have been marked with a number under the complementing variable to make it clear which terms have been used to obtain the new lists. 3. The next step is to find the essential terms. Writing the prime implicants in a column and the canonical terms in a row, mark where a canonical term is part of a prime implicant. A prime implicant associated with a column with only one mark is an essential term. The minimized function is the sum of the essential terms and the simplest set of other prime implicants to give at least one mark in each column. (Select the simplest set of loops.) XB·C·D XB·C·D A·B·C·D A-B·C·D A·B·C·V A·jj·C·V B·D X X X X A-B·C X X A·C·V X X Essential terms are B· D and A· C· fj and they are sufficient to cover all canonical terms. The final minimized function is f= B·D + A·C·fj. Note that, all prime implicants may not be required for a Minimization in product-oj-sums Jorm 181
minimized function but all are needed for hazard-free operation (section 2.10).
A1.3 MINIMIZATION IN PRODUCT-OF-SUMS FORM In general, people find it easier to work with logic functions in the sum-of-products form. Because of the relationship between sum-of• products and product-of-sums expressions, a convenient method of minimizing in product-of-sums form is to minimize the inverse function in sum-of-products form and then apply De Morgan's theorem. Using a map, the function is plotted on the map and then each element is inverted (all ones are changed to zeros and zeros to ones) to give the inverse function. For the algebraic method, find the canonical expression and then the inverse function is all the terms not in that expression. Minimize in the normal way to give a sum-of-products form for the inverse function and apply De Morgan's theorem to obtain a product-of-sums form. For example, if 1 = (A·B·C·D) + (A-ii·D) then De Morgan's theorem gives J = (A + Ii + C + D)·(A + B + 15). APPENDIX 2 Logic families
A2.1 TTL CIRCUITS
Transistor-transistor logic (TTL) was the first major integrated• circuit logic family. It uses bipolar junction transistors and runs from a 5 V power supply. The circuit for a standard TTL NAND gate is shown in Fig. A2.l(a). The circuits for other families of TTL look somewhat different, but operate in fundamentally the same way. The basic input and output voltage levels for standard TTL are given in Table A2.1. The difference between the limits for input and output levels is to allow for noise induced on the connections between devices. From the data in Table A2.l it is seen that TTL has a noise margin lor immunity) of 0.4 V at both logic levels. In Fig. A2.l(a), the states of the transistors and the voltage levels through the circuit are given for all inputs logic high (> 2.0 V). Figure A2.l(b) shows the states and voltages when one input is logic low (0.2 V in this case). When all inputs are high, the base-emitter junctions of T 1 are reverse biased but its base-collector junction is forward biased, and this supplies current to T 2 and T 3, i.e. T 2 and T 3 are turned on and saturate. The voltage between the base of T 4 and the output is only about 0.7 V and, as this is across two p-n junctions (T 4 and D 1)' T 4 is turned off. With T 4 off and T 3 on, the output is governed by T 3. The output voltage is VSAT for T 3, which is about 0.2 V, and this increases to about 0.4 Vas the current into the output is increased to 16 rnA. (It is customary to define the direction of currents as into inputs or outputs, and, therefore, as T 3 provides a current sink, the value is positive.) The current to maintain an input at the logic high level is the TTL circuits 183
Out i6mA max
Inputs logic high (>2U) Input logic low (O.2U) Out put log i c low (0. 2U) Output logic high (3.3U)
(a) (b) Fig. A2.1 NAND gate with (a) all inputs high, and (b) one input low.
Table A2.1 TTL operating voltage levels
Min. Typ. Max.
VIL Input low level 0.8V
VIH Input high level 2.0V VOL Output low level 0.2V 0.4 V VOH Output high level 2.4 V 3.4 V
leakage current associated with the reverse-biased emitter-base junction of T 1 and is therefore small ( < 40 J-la). If one or more inputs are taken to a logic low value (the diagram assumes a VL of 0.2 V), then the base-emitter junction ofT 1 is forward biased. The maximum current to maintain an input at the logic low level is - 1.6 rnA. With the voltage at the base of T 1 at about 0.9 V, both T 2 and T 3 are switched off and T 4 is switched on. The output is now governed by T 4' The unloaded output voltage is close to the supply voltage less the voltage drop across two forward-biased p-n junctions (T 4 and D 1), i.e. about 3.6 V. The output is guaranteed to supply a current of at least - 400 JlA at the minimum logic high level output of 2.4 V. The arrangement ofT4, D1 and T 3 is known as a totem-pole output and provides fast switching in both directions between the high and low output states. This is because the output has an active pull-down when T 3 is switched on (and T 4 om, and an active pull-up when T 4 is switched on (and T 3 om. The high currents available from the emitter of T 4 during pull-up and the collector of T 3 during pull-down mean 184 Appendix 2 Logic families that the capacitive load on the output is rapidly charged or dis• charged and results in short switching times. The circuit values are chosen so that, during the time the output is switching, the current• carrying capability of one transistor (T 3 or T 4) is reduced as the other's capability is increased. This prevents large, transient currents flowing in both transistors of the totem-pole during switching, and reduces the size of switching spikes on the power supply lines. From Fig. A2.1(a) it can be seen that the output is unaffected by lowering an input voltage until the input approaches 1.4 V (the voltage at T 1 collector) and starts diverting current into the emitter. When the input drops below this voltage T 3 is turned off, but T 2 still conducts the current flowing through its emitter resistor. The voltage at the collector of T 2 rises rapidly and T 4 starts to conduct, establishing a logic high value (> 2.4 V) at the output. The full output voltage is reached when T 2 is switched off which requires the input to fall below about 0.7 V. The output current drive of the circuit is designed to be greater than 10 times the input current requirements so that one output can be connected to at least 10 inputs and still provide logic levels within the specification. This number is known as the fan-out capability of the logic. Note that if inputs are left unconnected, they float to a logic high level. For the NAND gate shown here, if all inputs are left floating, the output will be logic low. Unconnected or floating TTL inputs are sensitive to noise pickup and, therefore, it is strongly recommended that all unused inputs are tied to the appropriate logic level. Inputs required to be logic low can be tied directly to ground. Inputs required to be logic high should be connected to the 5 V supply through a 1 kn resistor, where up to 25 inputs may be connected to the same resistor. The resistor protects the inputs against transients on the supply rail which could exceed the maximum rating of 5.5 V between emitters of the common-emitter input transistor. This limitation does not apply to low-power Schottky logic devices with diode inputs (see section A2.5 on LSTTL), and these may be connected directly to the 5 V supply. Standard totem-pole devices must never have outputs connected together. Conflicts between the output levels of the devices can damage the devices and will produce an output level somewhere between the specified high and low logic levels. Conflicts of this kind are known as contentions. Three variants of the basic circuit exist within each family and Open-collector output 185 extend the versatility of the logic. Two (open collector and tri-state) affect the output of the circuit, the third (Schmitt trigger) affects the input.
A2.2 OPEN-COLLECTOR OUTPUT In an open-collector device the active pull-up circuit of the totem pole is removed leaving the circuit shown in Fig. A2.2. A logic low output is achieved, as before, by switching on T 3' and a logic high by switching it off and leaving the output floating. A resistor, connected to 5 V, must be added externally to give a passive pull-up to the logic high level, and this, depending on the value of the resistor used, can result in a slow low-to-high transition time. A low value of resistance gives a low transition time but high power dissipation. The minimum resistance value is determined by the number of inputs connected to the output and is given approximately by
Vee - VOL 4.6 Rmin = N = 16 _ 1.6. N kQ ~ 330fHor N = 1, IOL - 'IIL where IOL is the maximum low-level output current of 16 rnA and IlL is the maximum low-level input current of 1.6 rnA. The maximum value of resistance is determined by leakage currents for the circuits and gives a value of9 kQ for connection to one input, reducing to 4 kQ for 10 inputs. Open-collector devices allow outputs to be connected together in what is called a wired-OR configuration (note that it is actually wired• AND). If all the outputs connected together have their output transistors switched off, the output is the logic high level produced by the passive pull-up resistor; if one or more output transistors are turned on, then a logic low level results. Using positive logic conventions, the resultant level is the AND of the outputs connected
5U9pUII up 1 .6kO res i st.or . 3300 min
In Out
Fig. A2.2 Open-collector NAND gate circuit and symbols. 186 Appendix 2 Logic families together. Connecting outputs together in this way can reduce the number oflogic circuits required at the expense of adding one resistor. Open-collector devices can also be used in bus systems where a number of devices must be able to supply data to the bus. Because an open-collector device only has an active pull-down circuit no damaging output contentions can occur.
A2.3 TRI-STATE OUTPUT Tri-state devices overcome the necessity for a pull-up resistor while allowing outputs to be connected together in certain cases. The circuit for a tri-state NAND gate is shown in Fig. A2.3. The additional components and the control input either allow the gate to operate as a normal TTL gate with a totem-pole output or disable both output transistors. T 5, T 6 and T 7 work in exactly the same way as T l' T 2 and T 3 of a standard gate and therefore the control input operates at the same levels as a logic input. When the control input is logic low, T 6 and T 7 are switched off and the operation of the gate circuit is unaffected. When the control input is high, T 6 and T 7 are switched on and the collector ofT 7 is at about 0.3 V. This acts as a logic low input to T 1 which then switches off T 2 and T 3 and also, via D 2 , reduces the base voltage of T 4 to approximately 1.0 V which means that T 4 is held off. The output can neither source nor sink current: it is high impedance (called Hi-z for brevity). If the outputs of a number of tri-state devices are connected together, then, as long as only one output is enabled, i.e. all the others are of high impedance, the combined output is determined by the state of the enabled device. Care must be taken to enable only one of
Out
Fig. A2.3 Tri-state NAND gate circuit and symbols. Schmitt trigger inputs 187 the interconnected outputs at one time, otherwise contention and damage can result. One standard way to ensure that only one device is enabled is to use a decoder (with active-low outputs) to supply the control signals to the tri-state devices. As only one decoder output can be logic low, only one tri-state output is enabled. If none of the interconnected outputs is enabled, the input (or inputs) to which they are joined can float to any level (normally logic high) and become very noise sensitive because of the connecting leads. The system should be designed so that such inputs have no effect on the circuit operation until one of the tri-state outputs is enabled. Because an enabled output has active pull-up as well as pull-down, tri-state devices switch rapidly in either direction even when driving capacitive loads. They are, therefore, very suitable for use in bus systems but cannot be used in wired-AND applications.
A2.4 SCHMITT TRIGGER INPUTS A Schmitt trigger circuit is one that uses positive feedback to improve the switching time of a circuit. No matter how slowly the input changes, when the threshold of the circuit is reached, the output switches rapidly from one state to the other. The positive feedback produces another effect on the operation of the circuit, which is that the threshold to switch in one direction differs from the threshold to switch in the other. The circuit is said to exhibit hysteresis or backlash. If the high and low thresholds are VT + and VT -, respectively, then starting with an input below VT _, the output will not switch until the input reaches V T + ; the output will now stay in this state until the input drops below V T _. Threshold values for TTL are given in Table A2.2. The main use for this type of circuit is to convert slowly changing signals to logic signals with transition times of a few nanoseconds. An additional benefit is that noise which is less than the hysteresis will not
Table A2.2 Schmitt-input levels for TTL
Min. Typ. Max.
VT + Positive threshold 1.5 V 1.7 V 2.0V
VT - Negative threshold 0.6V 0.9V l.1V
VT + - VT - Hysteresis 0.4 V 0.8V 188 Appendix 2 Logic families
R T H~ C~
LSTTL T = R.C R = 2.2 kQ CMOS T = R.C/2 2.2 kQ< R <1 MQ Fig. A2.4 TTL oscillators using Schmitt-input gates.
produce multiple output transitions as the slowly changing signal passes a threshold. A very common use for a Schmitt-input device is as a simple oscillator. In Fig. A2.4 a Schmitt-input inverter and NAND gate are used for this function, and a second gate is used as a buffer. The hysteresis loop in the gate symbol is used to indicate a Schmitt-input device. The feedback resistor charges the capacitor when the output is logic high and discharges it when the output is logic low. With the output high, the voltage across the capacitor increases until the Schmitt positive threshold is exceeded. At this point the output changes to low and the capacitor voltage decreases until the lower threshold is passed. The output again changes to logic high and the cycle repeats. For standard TTL the recommended value for the feedback resistor is 330 n, and the circuit will only work reliably for values fairly close to this; there is no limit on the size of the capacitor. The period of the oscillation is approximately equal to 330C J.1,S, where C is the value of the capacitor in microfarads. Even though the specification of the 7414 surpasses the basic TTL requirements (it sources more current from a logic high output and less from a logic low input), the peak current for the logic high output exceeds the specification by a considerable margin and results in a slow low-to-high transition. The second Schmitt-input inverter is used as a buffer to restore fast switching between standard TTL levels, and the oscillator should not be used without this buffer. When low• power Schottky TTL is used (see section A2.5) the recommended resistance is 2.2 kn and the input and output current limits are more nearly satisfied. Again, a second Schmitt-input inverter should be used as a buffer. Schottky TTL 189
A2.5 SCHOTTKY TTL A major limitation to the speed of standard TTL is caused by the charge stored in the bases of the saturated transistors. Virtually all this charge storage can be eliminated if a Schottky diode (a metal• semiconductor diode with a forward voltage drop of about 0.4 V) is connected between the base and collector so that it becomes forward biased when that junction becomes forward biased. The Schottky diode, which as a majority carrier device has no stored charge, prevents the transistor saturating and, with no stored charge to remove, the speed of the logic can be increased and/or the power consumption reduced. Low-power Schottky (LS) TTL, which is currently the most popular family, is slightly faster (typical gate delay of 9 ns) and has only one-fifth the power consumption of standard TTL. A circuit for an LSTTL NAND gate is shown in Fig. A2.S. The main changes compared with the original TTL circuit in Fig. A2.1 are that the multi-emitter input transistor (T d has been replaced with the (faster) diode AND gate (D2' D 3), and the pull-up circuit ofT4 and Dl has been replaced by the Darlington pair of T 4 and T 5' Additions to the circuit are D4 and D 5 , which provide input protection against negative input signals, and D 6, D7 and T 6, which improve the swit• ching characteristics of the circuit. There are very few problems in using different families of TTL in the same circuit. In many cases mixing is necessary as some devices are
In Out
OU ~--~------~--~ Fig. A2.5 LSTTL NAND gate circuit. 190 Appendix 2 Logic families
Table A2.3 Basic parameters for LSTTL
Voltage Current Min. Typ. Max. Min. Typ. Max.
Input low level VIL 0.8V IlL -O.4mA Input high level VIH 2.0V IIH 20fJA Output low level VOL 0.25 V 0.4 V 10L 8mA Output high level VOH 2.7V 3.4V 10H - 4OO IlA
Pull-up R min 600Q Rmax 18kQ resistor not made in all families. The slight differences in logic levels between the families are not significant, but the input loading and output drive capability does vary and must be taken into account. Logic levels and other basic parameters for LSTTL are given in Table A2.3. Recent additions to TTL-compatible logic families offer higher speed and/or lower power consumption than the two families described here. FAST (Fairchild advanced Schottky TTL) is LSTTL drive compatible and about three times faster, but has about three times the power consumption of LSTTL. Advanced low-power Schottky (ALS) has about twice the speed and half the power consumption of LSTTL. Devices from the TTL-compatible high• speed CMOS families, 74HCT and 74ACT series, can be used as drop-in replacements for LSTTL and have a quiescent power con• sumption of less than one-thousandth of the low-power Schottky devices. The 74HCT devices are similar in speed to LSTTL, while 74ACT devices are of the same speed as FAST.
A2.6 EMITTER-COUPLED LOGIC (ECL) Emitter-coupled logic is built from bipolar junction transistors but avoids saturated switching by using differential pairs to provide current switching instead. This results in a high-speed, high-power circuit with comparatively small separation between logic levels. A basic ECL ORjNOR gate circuit is shown in Fig. A2.6. The levels MOS logic 191
OR out .-..-- NOR out In A
In B ---'
Fig. A2.6 Basic EeL ORjNOR gate circuit.
used in ECL are - 0.8 V for logic high and - 1.7 V for the logic low level. A temperature-stabilized intermediate level of - 1.3 V is used as the reference level, VR, for the current steering network. When both inputs to the OR gate in Fig. A2.6 are at the logic low level, T 1 and T 2 are turned off and current flows in T 3; the output at the emitter ofT4 is logic high and at T 5 is logic low. If either input changes to the logic high level, then the current is switched through the transistor connected to that input and makes T 4 logic low and T 5 logic high. The current switching action is very fast and gate delays are only about 1 ns. Because both a function and its inverse are produced by the logic, intermediate inversion of signals is not required. The low-impedance emitter-follower outputs give ECL a typical fan-out capability of 25. ECL logic is used where the ultimate in logic speed is required. Because the two complementary outputs form a balanced pair, this type of logic is useful for transmitting fast signals over large distances ( ~ 100m) using twisted pair cables. Chips are available which convert between TTL and balanced ECL to facilitate its use in this way (e.g. MC10124/5).
A2.7 MOS LOGIC Bipolar transistor logic uses n-p-n transistors almost exclusively. Metal oxide semiconductor (MOS) logic uses both p- and n-channel field-effect transistors (FETs) either separately, to produce PMOS and NMOS logic, or jointly to produce complementary (CMOS) logic. The advantages ofMOS logic, and in particular CMOS, are the small size ofthe basic elements and the low power dissipation, which means that very large quantities of logic can be squeezed into one IC package. Traditionally, MOS logic has been slow, with CMOS gate 192 Appendix 2 Logic families propagation delays of between 25 ns and 100 ns. Improved manu• facturing techniques have significantly changed this picture recently, and CMOS families (e.g. 74ACT series) are available which are fully compatible with LSTTL, as fast as any other TTL family and have a much lower power consumption. Large memories are normally constructed using NMOS or CMOS technology and are produced with access times down to 15 ns. Only ECL memories which have a smaller capacity can offer higher speeds. The basic transistors used are enhancement type MOSFETs. With zero voltage between gate and source, no current flows from source to drain, and a threshold voltage (between 1 V and 5 V, depending on the manufacturing process) must be exceeded before current flows easily. Circuits of the NMOS (and PMOS) type use transistors both as switches and resistors. A resistor is obtained by permanently biasing the gate for conduction, i.e. the gate is connected to the drain, and the value of the resistance is determined by the dimensions of the channel. This means that MOS logic circuits consist entirely of transistors, which reduces the number of steps in the manufacturing process and allows the high packing density. Figure A2.7 shows NMOS circuits for the basic logic functions, Invert, NAND and NOR. In each case the top transistor is used as a resistor, so that, if the lower transistors allow conduction, the output level is close to ground, and, if they bar conduction, the output is + V. Logic levels in NMOS (and PMOS) circuits are, therefore, close to the supply levels and the transition point is determined by the threshold voltage. The arrow on the source connection of the MOSFETsymbol indicates the direction of positive current flow. For an n-channel symbol the arrow points away from the channel, for a p-channel symbol the arrow direction is reversed. In CMOS logic all the transistors act as switches. The basic circuits are shown in Fig. A2.8, where each circuit contains the switch section
D Drain +U +U G Gate +U S Source Y=A.B Y=A A-I&, B-1 .... OU OU OU (a) (b) (c) Fig. A2.7 NMOS (a) inverter, (b) NAND, and (c) NOR circuits. Conversion between TTL and CMOS 193 +u +u +u B Y = R.B R =R B fl-C~Y Y = R+B R au au au
(0) (b) (c) Fig. A2.8 CMOS (a) inverter, (b) NAND, and (c) NOR circuits. of the PMOS logic circuit added to the switch section of the NMOS circuit for the same logic function; the resistive elements are discarded. For the inverter, if the input level is logic low (i.e. near ground level), the n-channel device is off, the p-channel device on and the output is logic high. If the input is logic high, the states of the transistors are reversed and the output is logic low. In the quiescent state, either the p-channel or the n-channel part of the circuit is non• conducting and the current flow is restricted to the leakage current through the non-conducting elements. The power consumption is therefore extremely low except during the time the circuit is switching from one state to another. At very high switching rates, CMOS power consumption can reach or exceed TTL levels. CM OS logic, except for the TTL-compatible families, operates over a wide range of power supply level (3 V to 18 V). Logic levels are close to the supply voltage levels and the logic transition level is at the mid point. Noise immunity is high, between 30% and 45% of the supply voltage, and speed and noise immunity increase with increasing supply voltage. Because of the extremely high input impedance of MOSFET devices they can be damaged by voltage transients and static charges. Therefore, they should be handled with care and only inserted or removed from circuits when the power is off. An unconnected input in a circuit will float to an indeterminate level and become very sensitive to noise; therefore, all unused inputs in CMOS devices must be connected to the appropriate supply level (high for ANDed and low for ORed inputs).
A2.8 CONVERSION BETWEEN TTL AND CMOS CMOS and TTL logic can be connected together provided some precautions are taken. These precautions are, of course, unnecessary 194 Appendix 2 Logic families in the case of logic designed to be directly compatible (e.g. 74HCT series). The main problem in converting from TTL to CMOS is the difference in the logic high levels; for conversion from CMOS to TTL it is the mismatch between the current the CMOS output can sink at the logic low level and the current the TTL input sources. Conversion from TTL to CMOS, where the CMOS logic uses a 5 V supply, can be accomplished with the help of a pull-up resistor (cf. open-collector circuits), see Fig. A2.9(a). The resistor has little effect on the low output level but it pulls the high level up from the TTL minimum of 2.4 V to the 5 V supply, i.e. from the CMOS transition level to the CMOS high level. As the input impedance of CMOS is almost purely capacitive, the usable range of resistance values is that for the open-collector devices ofthe TTL family used. If a high current buffer is used even lower values of pull-up resistance are possible. The speed of a low-to-high transition is determined by the pull-up resistor and the capacitance of the CMOS inputs (about 10 pf/input). If the CMOS logic uses a power supply level other than 5 V, a level-shifting circuit is required. This could be an open-collector device with the resistor connected to the CMOS supply rail, a transistor inverter circuit or a special-purpose level shifter. Figure A2.9(b) shows an open-collector circuit for interfacing to CMOS using a 12 V supply. The TTL output sink current has been kept to the same value as that in Fig. A2.9(a) by increasing the value of the pull-up resistor. The ease of conversion from CMOS to TTL depends on the current sinking ability of the CMOS device and the CMOS operating voltage. For 5 V operation it is normally possible to connect a CMOS output directly to at least one LSTTL input. The low-level output sink current capability of74C series devices is well matched to the low level input source current requirements of one LSTTL input ( - 0.4 rnA),
.----r-12U
! i nd i cat es power supp I y !, connect i on to 109 ice I ement (a) (b) Fig. A2.9 TTL-to-CMOS conversion for (a) 5 V, and (b) 12 V CMOS. A CMOS oscillator circuit 195
but any fan-out of the signal must take place after conversion to TTL. 74C series devices have insufficient output sink current to drive standard TTL. Other CMOS logic families are available which have a TTL fan-out ability similar to low-power Schottky devices (e.g. 74HCT series). For CMOS operating at other supply voltages a level-shifting circuit is required, e.g. a 4504, which is a CMOS buffer which can operate from a 5 V supply but can tolerate a higher input voltage. Other solutions use open-drain circuits (the CMOS equiva• lent of open-collector) or transistor inverters.
A2.9 A CMOS OSCILLATOR CIRCUIT Replacing the TTL inverter in Fig. A2.4 by a Schmitt-input CMOS inverter (e.g.40106B) produces an oscillator with a more even (1:1) mark/space ratio, and by modifying the circuit an oscillator with a very large (1000:1) mark/space ratio can be produced. The hysteresis in Schmitt-input CMOS devices is normally quite small ( ~ 0.3 V) and is symmetric about the standard transition point. Because of the very low input current, the feedback resistor can be varied over a very wide range (a few kil to about 1 Mil) and, consequently, the period can be widely varied without changing the capacitor (cf. the TTL circuit). In the modified circuit shown in Fig. A2.10, the diode conducts when the output is high, and the capacitor is charged through a low resistance, producing a short period; the diode is reverse biased when the output is low, and the capacitor discharges through a high resistance, producing a long period. The ability to use smaller capacitors than the TTL circuit for the same period of oscillation, and the more even mark/space ratio for a simple oscillator make the CMOS circuit an attractive replacement for the TTL oscillator.
1k 0 r-£:=Hc;. mark or space 1MO H:=J---I period ~ Rei'!
Fig. A2.10 CMOS oscillator with large mark/space ratio. APPENDIX 3 Designing and testing
This appendix will concentrate on the building and testing of prototypes and single units. No description will be given of the techniques for the large-scale production of electronic circuits.
A3.1 DESIGNS AND DIAGRAMS The outline design for a system is produced by dividing the system into a number of well-defined units which interact with each other in a well-defined way; each unit can then be designed independently. A unit to control the flow of data between sections of the system may have to be added to the design. It will be assumed here that an outline design for the circuit has already been produced. The necessity of preparing good-quality circuit descriptions and diagrams cannot be over-emphasized. They help to prevent errors in the construction of a prototype, and fault tracing and correction are almost impossible without them. Many people insist on constructing a circuit based on the back of an envelope diagram and, when it fails to work as expected, have no option but to take it apart and start again. The ideal set of information on a circuit comprises 1. an outline description of what the circuit does 2. a detailed description of how it does it 3. a block diagram of the functional units 4. a circuit diagram showing the detail of the circuit 5. a layout diagram showing the position of all components 6. a parts list of all the components used. For very simple circuits it is possible to work with just a very brief description and a combined circuit and layout diagram. The habit of Designs and diagrams 197 producing neat documentation for even simple circuits is encouraged for anyone who believes they may design a complex system at some point in the future. The outline description of the circuit is essentially a statement ofthe problem the circuit is to solve and is the first step in the design. The block diagram is the division of the problem into functional units, and the circuit diagram is the detailed logic in each of the units. These are the next design stages. The layout of the circuit and the parts list are required before a prototype can be built, and the detailed description allows the action of the circuit to be followed and checked. The detailed circuit diagram is the central element of the documen• tation. It contains all the information on the logic connections between ICs, passive components and connectors. An example of a
UI 51 .3 U+ .... "'----,,....-~ 2 I RI) 2 OU URI .-'-1 CZJ--iC.~':'" R31-C:::J----j I3 HI 2 p:-'-'---~IJ)~==r..J '"...... C'I oU [~]
Component side Layout
UI 40138 Dual O-FF CI 47iJF 16U JI. I 6U U2 40938 HAHO RI 10k{J .25U JI.2 OU 01 IH4148 R2 10k{J. 25U 02 Red LED R3 220kO .25U 03 Green LED R4 5600 .25U R5 5600 .25U J I 2 pin 50cket UR I 47kO . SOU 51 momentary action 5POT push button Fig. A3.1 Sample circuit diagram, layout and component list. 198 Appendix 3 Designing and testing circuit and a layout diagram are given in Fig. A3.l. Whether you use the modern IEC symbols for logic elements or the more traditional ones, the basic rules are the same. Three types of markings can appear inside or near the symbol. 1. A label unique to that element which also appears on the layout diagram is essential (e.g. U 2 on the circuit diagram must corre• spond to U 2 on the layout). 2. Markings (or the symbol shape for basic gates) to show the logic function of the element. These markings can either be the device type (e.g. BIN/OCT) or a device number (74LS138). If there is insufficient room for one of these, then the parts list can be drawn up to give layout position number against device type or number (e.g. U 17' 74LS138 binary-to-octal converter). 3. The third set of internal markings gives information on the logic signals on input and output lines (e.g. D3 for data line 3, Ao for address line 0 and EN for an enable input). Pin numbers are marked outside the symbol. Note that power supply lines are not generally marked on logic circuit diagrams. The layout diagram gives the position and orientation of all components. For ICs, connectors and other multi-pin components the position of pin 1 is normally marked. Components should be placed so that connections between them are fairly short and neat. Signals should progress from input to output connectors by a fairly smooth route and not jump backwards and forwards across the circuit board. A3.2 PROTOTYPING METHODS Before constructing a complete prototype, it can be useful to check the operation of each of the functional units by building and testing all or part of a unit. A demountable proto typing board provides a quick way of building a circuit which is only required on a temporary basis. This type of board contains a grid of contacts into which components (ICs, resistors, etc.) can be plugged and connected together. Even though each board can take more components, above about four ICs the number of interconnecting wires becomes excessive for reliable circuit testing. Somewhat larger circuits can be built using several boards, but, for circuits involving more than about fifteen chips, permanent construction methods are recommended, even for prelimi• nary design tests. Soldering components to a board produces reliable circuits, but it is Testing 199 not ideally suited to prototype work where changes to the design are frequently required; unsoldering and resoldering components rapidly reduces the quality of the connections. If soldering is used for prototype construction, then IC sockets should be used so that the integrated circuits can be recovered without damage; it is extremely difficult to unsolder a multi-pin component without destroying it. Wire wrap is a good, fast but rather expensive method for producing prototype digital logic circuits; wire wrap sockets can cost more than the ICs plugged into them. The six (or so) turns of wire round the square wire wrap pin (or post) produce a reliable contact with no possibility of the 'dry' joint associated with soldering. The modified wrap, which puts one turn of un stripped wire round the bottom of the post, eliminates the problem of the wire breaking if it is flexed. Although wire wrap pins can only be re-used a few times, wire wrapped connections can be removed and replaced more easily and reliably than can soldered ones. A3.3 TESTING A prototype should be built in sections which can be tested independently. This allows faults to be corrected and any design changes incorporated into subsequent sections before they are built. Tracing and correcting faults causes severe problems to the in• experienced designer, and the following advice is an attempt to assist the practical learning process. Faults can be catalogued under three main headings: 1. faulty interconnections 2. faulty components 3. faulty logic design. Finding the cause of faults is simplified to a truly amazing degree if the circuit documentation is complete and up to date. For many circuits, logic probes and an oscilloscope are all that is needed to trace the fault; a logic analyser is required for more complex problems. Interconnection faults can be eliminated by checking to see if a signal leaving an output arrives only at the correct set of inputs. Component faults can be eliminated by checking if the outputs behave in the correct way when input signals are applied. Power supply lines and connections are not normally marked on a circuit diagram and can easily be forgotten when constructing a circuit. Therefore, if a circuit fails to work, first test ifthe power supply connections have been made. Because most digital circuits generate 200 Appendix 3 Designing and testing large current transients during switching, it is advisable to connect a capacitor, of about 10 nf, from the power supply input of each integrated circuit to a good ground connection. If low-impedance power supply lines are used it may be sufficient to use one capacitor, of about 100nf, for four or five chips. If the circuit fails to work correctly after eliminating connection and component errors, then the logic design should be examined closely. The list of possible design errors is almost endless, but, assuming that the design appears correct, the following are fairly common mistakes. 1. Unused inputs have been left floating. 2. A signal at some point in the circuit is the inverse of the one expected. 3. A timing error or asynchronous operation has caused a critical race. 4. The circuit can get into an unexpected state or loop which does not return to the designed operating cycle. It is not always easy to diagnose (1) correctly, as pick-up on the unconnected inputs can produce complex effects. The solution is to connect all unused inputs to the appropriate logic level. (2) is solved by inserting an inverter in the appropriate place. (3) requires an additional delay in one case and a synchronization circuit in the other. (4) is rather more significant, in that, strictly, it would be better to redesign the circuit so that the problem is eliminated. To rescue the current design, components must be added which detect a false state and return the circuit to its correct operation. In any circuit containing registers and flip-flops as control elements, it is prudent to have a means of setting the circuit to a well• defined state both when the power is applied and on demand. The RC circuit shown in Fig. A3.2 holds the reset input of the flip-flop low for a short time after turning on the power and the flip-flop can be cleared at any time by a reset signal.
To other + 5u-=c:=t.~Lj...L.----r eg i st ers
Fig. A3.2 Power-on reset circuit. Answers to problems
Note that for many design problems more than one solution exists although only one is given here.
1 Introduction
1.1 1.3 1.4 B A C D
F F F F F F F T T F T T T F F T T T T T F F F T
1.8 74 10 == 010010102 == 1128 == 4A 16 127 10 == 01111111 2 == 177 8 == 7F 16 193 10 == 11000001 2 == 301 8 == C1 16
1.9 11011102 == 110 10 100110002 == 15210 10110011 2 == 179 10 1.10 For E = r x nand rft = constant,
dE = 0 when loge r = 1, i.e. r = e and nearest integer is 3. dr
2 Basic gates 2.1 (a) R = 23 and N = 2R = 28 = 256. (b) N = 232 = 4294976296 2.3 Fl =F2 202 Answers to problems
2.5 F1 = If-jj-c + Xjj-c + A-jj-C F2 = Xjj-c + A-jj-C + A-B-C + A-B-C F3 = A-jj-C + Xjj-c + A-jj-C + A-B-C 2.6 F1 =Xjj+jj-c F2 = jj-c + A-B F3 = jj-c + A-C + A-jj
2.7 (a) 118 10 =011101102 F118=16+1s+14+12+11 (b) 173 10 =101011012 :_ F173=17+1s+13+12+10 Fx=17 +16 +12 +10 :_ X = 11000101 2 = 19710 2.8 F=XC-V+A-B-D+B-C 2.9 F = A-jj-V + jj-c-v + CoD or A-jj-C + jj-c-v + CD 2.10 F=A-B+A-C+A-D+B-C-D 2.11 Taking 1 as a prime F = jj-C-D + B-C-D + XD + Xc + Xjj_ 2.12 Potential static hazard on change between XB-C-V and XB-C-V_ To remove hazard, add loop XB-V_ 2.13 F = Xv + jj-v 2.14 F = Xjj-c + XC-V + Xjj-v + jj-c-v + A-B-C + A-CD +A-B-D+B-C-D 2.15 F = A-B-C + XB-C + A -D for word (DCBA) with D msb_ 2.16 F = A-D + B-C or A-C + B-D 2.17 XOR gates can be used to invert signals, i_e_ produce the NOT function, but applying inverted signals to an XOR only results in XOR or Equivalence (XOR)_ As XORs cannot be used to generate AND or OR functions they cannot be a universal logic element. 2.18 OR(A, B) = c is true for truth table rows 1, 2 and 3; AND (A, B) = d is true for row 3_ NOT(d) ANDed with c gives function true for rows 2 and 3, i_e_ XOR(A, B)_ 2.19 Use ANDs and ORs to derive the following signals: (a) 1 or more inputs true; (b) 2 or more inputs true; (c) all 3 inputs true_ NOT (b) = d and corresponds to 1 or less inputs true_ AND(a, d) = e is true when only 1 input is true_ OR(c, e) = 1 is true if 1 or 3 inputs are true_ NOT(f) = g is true if 0 or 1 inputs true_ Now have signals d(O, 1), b(2,3), g(0,2) and 1(1,3) which can be used in pairs to get unique signal corresponding to 0,1,2 and 3 inputs true, e_g_ AND(d, g) is true if 0 inputs true_ That's the hard bit! The rest is just lots of ANDs and ORs_ If AND(d, g) is true then set all three outputs to true_ If AND(b, f) is true set all outputs to false_ If AND(d, f) = i is true then 1 Answers to problems 203
input (X, say) is true, then AND(X, i) = j is true (AND(Y, i) and AND(Z, i) are false). Usej to set outputs Y and Z to true. Continue in this way. In general, m inverters can invert n input lines where 2m - 1 = n. Three inverters can invert seven signals. 2.20 To recognize when one or three inputs are true, use the parity circuit described in section 3.6.
3 Gating circuits
3.1 For G = G1 + G2
G B A Y3 Y2 Y1 Yo
H X X H H H H L L L H H H L L L H H H L H L H L H L H H L H H L H H H
3.2 If inputs correspond to true, the false output set are all high and the AND output is high; if inputs correspond to false, then one output of the false output set is low and the AND output is low. 3.4 See data book for circuit diagram of 74LS43A. 3.5 See data book for 74LS47. 3.6 See data book for 74LS148. 3.7 Using active high logic. Use BCD to decimal decoder to obtain one active line for each input code. Two-in OR gates are used between decoder and LED drivers. Output 9 is connected to the LED 10 driver and to OR gate; output 8 is connected to the other input. The OR gate output is connected to LED 9 and an OR gate input; output 7 is connected to the other input, etc. 3.8 Input (ZYX), i.e. Z is the most significant bit
LEDs off for invalid codes Don't care if code invalid a=d=X'Y'Z+X'Z+ Y·Z X'Y+Z b=e=X'Y'Z Y·Z c=f= X·Y+ Y·Z X+Z g= X'Y+X'Z X 204 Answers to problems
3.11 Input (DCBA); output (Z Y X W); D and Z are the most significant bits. W=A, X=A-S+A'B, y=A-S'C+A'C+B'C, Z=A'C+ B· C + D. Note that full input decoding would need one more product term. 3.12 Input (CBA); output (ZY XWVU). U=O, V=A'S+A-B, W=B'C+S'C, X=A'B+A'C+B'C, Y= A'C + S'C, Z = B·C. Note there are seven different product terms. PLA is three-in seven-term six-out. The PROM has eight terms. 3.13 Each of the 12 product terms contains one row bit non-inverted and the rest complemented and one column bit non-inverted and the others complemented. Connect the product terms to the OR gates to produce the required output patterns, e.g. for the lsb, connect to ANDs selecting keys 2, 4, 6, 8, 0 and #. 3.14 Implement Fl = A'S'C + A-B + B'C, F2 = A'S + C. 3.15 See data book for 74LS47 logic functions. 3.16 Connect SUM(A, B) from the first half adder to the second half adder with Ci. The SUM output is the full-adder sum. Connect both carry outputs to the third half adder. The SUM output is Co. N.B. both 'carry's cannot be 1. 3.18 (a) to (e) valid; (f) and (g) outside range. 3.19 For eight-bit 2's complement, bits 6-0 hold the value and bit 7 is the sign bit. For C = ADD(A, B), if A and B are of different signs, then C must be in range; if A and B are the same sign, then C will be the same sign if in range and of the opposite sign if out of range. - -- Out of range = A7·B7·C7 + A7·B7 ·C7. 3.20 For inputs (DC) and (BA) and outputs (ZYXW) W=A'C, X=A-B·C+A-S·D+A·C·D+B·C·i5, Y=A-B'D+ B'C'D, Z = A·B·C-D. Eight terms are needed; nine canonical terms are non-zero. 3.21 See data book for 74LS85. AND of Equivalence between each pair of bits gives equality. 'Greater than' is found by comparing bits from the most significant down; the first non-equal pair determines the output state.
4 Latches and flip-flops 4.1 X = 0, Y = 1 is the input state in which the other gate inputs Answers to problems 205
determine outputs (quiescent state). Critical race if X 1->0 and Y 0-> 1 simultaneously. Therefore the forbidden input state is X = 1, Y = O. For all other input states QA = QB = Q. The next-state equation is Q + = X + Q. Y. Critical race is followed one gate delay later by XO-> 1. 4.4 Use critical race. Apply signals to Fig. 4.1 (c). In addition, use AND of signals to indicate output valid. For signals of arbitrary length, use signals to set SR-FFs then apply outputs to critical race circuit. OR of SR-FF outputs indicates data valid. 4.5 There is no way of distinguishing bounces from real switch operations. A monostable, triggered from the first switch contact, is gated with the switch output to maintain a constant level during the bounce period. If bouncing continues after the monostable period, then output follows bounces until the monostable is again triggered, therefore use a retriggerable monostable. 4.6 Next-state equation refers to Q and not to Q. Q+ = R + Q·S. 4.7 Q+ = C·Q + C·jj 4.9 Glitches are generated by OR gate on QO-> 1 transition. Use AND gate and Q output. 4.10 Use multiplexer, with new and old data as inputs, on data input ofD-FF. Clock then loads the D-FF with new data or reloads it with the old data depending on the control signal to the mux. 4.11 See Fig. 4.18 and equation (4.6). 4.12 Use XOR on control input ofT-FF so that, if new =I old, toggle and, if new = old, don't toggle.
4.14 Time is for C to charge from VL 0.3 V to Vr 1.5 V with Vs 3.5 V 4 t RC and time constant RC = 2.210- , VL = (Vs - Vd (1 - e- / ) + VL , t ~ 100 JlS. 4.15 Form each input signal into a short pulse. Use the short pulse to charge the capacitor to a set voltage (e.g. via diode). The capacitor discharges through R and the output resets when the logic transition point is reached. The output will remain set until a fixed time after the last input. 4.16 Circuit is an asynchronous counter, see section 5.7. If J = K = 0 it stops counting. 4.17 Circuit is a shift register, see section 5.4. With data latches, all outputs are set to the current input Dn on a clock signal. 206 Answers to problems
5 Registers and counters 5.1 The signal to be counted is applied to the clock input of the register. The register output is connected to the adder with 1 as the other number. The adder output is connected to the register input. Consult the data book for timings. Connect the Isb of the register to the carry in of the adder so that for even numbers the carry in is zero and for odd numbers it is 1. 5.2 See answer to Problem 4.10. 5.3 Use a decoder to select which multiplexer in Problem 5.2 is set for new data and to keep the others set to retain data. 5.4 Use a three-bit counter with decode for one state (e.g. 0) to clock D-FF with new/old as data input. The output of the D-FF controls the multiplexer for old/new data into the shift register. 5.5 For universal shift registers. Parallel load data into two registers. Connect Isbs (Qo) to adder inputs. Connect ~ output to the serial input of the output register and Co to the data input of a D-FF. The output ofthe D-FF is connected to the Ci ofthe adder. Use the clock to shift data (left) into output register, load Co into the D-FF and shift data (left) in input registers, so that new data is applied to adder. At the end of the add cycle, the input registers are empty, the sum is stored in the output register with the msb in the D-FF. Note that one of the input registers can be used as the output register. 5.6 Starting from all zeros the sequence lasts 10 cycles. 0, 1,3, 7, 15,31,30,28,24, 16. Other sequences are 2, 5, 11, 23, 14, 29, 26, 20, 8, 17 4, 9, 19, 6, 13, 27, 22, 12, 25, 18 10,21 5.7 All registers are set to zero if F is satisfied F = XB'V + S'C-V + A'S'D + B'C'D or = XB'C + XC-V + A'S'C + A'C'D 5.8 For sequences A -+H and I -+P, select state in one sequence, D say, and force a jump to state, K say, in the other sequence. Cycle through to J then jump back to E. For the four-bit twisted ring counter not inverting the bit on selected states is sufficient (cf. Fig. 5.6). Four sets can be used: no flip on (a) 1 or9; (b) 3 or 11; (c) 14 or 6; (d) 12 or 4. 5.9 Sequence is 1, 2, 4, 9, 3, 6, 13, 10, 5, 11, 7, 15, 14, 12, 8. Detect zero and flip feedback bit using XOR as in Problem 5.8. Detect 8 and flip feedback bit so that next state is O. Add to logic of previous part. Answers to problems 207
5.10 Original state 0 1 2 3 4 5 6 7 Up --+ down changes state to 0 7 6 5 4 3 2 1 Down --+ up changes state to 6 5 4 3 2 1 0 7 5.11 Reset on Q3' Q2' Ql' Qo' State diagram has transient only at 10, 11 and higher count up to 15 and then resume normal sequence, 5.12 For states not in main sequence Present state 10 11 12 13 14 15 Next state 11 1 13 5 15 1 5.13 Present state 0 1 2 3 4 5 6 7 Next state 1 2 4 4 5 2 0 0 5.15 Present state 0 1 2 3 4 5 6 7 Next state 1 2 3 4 0 2 6 4 Detect 6 and force one FF to toggle on next clock, 5.16 JKA = 1, JKB = QA'QC' JKc = QA'QB + QA'QC Present state 0 1 2 3 4 5 6 7 Next state 1 2 3 4 5 0 7 2 5.17 J A= QB + Qo KA = 1, JB= QA' KB = QA + Qc, J c = QA'QB' Kc = QB Present state 0 1 2 3 4 5 6 7 Next state 1 2 3 4 5 6 0 0
5.18 J A = Qc,(j + Qc'U + QB,KA = 1, J B = Qc,(j + QA'U. KB = QA,(j + QA'U, J c = QA'QB' (j + QA'QB'U, Kc = 1
U=o U= 1
Present state 0 1 2 3 4 5 6 7 o 1 2 345 6 7 Next state 4 0 2 3 2 1 2 1 2 3 402 3 0
5.19 DA = QA' DB = QA'QB + QA'QC' Qc, Dc = QA'QB + QB'QC Present state 0 1 2 3 4 5 6 7 Next state 3 2 3 4 5 6 1 4 5.20 J A = KA = QB'QO J B= KB = 1, Jc = Kc = QB
5.21 JKA = QA'QB'QC'Qo + QA'QO' JKB = QA'QO + QB'QO + Qc'Qo + QA'QO' JKc = QA'QB'QC + QA'QB + QA'QO' JKo = QA'QB'QC + QA'Qo Not in main sequence Present state 10 11 12 13 14 15 Next state 14 4 13 3 3 1 208 Answers to problems
5.22 DA = QB'QC + QB'QO DB = QA'QC + QA'QB' Dc = QA'QC + QA'QB 5.23 J A = QB'QC'QO + QB'QO' KA = QB'QO + QB'QO' J B= QA'Qo, KB = QA'QO' JC:::!:QA'QB'QO' Kc=Qo, Jo=Qc, KO=QA'QB Not in main sequence Present state 4 5 7 12 13 15 Next state 13 15 14 0 8 9 Any contiguous set of 10 states which form a closed loop on the Karnaugh map, where the loop is symmetric about the line dividing the map into halves with the msb 0 and 1, e,g" 0, 1, 3, 7, 5, 13, 15, 11, 9, 8,
6 Memories
6.2 512 by two-bit = 1024 memory cells = 32 by 32 array, Therefore there are five row decoder lines and four multiplexer lines, 2 k by four bit = 213 and does not give square memory cell array, 6.3 Active totem-pole outputs must not be connected together, 6.4 Write into the memory at the address given by the counter and then increment the counter; decrement the counter and then read from the memory, Make the counter length equal to the memory length, If the counter goes to zero after write then the memory is full; ifthe counter goes to zero on read then the memory is empty, 6.5 See data book on 74LS222, 6.6 Use four single-bit full adders to add together three bits at a time (A, B, Ci), Second stage uses two two-bit adders and the final stage uses a four-bit full adder (a three-bit adder, if it existed, would do),
7 The analogue connection 7.1 Assume all resistors have value nR(1 + In) where In is normally distributed, Half full scale is likely to be the worst point for monoticity (transition from 7 to 8),
V =~(2_ 154 _ 158 _ M6) V8=~(~- 152) 7 2R 8 2 4 8' 2R 8 1 Errors add in quadrature and the sum must be less than the step Answers to problems 209
size. Total error ~ = 15(1 + .25 + .0625 + .0156)1/2 ~ 1.215, 1.215 = 0.125, 15 ~ 0.10. To ensure monoticity 15 should be about three standard deviations (a). Therefore a ~ 3%. For eight-bit DAC 1.215 = 7.8 10- 3, a ~ 0.2%. 7.2 For symmetricladder and input code 10, output = 2/3 x 10/16 x 5 V = 2.08 V. For on switches one at a time, current through a switch is 5/3 rnA. At each junction moving up or down the ladder this current is split into two equal halves. Bottom end (r 4 + 2-2)5/3 Topend(r 1 + r 3 )5/3 = 0.52 rnA. = 1.04 rnA. 7.3 Output voltage is proportional to code and ladder resistance is constant independent of code. Short-circuit current equals output voltage divided by ladder resistance and is, therefore, proportional to code. 7.4 Basic equations are: unipolar (a) resistance I/Rl + I/R2 = 1/4kn, (b) gain (Rl + R2)/R2 = G; bipolar (a) resistance I/Rl + I/R2 + I/R3 = 1/4kn, (b) OV out at mid scale I/Rl + I/R2 = I/R3' (c) -GV out at 0, G·R3 =R1• 7.5 Estimated value. For lO-bit DAC the average step size is 10- 3 V. Monotonic if all steps 10 - 3 ± lO - 3 V, i.e. 3a is 10 - 3 V. Therefore a ~ 3 x 10-4 • Integral non-linearity is a measure of the maximum distance from the best fit line. Add up random step size errors over about a quarter of the range to give an estimate of non-linearity. Deviation ~ 3 x 10-4 (256)1/2 V ~ 5 x 10- 3 V, i.e. t% of full range. 7.9 Maximum frequency = l/256n500 x 10-9 = 2.5 kHz. 7.10 Transfer data to the display register either (a) on alternate clock cycles or (b) when the counter is counting up (or down but not both). 7.11 Display every six clock cycles. 7.12 Maximum frequency = l/256nl5 x 10- 6 = 83 Hz.
7.13 A3 = Cs, A2 = C12 + C4 ·CS' Al = C14 + C lO ·C12 +C6 ·CS +
C 2 ·C4 , Ao = C15 + C 13·C14 + Cll·C12 + C9 ·ClO + C7 ·CS + CS ·C6 + - - C 3 ·C4 +C1 ·C2• Further reading
Some general texts on digital electronics. Almani, A. E. A. (1989) Electronic Logic Systems, Prentice-Hall. Lewin, D. (1985) Design of Logic Systems, Van Nostrand Reinhold. McCluskey, E. J. (1986) Logic Design Principles, Prentice-Hall. Malvino, A. P. (1986) Digital Principles and Applications, McGraw-Hill. Mano, M. M. (1984) Digital Design, Prentice-Hall. Prosser, F. P. and Winkel, D. E. (1987) The Art of Digital Design, Prentice• Hall. Tocci, R. J. (1985) Digital Systems, Prentice-Hall.
Texts on specific areas. Bostock, G. (1987) Programmable Logic Handbook, Collins. Carr, J. (1987) Digital Interfacing with an Analogue World, TAB. Clayton, G. B. (1986) Data Converters, Macmillan. Ercegovic, M.D. and Lang, T. (1985) Digital Systems and Hardwarej Firmware Algorithms, John Wiley. Glasser, L. A. and Dobberpuhl, D. W. (1985) The Design and Analysis of VLSI Circuits, Addison-Wesley. Gorsline, G. W. (1986) Computer Organization, Prentice-Hall. Kampel, I. (1987) New Logic Symbols, Butterworths. Mead, C. and Conway, L. (1980) Introduction of VLSI Systems, Addison• Wesley. Osborne, A. (1980) An Introduction to Microcomputers, McGraw-Hill. Stone, H. S. (1982) Microcomputer Interfacing, Addison-Wesley.
Most of these books receive frequent updates and so no publication date has been given. A-D Conversion Handbook, Analogue Devices, Prentice-Hall. AjD and DjA Conversion Manual, Motorola Semiconductor Products. Further reading 211
CMOS data books and books on advanced and high-speed CMOS integrated circuits are available from most manufacturers of such devices, e.g. Cypress, Harris (RCA), Motorola, National Semiconductor and Philips. Data Converters and Reference ICs, Ferranti. Integrated Circuit Memory Data, Hitachi. M ECL Device Data, Motorola Semiconductor Products. MECL System Design Handbook, Motorola Semiconductor Products. MOS Memory Data Book, Texas Instruments. PAL Device Handbook, Advanced Micro Devices. Programmable Logic Data Book, Texas Instruments. Systems Design Handbook, Monolithic Memories. The TTL Data Book (Vols 1 and 2), Texas Instruments. TTL data books and books on other TTL logic families are available from most manufacturers of the devices, e.g. Fairchild, Motorola, National Semiconductor and Philips.
Original texts. Boole, G. (1849) An Investigation ofthe Laws of Thought, reprinted by Dover Publications N.Y., 1954. Clare, C. R. (1973) Designing Logic Systems Using State Machines, McGraw• Hill, N.Y. Hamming, R.W. (1950) Error-detecting and error-correcting codes, Bell Syst. Tech. J., 29, 147-60. Karnaugh, M. (1953) The map method for synthesis of combinational logic circuits, Trans. AlEE. Comm. and Electronics, 72, 593-9. McClusky, E. 1. (1956) Minimization of Boolean functions, Bell Syst. Tech. J., 35, 1417-44. Mealy, G. H. (1955) A method for synthesising sequential circuits, Bell Syst. Tech. J., 34, 1045-79. Moore, E. F. (1956) Gedanken-experiments on sequential machines, Ann. Math. Stud., 34, 129-53. Quine, W. V. (1952) The problem of simplifying truth functions, Am. Math. Mon., 59,521-31. Shannon, C. E. (1938) A symbolic analysis of relay and switching circuits, Trans. AlEE, 57, 713-23. Veitch, E. W. (1952) A chart method for simplifying truth functions, Proc. Ass. Comput. Mach., May, 127-33. Index
Accuracy, DAC scaling, 158 Backlash, 187 Acquisition, data, 146 BCD (binary coded decimal), Adder 34 binary, 54 Boole, George, 2 decimal, 60-1 Borrow, binary, 62 full, 56, 57-9 Bounce, contact, 77 half,55 Breadboard, demountable, 35 parallel, 56 Buses, 138, 186, 187 Addition, binary, 54-60 unidirectional, 138 Address, memory, 131 bidirectional, 138 Algebra, Boolean, 2, 15-18, 178-9 Cables, twisted pairs, 191 identities, 178 Canonical form, 179 laws, 178 Can't happen states, 27 rules, 178 Carry American standard code for binary, 55 information exchange input, 55 (ASCII),52 look ahead, 59-60 Analysis, sentence, 2-4 output, 55 Arbitrary signal generation, 157 Carry-generate, 60 Architecture, memory, 133-7 Carry-propagate, 60 Aristotle, 2 Charge, stored, 189 Arithmetic Chip select, 136 floating point, 55 Circuit integer, 55 adder/subtractor, 63 Array CMOS, 193 logic cell (LCA), 54 combinational logic, 6 uncommitted logic, 54 decoder, 38, 39 Index 213
full adder, 56, 57 digital, 69 half adder, 55 Contention, 184 integrated, 6 Control section, 74 logic, 15 Conversion between TTL and logic display, 35 CMOS, 193-5 logic input, 35 Conversion LSTTL gate, 189 analogue to digital, 159-72 memory, 141-2 digital to analogue, 148-58 multiplexer, 43 Converter basic, 29 analogue to digital NMOS, 192 DAC, 165-72 not robust, 101 dual slope, 162-4 parity checking, 47 flash (parallel), 170-2 parity measuring, 47 integrator, 159-65 power on reset, 200 single slope, 160-2 sample and hold, 169 successive approximation, sequential, 73 167-70 sequential logic, 6 tracking, 165-7 successive approximation voltage to frequency, 164 ADC, 176 voltage to pulse rate, 164 track and hold, 169 digital to analogue TTL NAND gate, 183 accuracy and resolution, TTL open collector, 185 158 TTL tri-state, 186 bipolar operation, 153 Circuit reliability, 37 comparison of, 156 Circuit testing, 199-200 microprocessor compatible Clear, synchronous, 114 (ZN428), 152-4 CMOS logic, 192-4 multiplying (DAQ-08), input capacitance, 194 154-7 power consumption, 193 unipolar operation, 153, TTL compatible, 190 156 unused inputs, 193 uses, 157 Code Count sequence, 101 Gray, 128 Count, terminal, 111 Hamming, 47 Counters proportional, 149 asynchronous, 103, 104-10 reflected binary, 128 down, 105 Code converter, 40 modulo-n, 107-10 keyboard, 51 modulo-8, 104 Comparator self-stopping, 109 analogue, 159, 170 up, 104 214 Index
up or down, 106 Device, field programmable, 50 program, 95 Diagrams, 196-8 register and adder as, 95 block, 196 ring, 100-3 circuit, 196 divide-by-n, 100 DAC ZN428, 152 switch-tail, 100 DAC-08,155 twisted, 100 successive approximation ripple, 104 ADC, 168 synchronous, 103, 110-25 tracking ADC, 165 binary up, 110 layout, 196 binary down, 113 state, 103, 122 decade using D-FFs, Veitch, 10, 21 123-4 Dice, electronic, 68 modulo-5 using JK-FFs, Difference, binary, 62 115-18 Differential pairs, 190 modulo-5 using T-FFs, Display 118-20 Karnaugh map, 71 modulo-3 up/down using seven segment, 68 JK-FFs, 120-3 Division, binary, 66 up/down, 113 Don't care states, 27 Critical race, 75, 79 Cycle Edge controlled devices, 78 memory read, 138-41 Efficient logic, 20 memory write, 138-41 Emitter coupled logic (ECL), 190-1 Darlington pair, 189 Encoder, priority, 68 Data flow, 73 Equation, next-state Data link, serial, 44 data latch, 79 Debouncer, switch, 77 D-FF,82 Decoders, 37-42 JK-FF,85 as logic elements, 41 SR-FF,76 De Morgan's theorem, 18, 179 Error, quantization, 159 Demultiplexer, 40 Errors Dependency, address, 134 circuit design, 200 Description, outline, 196 correction of, 47 Design single-bit, 46 custom, 54 Essential terms, 180 semi-custom, 54 Excess-3, 67 synchronous system, 115 Expression Design limitations, single slope canonical, 21 ADC, 162 logic, 15 Index 215
Fan out capability, A184 Hazard-free operation, 30, 181 of ECL, 191 Hazards, 28-30 Fault tracing, 196 elimination of, 30 Finite state machine, 96 single static, 29 Flip-flops, 73-94 Hi-z, 186 data (D-FF), 80-2 Hysteresis, 187, 195 edge-triggered D-FF, 81 edge-triggered JK-FF, 85 IEC (International Electro• JK-FF,84-6 technical Commission) master-slave D-FF, 80 symbols, 14 master-slave JK-FF, 85 Implementation set-reset (SR-FF), 74-7 NAND, 24-5 toggle (T -FF), 86-7 NOR, 24 Format Inputs bit, 5 asynchronous, 81 hexadecimal, 5 control, 38 octal, 5 dynamic, 82 Frequency measurement, 96 enable, 38 Full adder, see Adder, full expansion of, 40 Function floating TTL, 184 AND, 2 history of, 73 change, 120 Schmitt trigger, 187-8 Equivalence, 17 synchronous, 78 excitation Integrator circuit, 161 data latch, 79 D-FF,82 JK-FF, 85, 115 Keypad, telephone, 69 SR-FF,76 Exclusive-NOR, 17 Ladder Exclusive-OR, 3 R-2R (binary), 149-52, 155 NAND, 18 symmetrical R-2R, 151 NOR, 18 Latches, 73-94 NOT, 2 addressable, 168 OR, 3 data, 77-80 Fuses, 49 transparent, 137, 141 Level shifting, 194 Glitches, 28-30 Limit, ADC frequency, 166, 169 Ground, analogue and digital, Linearity of conversion, 158 152 Lines memory address, 131 Half adder, see Adder, half memory cell control, 133 216 Index
memory cell data, 133 random access (RAM), 131, product, 51 132-3 sum, 51 dynamic (DRAM), 133 Links, fusible, 49 static (SRAM), 133 List, chip read only (ROM), 48, 131 A/D conversion, 173 mask programmable analogue, 172 (MROM),132 counter, 126 programmable (PROM), D/A conversion, 172 50, 132 flip-flop, 90 erasable programmable gate (MSI), 66-7 (EPROM), 48, 132 gate (SSI), 32 electrically erasable latch, 90 (EEPROM), 132 memory, 142-3 volatile, 48, 133 programmable logic, 67 Memory address, 48 register, 125 Memory expansion, 137 Load, synchronous, 114 Minimization, 20-4 Logic algebraic, 21, 179-81 encoder, 170 graphical, 21, 179-81 glue, 74 limitations of, 25-7 multi-stage, 25 product of sums, 181 programmable, 49-54 Min terms, 14 random, 74 Mode control, 98 reprogrammable, 49 Mode dependency, 87 Logic function, equality, 178 Model Logic levels Mealy, 122 LSTTL,190 Moore, 122 TTL,193 Monotonicity of DAC, 158 Loops, 23 MOS logic, 191-3 LSI (large scale integration), 8 MSI (medium scale integration), 8 Maps, Karnaugh, to, 21 Multiplexers, 29, 42-4 layout of, 22 as logic elements, 45-6 Matrix, memory cell, 134 as open-collector gates, 44 Max terms, 14 as tri-state gates, 44 Memories as logic elements, Multiplication, binary, 64 48-9 Multiplier, parallel, 66 Memories, 131-42 Multivibrators, 87-90 first-in/first-out (FIFO), 143 astable, 87 last-in/first-out (LIFO), 143 bistable, 87 non-volatile, 48, 132 monostable (one-shot), 87 Index 217
retriggerable monostable, 89 Prime implicants, 180 MUX, see multiplexers Product, partial, 64 Product of sums, 24 Network, steering, 84 Programmable array logic Noise, quantization, 159 (PAL), 52 Non-linearity Programmable logic array differential, 158 (PLA),50 integral, 158 Programmable logic device Notation (PLO), 52, 74 bar, 14 Prototype, 198-9 dependency, 15 Proto typing board, shorthand logic, 50 demountable, 198 Numbers Pull down, active, 183 binary,S Pull up negative, representation of, active, 183 62 passive, 185 Operation, hazard-free, 30, 181 resistor, 185 Oscillator, 188 Pulse, single synchronized CMOS, 195 clock,83 crystal-controlled, 90 simple, 70 Quiescent state, 75 Oscilloscope, digital storage, Quine-McCluskey method of 177 minimization, 179 Output active-low, 98 Radix, 4 current source, 151 Ramp, voltage, 160 open collector, 185-6 Range, adder working, 63 open drain, 195 Reaction time check, 93 ripple-carry, III Reaction time circuit, 130 totem pole, 183 Reference, current, 155 tri-state, 135, 186-7 Registers, 96-100 voltage source, 151 accumulator, 95 Output enable, 137 addressable, 126 memory buffer, 95 Package, OIL (dual-in-line), 7 parallel-in/parallel-ou t Parity, 46-8 (PIPO),96 Parts list, 196 serial-in/parallel-out (SIPO), Patterns 97 die, 68 shift,97 seven-segment display, 68 successive approximation, Power supply decoupling, 199 168 218 Index
universal shift, 98 algebraic Register transfer, 73 Exclusive-OR, 17 Reset signal, circuit, 200 inversion (NOT), 14, 178 Ripple-carry output, 111 logical product (AND), 14, 178 Sampling theorem, Shannon's, logical sum (OR), 14, 178 170 alternative circuit, 31 Schmitt input, 30 basic circuit, 14 Sets, 178 circuit Sequences AND,14 closed, 118 clocked SR latch, 78 maximal length, 102 data latch, 78 pseudo-random binary decoder, 39 (PRBS), 102 demultiplexer, 39 Signal D-FF,81 latch clear, 80 Equivalence, 17 latch set, 80 four-bit counter, 112 over range, 164 full adder, 59 wrong polarity, 164 inverted-input AND, 31 Signal generator, digital, 177 inverted-input buffer, 31 Soldering, 198 inverted-input OR, 31 SSI (small scale integration), 8 JK-FF,85 States, unused, 116 monostable, 88 Strobe, 172 multiplexer, 43 Structure of NAND,18 PAL,53 NOR,19 PLA,53 NOT,14 PROM,53 OR,14 Subtractor, binary, 62 RAM,136 Subtraction ROM,135 binary, 62-4 shift register, 97 trial, 66 SR-FF,76 Sum, binary, 55 T-FF,87 Sum of products, 21 XOR,16 Switch common control block, 43 analogue, 149 Synchronization single-pole double-throw by clock, 30 (SPDT),77 of signals, 83-4 Switches System, electronic dice, 130 as AND gates, 24 as OR gates, 24 Table, current-state/next-state, Symbols 115 Index 219 D-FF decade counter, 123 NAND,18 JK-FF modulo-3 counter, NOR,19 121 NOT,14 JK-FF modulo-5 counter, OR,14 115 sparse, 50 T-FF modulo-5 counter, 118 time ordered, 75 Terminal count, 111 XOR,16 Terms, essential, 23 Theorem, De Morgan's, 18, 179 Universal logic elements, 18-19 Time hold,80 Value set up, 80 input, 12, 17 Timing constraints output, 12, 16 counter, 166 Variables memory, 139 logic, 14 Transfer characteristic, 11 two-state, 178 Transistor transistor logic VLSI (very large-scale advanced low power integration), 8 Schottky (ALS), 190 Voltage, reference, 149 Fairchild advanced Schottky Voting machine, 34 (FAST), 190 Schottky, 189-90 Weights, 148 TTL, 11,32, 182 Wire wrap, 199 Transition region, 11 Wired Transparent latch, 78 AND,185 Truth tables, 2-4 OR,185 AND,14 Write enable, 135 buffer, 14 Wrong sequence construction of, 12 correction, 102 decoder, 38, 39 detection, 101 Equivalence, 17