APPENDIX 1 Boolean algebra AU RULES Boolean algebra is the name given to the algebra of two-state variables, and it provides a more compact way of representing a logic function than does a truth table. Below are given the rules, laws and identities of Boolean algebra; their validity may be checked by the use of truth tables. The three basic operators AND, OR and NOT are used to construct logical expressions, where 1. A· B represents AND(A, B) (logical product), 2. A + B represents OR(A, B) (logical sum), 3. A represents NOT(A) (INVERT A or complement of A). Equality If A has the same logical properties as B (i.e. the same truth table), then A = Band B = A. If A = B and A = C, then B = C. Sets If A and B are subsets of k, then A· B and A + B are subsets of k. o is the empty set and 1 is the complete set. Laws Boolean algebra is commutative A·B=B·A and A+B=B+A Boolean algebra is associative A + B + C=A + (B + C) = (A + B)+C A·B·C = A ·(B·C) = (A·B)·C Boolean algebra is distributive A ·(B + C) = (A· B) + (A· C) A +(B·C)=(A + B)·(A + C) Algebraic minimization 179 Identities AND OR INVERT A'O=O A+O=A A+A=l A·l =A A + 1 = 1 A'A=O A·A=A A+A=A A=A A'A=O A+A=l Auxiliary identities A + (A' B) = A and A + (A- B) = A + B De Morgan's theorem states that if, in any Boolean function, each logical sum is replaced by a logical product, each logical product by a logical sum and each variable is replaced by its complement, the result is the complement of the original function. Therefore A·B···· =A+B+ ... A+B+···=A-B····. Note that, conventionally, the logical product symbol is implied, so that, AND(A, B) is represented by AB. The symbol has been used explicitly above to show the symmetry in the algebra between the AND and OR functions. Al.2 ALGEBRAIC MINIMIZATION The Quine-McClusky method for minimization is described here with the aid of an example to illustrate each step. The method minimizes a function into a sum-of-products form. The equivalent action in Karnaugh map minimization is indicated. Consider the function f = A·jj·C·jj + A-B'C'D + B·C·(A + D)+ A·B·D. 1. Expand to the sum-of-products canonical form. That is, expand all product terms (using X = X' Y + X' Y) so that they contain all variables explicitly, and remove all multiple occurrences of the same term (using X' Y + X' Y = X' Y). (Plot the function on the Karnaugh map.) f = A-B'C'D + A-B'CD + A-B'C'D + A·B·C·D + A·B·C·jj + A·jj·C·jj. 180 Appendix 1 Boolean algebra 2. Write out a list of the product terms and compare each term with every other term looking for pairs of the form W· X . y. Z and W- X· y. Z. That is, terms which differ in the state of only one variable. Mark both members of the pair and draw up a new list of the reduced terms W· X· Y. Do not remove marked terms from further comparisons. Remove any multiple occurrences from the new list. Save the unmarked terms; they are called prime implicants. Repeat the procedure until no further reductions are possible. (Loop all single 1s that cannot be looped in pairs, then pairs that cannot be looped in fours, etc. The prime implicants correspond to the loops on the map.) A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·fj A·Ii·cfj 2 1 3 1 2 4 3 45 6 5 6 A·B·D B·C·D B·C·D A·B·D A·B·C A·C·fj 1 2 2 1 B·D (B·D). The terms which can be reduced have been marked with a number under the complementing variable to make it clear which terms have been used to obtain the new lists. 3. The next step is to find the essential terms. Writing the prime implicants in a column and the canonical terms in a row, mark where a canonical term is part of a prime implicant. A prime implicant associated with a column with only one mark is an essential term. The minimized function is the sum of the essential terms and the simplest set of other prime implicants to give at least one mark in each column. (Select the simplest set of loops.) XB·C·D XB·C·D A·B·C·D A-B·C·D A·B·C·V A·jj·C·V B·D X X X X A-B·C X X A·C·V X X Essential terms are B· D and A· C· fj and they are sufficient to cover all canonical terms. The final minimized function is f= B·D + A·C·fj. Note that, all prime implicants may not be required for a Minimization in product-oj-sums Jorm 181 minimized function but all are needed for hazard-free operation (section 2.10). A1.3 MINIMIZATION IN PRODUCT-OF-SUMS FORM In general, people find it easier to work with logic functions in the sum-of-products form. Because of the relationship between sum-of­ products and product-of-sums expressions, a convenient method of minimizing in product-of-sums form is to minimize the inverse function in sum-of-products form and then apply De Morgan's theorem. Using a map, the function is plotted on the map and then each element is inverted (all ones are changed to zeros and zeros to ones) to give the inverse function. For the algebraic method, find the canonical expression and then the inverse function is all the terms not in that expression. Minimize in the normal way to give a sum-of-products form for the inverse function and apply De Morgan's theorem to obtain a product-of-sums form. For example, if 1 = (A·B·C·D) + (A-ii·D) then De Morgan's theorem gives J = (A + Ii + C + D)·(A + B + 15). APPENDIX 2 Logic families A2.1 TTL CIRCUITS Transistor-transistor logic (TTL) was the first major integrated­ circuit logic family. It uses bipolar junction transistors and runs from a 5 V power supply. The circuit for a standard TTL NAND gate is shown in Fig. A2.l(a). The circuits for other families of TTL look somewhat different, but operate in fundamentally the same way. The basic input and output voltage levels for standard TTL are given in Table A2.1. The difference between the limits for input and output levels is to allow for noise induced on the connections between devices. From the data in Table A2.l it is seen that TTL has a noise margin lor immunity) of 0.4 V at both logic levels. In Fig. A2.l(a), the states of the transistors and the voltage levels through the circuit are given for all inputs logic high (> 2.0 V). Figure A2.l(b) shows the states and voltages when one input is logic low (0.2 V in this case). When all inputs are high, the base-emitter junctions of T 1 are reverse biased but its base-collector junction is forward biased, and this supplies current to T 2 and T 3, i.e. T 2 and T 3 are turned on and saturate. The voltage between the base of T 4 and the output is only about 0.7 V and, as this is across two p-n junctions (T 4 and D 1)' T 4 is turned off. With T 4 off and T 3 on, the output is governed by T 3. The output voltage is VSAT for T 3, which is about 0.2 V, and this increases to about 0.4 Vas the current into the output is increased to 16 rnA. (It is customary to define the direction of currents as into inputs or outputs, and, therefore, as T 3 provides a current sink, the value is positive.) The current to maintain an input at the logic high level is the TTL circuits 183 Out i6mA max Inputs logic high (>2U) Input logic low (O.2U) Out put log i c low (0. 2U) Output logic high (3.3U) (a) (b) Fig. A2.1 NAND gate with (a) all inputs high, and (b) one input low. Table A2.1 TTL operating voltage levels Min. Typ. Max. VIL Input low level 0.8V VIH Input high level 2.0V VOL Output low level 0.2V 0.4 V VOH Output high level 2.4 V 3.4 V leakage current associated with the reverse-biased emitter-base junction of T 1 and is therefore small ( < 40 J-la). If one or more inputs are taken to a logic low value (the diagram assumes a VL of 0.2 V), then the base-emitter junction ofT 1 is forward biased. The maximum current to maintain an input at the logic low level is - 1.6 rnA. With the voltage at the base of T 1 at about 0.9 V, both T 2 and T 3 are switched off and T 4 is switched on. The output is now governed by T 4' The unloaded output voltage is close to the supply voltage less the voltage drop across two forward-biased p-n junctions (T 4 and D 1), i.e.