The Case for Oversampling

Home , Aliasing, Digital filter, Nyquist rate, Oversampling

EE247 Lecture 24 Oversampled ADCs – Why oversampling? – Pulse-count modulation – Sigma-delta modulation • 1-Bit quantization • Quantization error (noise) spectrum • SQNR analysis • Limit cycle oscillations –2nd order ΣΔ modulator • Dynamic range • Practical implementation – Effect of various nonidealities on the ΣΔ performance

The Case for Oversampling

Nyquist sampling:

Signal fs

“narrow” “Nyquist” DSP transition fs >2B +δ ADC B Freq AA-Filter Sampler

Oversampling: fs >> fN?? Signal

“wide” Oversampled ADC DSP transition fs= MfN B Freq AA-Filter Sampler

• Nyquist rate fN = 2B • Oversampling rate M = fs/fN >> 1

|X(f)| Input Signal

frequency fB

Nyquist Sampling

f B fs 2fs frequency fS ~2fB Anti-aliasing Filter Oversampling

fB fs frequency fS >> 2fB

Oversampling Benefits

• No stringent requirements imposed on analog building blocks • Takes advantage of the availability of low cost, low power digital filtering • Relaxed transition band requirements for analog anti-aliasing filters • Reduced baseband quantization noise power • Allows trading speed for resolution

EECS 247 Lecture 24: Oversampling Data Converters © 2005 H. K. Page 4 ADC Converters Baseband Noise Δ • For a quantizer with step size and sampling rate fs : – Quantization noise power distributed uniformly across Nyquist

bandwidth ( fs/2) Ne(f)

-fs /2 -fB fB f s /2 – Power spectral density: 22⎛⎞Δ ==e1 N(f)e ⎜⎟ fs ⎝⎠12 fs

– Noise is aliased into the Nyquist band –fs /2 to fs /2

Oversampled Converters Baseband Noise

ff BB⎛⎞Δ2 ==1 SN(f)dfBe∫∫⎜⎟ df −− ffBB⎝⎠12 fs Ne(f) Δ2 ⎛⎞ = 2fB ⎜⎟ NB 12⎝⎠ fs = where for fBs f /2 Δ2 = SB0 -fs /2 -fB fB f s /2 12 ⎛⎞2f S SS==BB0 BB0⎜⎟ ⎝⎠fMs f where M==s oversampling ratio 2fB

⎛⎞2f S SS==BB0 BB0⎜⎟ ⎝⎠fMs f where M==s oversampling ratio 2fB 2X increase in M

Æ 3dB reduction in SB Æ ½ bit increase in resolution/octave oversampling

To increase the improvement in resolution: Embed quantizer in a feedback loop ÆPredictive (delta modulation) ÆNoise shaping (sigma delta modulation)

Pulse-Count Modulation

Nyquist V (kT) in ADC t/T 0 1 2

Oversampled V (kT) in ADC, M = 8 t/T 0 1 2

Mean of pulse-count signal approximates analog input!

Magnitude

• Signal: low frequencies, f < B << fs • Quantization error: high frequency, B … fs / 2 • Separate with low-pass filter!

Oversampled ADC Predictive Coding

+ vIN ADC _ DOUT

Predictor

• Quantize the difference signal rather than the signal itself • Smaller input to ADC Æ Buy dynamic range • Only works if combined with oversampling • 1-Bit digital output • Digital filter computes “average” ÆN-Bit output

f = M f f = f +δ s1 N s2 N Signal E.g. Decimator “wide” Pulse-Count f = Mf “narrow” DSP transition s N Modulator transition Analog Sampler Modulator Digital AA-Filter AA-Filter B Freq 1-Bit Digital N-Bit Digital

Decimator: • Digital (low-pass) filter • Removes quantization error for f > B • Provides most anti-alias filtering • Narrow transition band, high-order • 1-Bit input, N-Bit output (essentially computes “average”)

Modulator

• Objectives: – Convert analog input to 1-Bit pulse density stream – Move quantization error to high frequencies f >>B

– Operates at high frequency fs >> fN • M = 8 … 256 (typical)….1024 • Since modulator operated at high frequencies Æ need to keep circuitry “simple”

Æ ΣΔ = ΔΣ Modulator

Analog 1-Bit ΣΔ modulators convert a continuous time

analog input vIN into a 1-Bit sequence dOUT

fs + vIN H(z) _ dOUT

DAC

Loop filter 1b Quantizer (comparator)

Sigma-Delta Modulators

• The loop filter H can be either switched-capacitor or continuous time • Switched-capacitor filters are “easier” to implement + frequency characteristics scale with clock rate • Continuous time filters provide anti-aliasing protection • Loop filter can also be realized with passive LC’s at very high frequencies

fs + vIN H(z) _ dOUT

DAC

fs fs /M

Input Signal Bandwidth Oversampling 1-bit Decimation n-bit Modulator Filter @ f /M B=fs /2M @ fs s

fs = sampling rate M= oversampling ratio

• Analog front-end Æ oversampled noise-shaping modulator • Converts original signal to a 1-bit digital output at the high rate of (2MXB) • Digital back-end Æ digital filter • Removes out-of-band quantization noise • Provides anti-aliasing to allow re-sampling @ lower sampling rate

1st Order ΣΔ Modulator

In a 1st order modulator, simplest loop filter Æ an integrator

z-1 H(z) = 1 – z-1 + vIN _ ∫ dOUT

DAC

Switched-capacitor implementation

φ φ 1 2 φ 2 - dOUT 1,0 + Vi

+Δ/2

-Δ/2

1st Order ΔΣ Modulator

+ vIN _ ∫ Δ ≤ ≤ Δ - /2 vIN + /2 dOUT

-Δ/2 or +Δ/2 DAC

• Properties of the first-order modulator: – Analog input range is equal to the DAC reference

– The average value of dOUT must equal the average value of vIN – +1’s (or –1’s) density in dOUT is an inherently monotonic function of vIN Æ linearity is not dependent on component matching – Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error but loose this inherent monotonicity & relaxed matching requirements

Tally of 1-Bit quantization error quantizer Analog input 1 2 3 Δ ≤ ≤ Δ X Q Y - /2 Vin + /2 z-1 -1 1-z 1-Bit digital Sine Wave Integrator Comparator output stream, -1, +1

Instantaneous Implicit 1-Bit DAC quantization error +Δ/2, -Δ/2 (Δ = 2)

• M chosen to be 8 (low) to ease observability

1st Order Modulator Signals

1st Order Sigma-Delta X analog input 1.5 X Q Q tally of q-error Y Y digital/DAC output 1

0.5 Mean of Y approximates X 0 Amplitude -0.5

-1 T = 1/fs = 1/ (M fN)

-1.5 0 10 20 30 40 50 60 Time [ t/T ]

• Quantization noise and thermal noise (KT/C) distributed over –fs /2 to +fs /2 Æ Total noise within signal bandwidth reduced by 1/M • Very high SQNR achievable (> 20 Bits!) • Inherently linear for 1-Bit DAC • To first order, quantization error independent of component matching • Limited to moderate & low speed

Output Spectrum

• Definitely not white! 30 • Skewed towards higher 20 Input frequencies 10 • Notice the distinct tones 0

-10

-20

Amplitude [ dBWN ] • dBWN (dB White Noise) -30 scale sets the 0dB line -40 at the noise per bin of a random -1, +1 -50 0 0.1 0.2 0.3 0.4 0.5 sequence Frequency [ f /fs]

Quantization Error e(kT) Integrator −1 = z Σ H(z ) −1 Σ x(kT) 1+ z y(kT) Quantizer Model

• Sigma-Delta modulators are nonlinear systems with memory Æ difficult to analyze directly • Representing the quantizer as an additive noise source linearizes the system

Signal Transfer Function

−1 z x(kT) H(z ) = Σ Integrator −1 y(kT) 1+ z - H(z) ω Hj()ω = 0 jω

Signal transfer function Æ low pass function:

ω = 1 HjSig ()

+ s Magnitude 1 ω 0 Yz() Hz () − f Frequency Hz()== = z1 ⇒ Delay 0 Sig Xz() 1+ Hz ()

22=×⎛⎞f vveq n ⎜⎟ 2 ⎝⎠f0 2 × ⎛⎞f vn ⎜⎟ ⎝⎠f0 ω v vi Σ 0 o - jω

f Frequency 2 0 22=×⎛⎞f vveq n ⎜⎟ ⎝⎠f0 ω v • Input referred-noiseÆ zero @ Σ 0 o ω DC (s-plane) vi - j

STF and NTF

Quantization Error e(kT) Integrator −1 = z Σ H(z ) − Σ x(kT) 1+ z 1 y(kT) Quantizer Model

Signal transfer function: Yz() Hz () − STF== =z 1 ⇒ Delay Xz() 1+ Hz ()

Noise transfer function:

Y (z) 1 − NTF = = = 1− z 1 ⇒ Differentiator E(z) 1+ H (z)

Yz() 1 − NTF== =−1 z 1 Ez() 1+ Hz () jTωω/2− jT /2 −−jTωω jT/2⎛⎞ee− NTF()(1 jω =− e )=2 e ⎜⎟ ⎝⎠2 − ω = 2sin/2ejTjT/2 ()ω =×−−jTωπ/2 j /2 ()ω 2sin/2ee⎣⎦⎡⎤ T = ()ω −−jT()ωπ/2 ⎣⎦⎡⎤2sinTe /2 = where Tf 1/ s Thus: ωπ NTF ()=2sin f() T /2=2sin() f / fs

= 2 Nfy () NTF() f Ne () f

First Order ΣΔ Modulator Noise Transfer Characteristics

= 2 N ye()fNTFfNf () () Low-pass = π 2 Digital 4sin()ff / s Filter

First-Order Noise Shaping Noise Shaping Function Noise Shaping

fB f Frequency N fs /2 Key Point: Most of quantization noise pushed out of frequency band of interest

30 Simulated output spectrum Computed NTF 20 Signal

-10

-20

Amplitude [ dBWN ] Amplitude 2 Nf()= 4sin()π ff / -30 ys

-40

-50 0 0.1 0.2 0.3 0.4 0.5

Frequency [f/fs]

Quantizer Error

• For quantizers with many bits

Δ2 e2 ()kT = 12

• Let’s use the same expression for the 1-Bit case

• Use simulation to verify validity

• Experience: Often sufficiently accurate to be useful, with enough exceptions to be very careful

NTF() z=−1 z−1 22=>>π NTF() f4sin() f / fs for M 1 B 2 SSfNTFzdf= () () Y ∫ Q ze= 2π jfT −B fs 2M 2 1 Δ 2 ≅ ∫ ()2sinπ fT df − fs fs 12 2M

π 221 Δ →≈S Y 312M 3

Dynamic Range

⎡ ⎤ ==⎡⎤peak signal power SX DR 10log⎢⎥ 10log ⎢ ⎥ ⎣⎦peak noise power ⎣ SY ⎦ Δ 2 ==1 ⎛⎞ SSTFX ⎜⎟ sinusoidal input, 1 22⎝⎠ π 22Δ M DR = 1 SY 16 33 dB 312M 3 32 42 dB S 9 X = M 3 1024 87 dB π 2 SY 2 ⎡⎤⎡⎤99 DRM==+10log3 10log 30log M ⎣⎦⎣⎦⎢⎥⎢⎥22ππ22

DR=−3.4 dB ++ 30log M

2X increase in MÎ9dB (1.5-Bit) increase in dynamic range

• ΣΔ modulators have interesting characteristics

– Unity gain for input signal VIN – Large in-band attenuation of quantization noise injected at quantizer input – Performance significantly better than 1-Bit noise performance possible for frequencies << fs

• Increase in oversampling (M = fs/fN >> 1) improves SQNR considerably –1st order ΣΔ: DR increases 9dB for each doubling of M – To first order, SQNR independent of circuit complexity and accuracy • Analysis assumes that the quantizer noise is “white” – Not true in practice, especially for low-order modulators – Practical modulators suffer from other noise sources also (e.g. thermal noise)

DC Input

• DC input A = 1/11 30 20 • Doesn’t look like spectrum 10 of DC at all 0 • Tones frequency shaped -10 the same as quantization -20 noise Æ More prominent at Amplitude [ dBWN ] -30 higher frequencies -40

-50 0 0.1 0.2 0.3 0.4 0.5 Æ Seems like periodic

Frequency [ f /fs ] quantization “noise”

0 6 +1 Output 7 -1 -0.2 8 +1 -0.4 9 -1 10 +1 0 10 20 30 40 50 11 -1 Time [t/T]

Limit Cycle

Ideal Low-pass Digital Filter In-band spurious tone with f ~ DC input

First-Order Noise Shaping Noise Shaping Function Noise Shaping

fB f Frequency N fs /2 • Problem: quantization noise is periodic •Solution: ¾ Use dithering: randomizes quantization noise - Thermal noise Æ acts as dither ¾ Second order loop

−− Yz()=+− z11 Xz ()() 1 z Ez ()

2nd Order ΣΔ Modulator

• Two integrators • 1st integrator non-delaying • Feedback from output to both integrators • Tones less prominent compared to 1st order

=+−+ Recursive drivation: YXnn−−−112() E n 2 E n E n −− −2 Using the delay operator z 11 :Yz ( )=+− z Xz ( )() 1 z 1 Ez ( )

2nd Order ΣΔ Modulator In-Band Quantization Noise

−1 ()= z Hz − 1− z 1 G = 1 − 2 NTF() z=−()1 z 1

2 NTF() f = =>>4 π 4 2 sin()ff /s for M 1

B 2 SSfNTFzdf= () () π YQ∫ ze= 2 jfT −B

fs 2 M 1 Δ2 ≅ ∫ ()2sinπ fTdf4 − fs fs 12 2 M π 42Δ ≈ 1 512M 5

Ideal Low-pass 2nd -Order Noise Shaping Digital Filter

First-Order Noise Shaping Noise Shaping Function Noise Shaping

fB Frequency fs /2

2nd Order ΣΔ Modulator Dynamic Range

⎡ ⎤ ==⎡⎤peak signal power SX DR 10log⎢⎥ 10log ⎢ ⎥ ⎣⎦peak noise power ⎣ SY ⎦ Δ 2 ==1 ⎛⎞ SSTFX ⎜⎟ sinusoidal input, 1 22⎝⎠ π 42Δ MDR = 1 SY 16 49 dB 512M 5 32 64 dB S 15 X = M 5 1024 139 dB π 4 SY 2 ⎡⎤⎡⎤15 15 DRM==+10log5 10log 50log M ⎣⎦⎣⎦⎢⎥⎢⎥22ππ44

DR=−11.1 dB ++50log M

2X increase in MÎ15dB (2.5-bit) increase in DR

•Digital audio application •Signal bandwidth 20kHz •Resolution 16-bit

16−→bit 98 dB Dynamic Range

DR=−11.1 dB ++ 50log M = M min 153

M Æ 256=28 to allow some margin & also for ease of digital filter implementation Æ Sampling rate (2x20kHz + 5kHz)M = 12MHz

Higher Order ΣΔ Modulator Dynamic Range L Yz( )=+− z−−11 Xz ( )() 1 z Ez ( ) , L →ΣΔ order Δ 2 ==1 ⎛⎞ SSTFX ⎜⎟ sinusoidal input, 1 22⎝⎠ π 22L 1 Δ S = Y 21L + M 21L+ 12 32()L + 1 SX = 21L+ 2L M SY 2π ⎡⎤32()L + 1 DR=10log M 21L+ ⎢⎥π 2L ⎣⎦⎢⎥2

⎡⎤32()L + 1 DR =+10log() 2LM+×110log × ⎢⎥π 2L ⎣⎦⎢⎥2 2X increase in MÆ(6L+3)dB or (L+0.5)-bit increase in DR

L=3

L=2

L=1

• Potential stability issues for L >2

Tones in 1st Order & 2nd Order ΣΔ Modulator

• Higher oversampling st ΣΔ ratio Æ lower tones 6dB 1 Order Modulator

•2nd order much lower tones compared to 1st 12dB 2nd Order ΣΔ Modulator •2Xincrease in M decreases the tones by 6dB for 1st order loop and 12dB for 2nd order loop

Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618 - 627, April 1991. R. Gray, “Spectral analysis of quantization noise in a single-loop sigma–delta modulator with dc input,” IEEE Trans. Commun., vol. 37, pp. 588–599, June 1989.

IN Dout

Switched-Capacitor Implementation 2nd Order ΣΔ Phase 1

•Sample inputs •Compare output of 2nd integrator •At the end of phase1, S3 opens prior to S1 opening

• Enable feedback from output to input of both integrators • Integrate • Reset comparator • At the end of phase2 S4 opens before S2

ΣΔ Implementation Practical Design Considerations

• Internal nodes scaling & clipping

• Finite opamp gain & linearity

• Capacitor ratio errors

• KT/C noise

• Opamp noise

• Power dissipation considerations

• Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input full- scale (Δ)

Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.

2nd Order ΣΔ Modulator Switched-Capacitor Implementation

• The ½ loss in front of each integrator implemented by choice of:

C2=2C1

• Effect of 1st Integrator maximum signal handling capability on converter SNR

Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.

2nd Order ΣΔ Effect of Integrator Maximum Signal Handling Capability on SNR

• Effect of 2nd Integrator maximum signal handling capability on SNR Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.

CI − φ φ Cs z 1 1 2 () =× Hz − ideal CI 1− z 1 - Cs a ⎛⎞ ⎜⎟a −1 Vo z + ⎜⎟Cs V ⎜⎟1++a i Cs Hz() =×⎝⎠CI Finit DC Gain CI ⎛⎞ ⎜⎟1+ a − 1− z 1 ⎜⎟Cs ⎜⎟1++a ⎝⎠CI

2nd Order ΣΔ Effect of Integrator Finite DC Gain

log H ()s Max signal level Ideal Integ. (a=infinite)

a ω ω 0 P1 = 0 a

Integrator magnitude response f0 /a

• Low integrator DC gain Æ Increase in total in-band noise • Can be shown: If a > M (oversampling ratio) Æ Insignificant degradation in SNR • Normally DC gain designed to be >> M in order to suppress nonlinearities

M / a

• Example: a =2M Æ 0.4dB degradation in SNR Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.

2nd Order ΣΔ Effect of Integrator Overall Integrator Gain Inaccuracy

• Gain of ½ in front of integrators determined by ratio of C1/C2

• Effect of inaccuracy in ratio of C1/C2 inspected by simulation

• Simulation show gain can vary by 20% w/o loss in performance ÆConfirms insensitivity of ΣΔ to component variations

• Note that for gain >0.65 system becomes unstable & SNR drops rapidly

2nd Order ΣΔ Effect of Integrator Nonlinearities

Ideal Integrator u(kT) Delay v(kT)

v(kT+= T) u(kT) + v(kT)

With non-linearity added: 23 v(KT+= T ) u(kT ) +αα⎡⎤⎡⎤ + ..... 23⎣⎦⎣⎦u( kT ) u( kT ) 23 ++v(kT )ββ⎡⎤⎡⎤ + + .... 23⎣v( kT )⎦⎣⎦ v( k T )

Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988

α ==β 22 0.01,0.02, 0.05, 0.1%

• Simulation for single-ended topology • Even order nonlinearities can be significantly attenuated by using differential circuit topologies Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.

2nd Order ΣΔ Effect of Integrator Nonlinearities

α ==β 33 0.05,0.2,1%

6dB Æ 1=Bit

• Simulation for single-ended topology • Odd order nonlinearities (3rd in this case) Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.