Quick Reference for Verilog HDL
Cover design: Sam Starfas Printed by: Technical Printing, Inc. Santa Clara Preface Copyright 1993, 94, 95 Automata Publishing Company This is a brief summary of the syntax and semantics of the Ver- ilog Hardware Description Language. The summary is not intended at being an exhaustive list of all the constructs and is UNIX is a registered trademark of AT&T not meant to be complete. This reference guide also lists con- Quick Verilog is a registered trademark of Cadence Design Systems, Inc. structs that can be synthesized. For any clarifications and to resolve ambiguities please refer to the Verilog Language Refer- c ence Manual, Copyright 1993 by Open Verilog Interna- Refer ence tional, Inc. and synthesis vendors Verilog HDL Reference Manuals. Copyright 1993, 94, 95 Automata Publishing Company for Published by Automata Publishing Company In addition to the OVI Language Reference Manual, for further examples and explanation of the Verilog HDL, the following text book is recommended: Digital Design and Synthesis With Verilog HDL Verilog HDL, Eli Sternheim, Rajvir Singh, Rajeev Madhavan c and Yatin Trivedi, Copyright 1993 by Automata Publishing In addition to this book, the following HDL books are available Company. from Automata Publishing Company:
1. Digital Design and Synthesis with Verilog HDL 2. Digital Design and Synthesis with VHDL Rajeev Madhavan
For additional copies of this book or for the source code to the Rajeev Madhavan examples, see the order form on the last page of the book.
AMBIT Design Systems, Inc. This book may be reproduced or transmitted for distribution provided the copyright notices are retained on all copies. For all other rights please contact the publishers.
Automata Publishing Company 1072 S. Saratoga-Sunnyvale Rd, Bldg A107 San Jose, CA 95129 Phone: 408-255-0705 Fax: 408-253-7916
Printed in the United States of America Released with permission from 10 9 8 7 6 5 4 3 2 Automata Publishing Company ISBN 0-9627488-4-6 San Jose, CA 95129 Copyright 1993, 1994, 1995 Automata Publishing Company. Quick Reference for Verilog HDL Quick Reference for Verilog HDL Quick Reference Use and Copyright for Verilog HDL Copyright (c) 1994, 1995 Rajeev Madhavan Copyright (c) 1994, 1995 Automata Publishing Company
1.0 Lexical Elements ...... 1 Permission to use, copy and distribute this book for any 1.1 Integer Literals ...... 1 purpose is hereby granted without fee, provided that 1.2 Data Types...... 1 2.0 Registers and Nets ...... 2 (i) the above copyright notices and this permission notice appear in all copies, and 3.0 Compiler Directives...... 3 4.0 System Tasks and Functions...... 4 (ii) the names of Rajeev Madhavan, Automata Publish- 5.0 Reserved Keywords...... 5 ing and AMBIT Design Systems may not be used in any advertising or publicity relating to this book without the 6.0 Structures and Hierarchy ...... 6 specific, prior written permission of Rajeev Madhavan, 6.1 Module Declarations ...... 6 Automata Publishing and AMBIT Design Systems. 6.2 UDP Declarations...... 7 7.0 Expressions and Operators ...... 10 THE BOOK IS PROVIDED "AS-IS" AND WITH- 7.1 Parallel Expressions ...... 13 OUT WARRANTY OF ANY KIND, EXPRESS, 7.2 Conditional Statements ...... 13 IMPLIED OR OTHERWISE, INCLUDING WITH- 7.3 Looping Statements...... 15 OUT LIMITATION, ANY WARRANTY OF MER- 8.0 Named Blocks, Disabling Blocks...... 16 CHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 9.0 Tasks and Functions...... 16 10.0 Continous Assignments ...... 18 IN NO EVENT SHALL RAJEEV MADHAVAN OR 11.0 Procedural Assignments ...... 18 AUTOMATA PUBLISHING OR AMBIT DESIGN 11.1 Blocking Assignment ...... 19 SYSTEMS BE LIABLE FOR ANY SPECIAL, INCI- 11.2 Non-Blocking Assignment...... 19 DENTAL, INDIRECT OR CONSEQUENTIAL DAM- AGES OF ANY KIND, OR ANY DAMAGES 12.0 Gate Types, MOS and Bidirectional Switches ...... 19 WHATSOEVER RESULTING FROM LOSS OF USE, 12.1 Gate Delays ...... 21 PROFITS, WHETHER OR NOT ADVISED OF THE 13.0 Specify Blocks...... 22 POSSIBILITY OF DAMAGE, AND ON ANY THE- 14.0 Verilog Synthesis Constructs...... 23 ORY OF LIABILITY, ARISING OUT OF OR IN CON- 14.1 Fully Supported Constructs...... 23 NECTION WITH THE USE OF THIS BOOK. 14.2 Partially Supported Constructs...... 24 14.3 Ignored Constructs ...... 25 14.4 Unsupported Constructs ...... 25 15.0 Index ...... 27
All rights reserved. This document is intended as a quick reference guide to the Verilog HDL. Verilog R is a reg- istered trademark of Cadence Design Systems, Inc. Quick Reference for Verilog HDL Quick Reference for Verilog HDL Quick Reference for Verilog HDL 1.0 Lexical Elements Time, registers and variable usage wire resolves to x. A trireg net behaves like a wire except that when all the drivers of the net are in high impedance (z) state, then the The language is case sensitive and all the keywords are lower case. time newtime ; net retains its last driven value. trireg ’s are used to model capaci- White space, namely, spaces, tabs and new-lines are ignored. Verilog /* time and integer are similar in functionality, tive networks. has two types of comments: time is an unsigned 64-bit used for time variables */ wire net1 ; 1. One line comments start with // and end at /* wire and tri have same functionality. tri is the end of the line reg [8*14:1] string ; used for multiple drive internal wire */ /* This defines a vector with range 2. Multi-line comments start with /* and end [msb_expr: lsb_expr] */ trireg (medium) capacitor ; with */ /* small, medium, weak are used for charge initial begin strength modeling */ Variable names have to start with an alphabetic character or underscore a = 0.5 ; // same as 5.0e-1. real variable followed by alphanumeric or underscore characters. The only excep- b = 1.2E12 ; tion to this are the system tasks and functions which start with a dollar c = 26.19_60_e-11 ; // _’s are sign. Escaped identifiers (identifier whose first characters is a backslash // used for readability A wand net or triand net operates as a wired and(wand), and a wor ( \ )) permit non alphanumeric characters in Verilog name. The string = “ string example ” ; net or trior net operates as a wired or (wor), tri0 and tri1 nets newtime =$time; escaped name includes all the characters following the backslash until model nets with resistive pulldown or pullup devices on them. When end the first white space character. a tri0 net is not driven, then its value is 0. When a tri1 net is not driven, then its value is 1. supply0 and supply1 model nets that are 1.1 Integer Literals 2.0 Registers and Nets connected to the ground or power supply. wand net2 ; // wired-and Binary literal 2’b1Z A register stores its value from one assignment to the next and is used to model data storage elements. wor net3 ; // wired-or Octal literal 2’O17 triand [4:0] net4 ; // multiple drive wand Decimal literal 9 or ’d9 trior net5 ; // multiple drive wor Hexadecimal literal 3’h189 reg [5:0] din ; tri0 net6 ; /* a 6-bit vector register: individual bits tri1 net7 ; din[5],.... din[0] */ supply0 gnd ; // logic 0 supply wire Integer literals can have underscores embedded in them for improved supply1 vcc ; // logic 1 supply wire readability. For example, Nets correspond to physical wires that connect instances. The default Memories are declared using register statements with the address range Decimal literal 24_000 range of a wire or reg is one bit. Nets do not store values and have to specified as in the following example, be continuously driven. If a net has multiple drivers (for example two reg [15:0] mem16X512 [0:511]; gate outputs are tied together), then the net value is resolved according 1.2 Data Types // 16-bit by 512 word memory to its type. // mem16X512[4] addresses word 4 The values z and Z stand for high impedance, and x and X stand for Net types // the order lsb:msb or msb:lsb is not important uninitialized variables or nets with conflicting drivers. String symbols wire tri The keyword scalared allows access to bits and parts of a bus and are enclosed within double quotes ( “string” ).and cannot span multi- wand triand vectored allows the vector to be modified only collectively. ple lines. Real number literals can be either in fixed notation or in sci- wor trior entific notation. tri0 tri1 supply0 supply1 wire vectored [5:0] neta; Real and Integer Variables example trireg /* a 6-bit vectored net */ tri1 vectored [5:0] netb; real a, b, c ; // a,b,c to be real /* a 6-bit vectored tri1 */ For a wire, if all the drivers have the same value then the wire resolves to this value. If all the drivers except one have a value of z integer j, k ; // integer variable then the wire resolves to the non z value. If two or more non z drivers 3.0 Compiler Directives integer i[1:32] ; // array of integer variables have different drive strength, then the wire resolves to the stronger driver. If two drivers of equal strength have different values, then the Verilog has compiler directives which affect the processing of the input
1 2 3 Quick Reference for Verilog HDL Quick Reference for Verilog HDL Quick Reference for Verilog HDL files. The directives start with a grave accent ( ‘ ) followed by some A list of standard system tasks and functions are listed below: 6.0 Structures and Hierarchy keyword. A directive takes effect from the point that it appears in the file until either the end of all the files, or until another directive that $display, $write - utility to display information Hierarchical HDL structures are achieved by defining modules and cancels the effect of the first one is encountered. For example, $fdisplay, $fwrite - write to file instantiating modules. Nested module definitions (i.e. one module defi- $strobe, $fstrobe - display/write simulation data nition within another) are not permitted. $monitor, $fmonitor - m ‘define OPCODEADD 00010 onitor, display/write information to file $time, $realtime - current simulation time $finish - exit the simulator 6.1 Module Declarations This defines a macro named OPCODEADD. When the text ‘OPCODEADD $stop - stop the simulator appears in the text, then it is replaced by 00010. Verilog macros are $setup - setup timing check The module name must be unique and no other module or primitive can simple text substitutions and do not permit arguments. $hold, $width- hold/width timing check have the same name. The port list is optional. A module without a port $setuphold - combines hold and setup list or with an empty port list is typically a top level module. A macro- $readmemb/$readmemh - read stimulus patterns into memory `ifdef SYNTH
‘resetall - resets all compiler directives to default values 5.0 Reserved Keywords // Net type declarations ‘define - text-macro substitution wire dl,dbl ; ‘timescale 1ns / 10ps - specifies time unit/precision The following lists the reserved words of Verilog hardware description ‘ifdef, ‘else, ‘endif - conditional compilation language, as of OVI LRM 2.0. // parameter value assignment ‘include - file inclusion paramter delay1 = 3, ‘signed, ‘unsigned - operator selection (OVI 2.0 only) and always assign attribute delay2 = delay1 + 1; // delay2 ‘celldefine, ‘endcelldefine - library modules begin buf bufif0 bufif1 // shows parameter dependance ‘default_nettype wire - default net types case cmos deassign default ‘unconnected_drive pull0|pull1, defparam disable else endattribute ‘nounconnected_drive - pullup or down unconnected ports end endcase endfunction endprimitive /* Hierarchy primitive instantiation, port ‘protect and ‘endprotect - encryption capability endmodule endtable endtask event connection in this section is by ‘protected and ‘endprotected - encryption capability for force forever fork ordered list */ ‘expand_vectornets, ‘noexpand_vectornets, function highz0 highz1 if initial inout input integer ‘autoexpand_vectornets - vector expansion options nand #delay1 n1(cf,dl,cbf), ‘remove_gatename, ‘noremove_gatenames join large medium module - remove gate names for more than one instance nand negedge nor not n2(cbf,clk,cf,rst); ‘remove_netname, ‘noremove_netnames notif0 notif1 nmos or nand #delay2 n3(dl,d,dbl,rst), - remove net names for more than one instance output parameter pmos posedge n4(dbl,dl,clk,cbf), primitive pulldown pullup pull0 n5(q,cbf,qb), pull1 rcmos reg release n6(qb,dbl,q,rst); repeat rnmos rpmos rtran 4.0 System Tasks and Functions rtranif0 rtranif1 scalared small /***** for debuging model initial begin specify specparam strong0 strong1 #500 force dff_lab.rst = 1 ; System taska are tool specific tasks and functions.. supply0 supply1 table task tran tranif0 tranif1 time #550 release dff_lab.rst; tri triand trior trireg // upward path referencing $display( “Example of using function”); tri0 tri1 vectored wait end ********/ /* display to screen */ wand weak0 weak1 while $monitor($time, “a=%b, clk = %b, wire wor endmodule add=%h”,a,clk,add); // monitor signals $setuphold( posedge clk, datain, setup, hold); // setup and hold checks
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Overriding parameters example Sequential Level Sensitive UDP’s example
Logic/state Representation/transition Abbrevation module dff_lab; // latch with async reset reg data,rst; primitive latch (q, clock, reset, data); don’t care (0, 1 or X) ? // Connecting ports by name.(map) input clock, reset, data ; output q; dff d1 (.qb(outb), .q(out), (xy) Transitions from logic x to logic y (xy). reg q; .clk(clk),.d(data),.rst(rst)); (01), (10), (0x), (1x), (x1), (x0) // overriding module parameters (?1) .. defparam initial q = 1’b1; // initialization dff_lab.dff.n1.delay1 = 5 , Transition from (01) R or r dff_lab.dff.n2.delay2 = 6 ; table // full-path referencing is used Transition from (10) F or f // over-riding by using #(8,9) delay1=8.. // clock reset data q, q+ (01), (0X), (X1): positive transition P or p ? 1 ? : ? : 1 ; dff d2 #(8,9) (outc, outd, clk, outb, rst); 0 0 0 : ? : 0 ; // clock generator (10), (1x), (x0): negative transition N or n 1 0 ? : ? : - ; always clk = #10 ~clk ; 0 0 1 : ? : 1 ; // stimulus ... contd Any transition * or (??) endtable Stimulus and Hierarchy example binary don’t care (0, 1) B or b endprimitive
initial begin: stimuli // named block stimulus clk = 1; data = 1; rst = 0; Combinational UDP’s example Sequential Edge Sensitive UDP’s example #20 rst = 1; #20 data = 0; // 3 to 1 mulitplexor with 2 select // edge triggered D Flip Flop with active high, #600 $finish; // async set and reset end primitive mux32 (Y, in1, in2, in3, s1, s2); primitive dff (QN, D, CP, R, S); input in1, in2, in3, s1, s2; output QN; initial // hierarchy: downward path referencing output Y; input D, CP, R, S; begin reg QN; #100 force dff.n2.rst = 0 ; table table #200 release dff.n2.rst; // D CP R S : Qtn : Qtn+1 end //in1 in2 in3 s1 s2 Y 1 (01) 0 0 : ? : 0; endmodule 0 ? ? 0 0 : 0 ; 1 (01) 0 x : ? : 0; 1 ? ? 0 0 : 1 ; ? ? 0 x : 0 : 0; ? 0 ? 1 0 : 0 ; 0 (01) 0 0 : ? : 1; // clocked data ? 1 ? 1 0 : 1 ; 6.2 User Defined Primitive (UDP) Declarations 0 (01) x 0 : ? : 1; // pessimism ? ? 0 ? 1 : 0 ; ? ? x 0 : 1 : 1; // pessimism ? ? 1 ? 1 : 1 ; The UDP’s are used to augment the gate primitives and are defined by 1 (x1) 0 0 : 0 : 0; 0 0 ? ? 0 : 0 ; truth tables. Instances of UDP’s can be used in the same way as gate 0 (x1) 0 0 : 1 : 1; 1 1 ? ? 0 : 1 ; primitives. There are 2 types of primitives: 1 (0x) 0 0 : 0 : 0; 0 ? 0 0 ? : 0 ; 1. Sequential UDP’s permit initialization of output 0 (0x) 0 0 : 1 : 1; 1 ? 1 0 ? : 1 ; terminals, which are declared to be of reg type and they store values. ? ? 1 ? : ? : 1; // asynch clear ? 0 0 1 ? : 0 ; ? ? 0 1 : ? : 0; // asynchronous set Level-sensitive entries take precedence over edge-sensitive ? 1 1 1 ? : 1 ; declarations. An input logic state Z is interpreted as an X. Similarly, only ? n 0 0 : ? : -; * ? ? ? : ? : -; 0, 1, X or - (unchanged) logic values are permitted on the output. endtable ? ? (?0) ? : ? : -; ? ? ? (?0): ? : -; 2. Combinational UDP’s do not store values and cannot be endprimitive initialized. ? ? ? ? : ? : x; endtable The following additional abbreviations are permitted in UDP declara- endprimitive tions.
7 8 9 Quick Reference for Verilog HDL Quick Reference for Verilog HDL Quick Reference for Verilog HDL 7.0 Expressions and Operators • All operators associate left to right, except for the Equality and Identity Operators ternary operator “?:” which associates from right to Arithmetic and logical operators are used to build expressions. Expres- left. sions perform operation on one or more operands, the operands being Operator Application vectored or scalared nets, registers, bit-selects, part selects, function Relational Operators = c = a ; // assign a to c calls or concatenations thereof. == c == a ; /* is c equal to a • Unary Expression Operator Application returns 1-bit true/false
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Shift Operators and other Operators if .. else ...conditions example casex statement example
always @(rst)// simple if -else casex (state) Operator Application if (rst) // treats both x and z as don’t care // procedural assignment // during comparison : 3’b01z, 3’b01x, 3b’011 << a << 1 ; // shift left a by q = 0; // ... match case 3’b01x // 1-bit else // remove the above continous assign 3’b01x: fsm = 0 ; deassign q; 3’b0xx: fsm = 1 ; >> a >> 1 ; // shift right a by 1 default: begin ?: c = sel ? a : b ; /* if sel always @(WRITE or READ or STATUS) // default matches all other occurances is true c = a, else c = b , begin fsm = 1 ; ?: ternary operator */ // if - else - if next_state = 3’b011 ; if (!WRITE) begin end {} {co, sum } = a + b + ci ; out = oldvalue ; endcase /* add a, b, ci assign the end overflow to co and the re- else if (!STATUS) begin sult to sum: operator is q = newstatus ; casez statement example called concatenation */ STATUS = hold ; end casez (state) {{}} b = {3{a}} /* replicate a 3 else if (!READ) begin // treats z as don’t care during comparison : times, equivalent to {a, a, out = newvalue ; // 3’b11z, 3’b1zz, ... match 3’b1??: fsm = 0 ; a} */ end 3’b1??: fsm = 0 ; // if MSB is 1, matches 3?b1?? end 3’b01?: fsm = 1 ; default: $display(“wrong state”) ; 7.1 Parallel Expressions endcase fork ... join are used for concurrent expression assignments. case, casex, casez: case statements are used for switching fork ... join example between multiple selections (if (case1) ... else if (case2) ... else ...). If there are multiple matches only the first is evalu- 7.3 Looping Statements initial ated. casez treats high impedance values as don’t care’s and casex forever, for, while and repeat loops example begin: block treats both unknown and high-impedance as don’t care’s. fork forever // This waits for the first event a case statement example // should be used with disable or timing control // or b to occur @(posedge clock) {co, sum} = a + b + ci ; @a disable block ; module d2X8 (select, out); // priority encode @b disable block ; input [0:2] select; for (i = 0 ; i < 7 ; i=i+1) output [0:7] out; memory[i] = 0 ; // initialize to 0 // reset at absolute time 20 reg [0:7] out; #20 reset = 1 ; always @(select) begin for (i = 0 ; i <= bit-width ; i=i+1) // data at absolute time 100 out = 0; // multiplier using shift left and add #100 data = 0 ; case (select) if (a[i]) out = out + ( b << (i-1) ) ; // data at absolute time 120 0: out[0] = 1; #120 data = 1 ; 1: out[1] = 1; repeat(bit-width) begin join 2: out[2] = 1; if (a[0]) out = b + out ; end 3: out[3] = 1; b = b << 1 ; // muliplier using 4: out[4] = 1; a = a << 1 ; // shift left and add 5: out[5] = 1; end 7.2 Conditional Statements 6: out[6] = 1; 7: out[7] = 1; while(delay) begin @(posedge clk) ; The most commonly used conditional statement is the if, if ... else ... endcase ldlang = oldldlang ; conditions. The statement occurs if the expressions controlling the if end delay = delay - 1 ; statement evaluates to true. endmodule end
13 14 15 Quick Reference for Verilog HDL Quick Reference for Verilog HDL Quick Reference for Verilog HDL 8.0 Named Blocks, Disabling Blocks task Example 10.0 Continous Assignments // task are declared within modules Named blocks are used to create hierarchy within modules and can be task recv ; Continous assignments imply that whenever any change on the RHS of used to group a collection of assignments or expressions. disable output valid ; the assignment occurs, it is evaluated and assigned to the LHS. These statement is used to disable or de-activate any named block, tasks or output [9:0] data ; assignments thus drive both vector and scalar values onto nets. Conti- modules. Named blocks, tasks can be accessed by full or reference begin nous assignments always implement combinational logic (possibly hierarchy paths (example dff_lab.stimuli).Named blocks can valid = inreg ; with delays). The driving strengths of a continous assignment can be have local variables. if (valid) begin specified by the user on the net types. ackin = 1 ; Named blocks and disable statement example data = qin ; • Continous assignment on declaration wait(inreg) ; initial forever @(posedge reset) ackin = 0 ; /* since only one net15 declaration exists in a disable MAIN ; // disable named block end given module only one such declarative continous // tasks, modules can also be disabled end assignment per signal is allowed */
always begin: MAIN // defining named blocks // task instantiation wire #10 (atrong1, pull0) net15 = enable ; if (!qfull) begin always begin: MAIN //named definition /* delay of 10 for continous assignment with #30 recv(new, newdata) ; // call task if (!qfull) begin strengths of logic 1 as strong1 and logic 0 as if (new) begin recv(new, newdata) ; // call task pull0 */ q[head] = newdata ; if (new) begin head = head + 1 ; // queue q[head] = newdata ; • Continous assignment on already declared nets end head = head + 1 ; end end assign #10 net15 = enable ; else end else assign (weak1, strong0) {s,c} = a + b ; disable recv ; disable recv ; end // MAIN end // MAIN function Example 11.0 Procedural Assignments 9.0 Tasks and Functions module foo2 (cs, in1, in2, ns); Assignments to register data types may occur within always, ini- input [1:0] cs; tial, task and functions . These expressions are controlled by Tasks and functions permit the grouping of common procedures and input in1, in2; triggers which cause the assignments to evaluate. The variables to then executing these procedures from different places. Arguments are output [1:0] ns; which the expressions are assigned must be made of bit-select or part- passed in the form of input/inout values and all calls to functions and function [1:0] generate_next_state; select or whole element of a reg, integer, real or time. These trig- input[1:0] current_state ; tasks share variables. The differences between tasks and functions are gers can be controlled by loops, if, else ... constructs. assign and input input1, input2 ; deassign are used for procedural assignments and to remove the con- Tasks Functions reg [1:0] next_state ; // input1 causes 0->1 transition tinous assignments. Permits time control Executes in one simulation // input2 causes 1->2 transition // 2->0 illegal and unknown states go to 0 module dff (q,qb,clk,d,rst); time begin output q, qb; Can have zero or more argu- Require at least one input case (current_state) input d, rst, clk; 2’h0 : next_state = input1 ? 2’h1 : 2’h0 ; reg q, qb, temp; ments 2’h1 : next_state = input2 ? 2’h2 : 2’h1 ; always Does not return value, Returns a single value, no 2’h2 : next_state = 2’h0 ; #1 qb = ~q ; // procedural assignment default: next_state = 2’h0 ; assigns value to outputs special output declarations endcase always @(rst) required generate_next_state = next_state; // procedural assignment with triggers end if (rst) assign q = temp; Can have output arguments, Does not permit outputs, endfunction // generate_next_state else deassign q; permits #, @, ->, #, @, ->, wait, task wait, task calls. calls assign ns = generate_next_state(cs, in1,in2) ; always @(posedge clk) endmodule temp = d; endmodule
16 17 18 Quick Reference for Verilog HDL Quick Reference for Verilog HDL Quick Reference for Verilog HDL force and release are also procedural assignments. However, they can force or release values on net data types and registers. The following strength definitions exists Gate Types Component 11.1 Blocking Assignment • 4 drive strengths (supply, strong, pull, Gates Allows and, nand, or, weak) strengths nor,xor, xnor module adder (a, b, ci, co, sum,clk) ; buf, not • 3 capacitor strengths (large, medium, small) input a, b, ci, clk ; output co, sum ; Three State Allows buif0,bufif1 • 1 high impedance state highz reg co, sum; Drivers strengths notif0,notif1 always @(posedge clk) // edge control The drive strengths for each of the output signals are // assign co, sum with previous value of a,b,ci MOS No strengths nmos,pmos,cmos, {co,sum} = #10 a + b + ci ; Switches rnmos,rpmos,rcmos endmodule • Strength of an output signal with logic value 1 Bi-directional No strengths, tran, tranif0, supply1, strong1, pull1, large1, weak1, switches non resistive tranif1 highz1 11.2 Non-Blocking Assignment • Strength of an output signal with logic value 0 rtran,rtranif0, No strengths, supply0, strong0, pull0, large0, weak0, Allows scheduling of assignments without blocking the procedural resistive rtranif1 flow. Blocking assignments allow timing control which are delays, highz0 whereas, non-blocking assignments permit timing control which can be Allows pullup delays or event control. The non-blocking assignment is used to avoid strengths pulldown race conditions and can model RTL assignments. Logic 0 Logic 1 Strength Gates, switch types, and their instantiations /* assume a = 10, b= 20 c = 30 d = 40 at start of supply0 Su0 supply1 Su1 7 block */ cmos i1 (out, datain, ncontrol, pcontrol); strong0 St0 strong1 St1 6 nmos i2 (out, datain, ncontrol); always @(posedge clk) pmos i3 (out, datain, pcontrol); pull0 Pu0 pull1 Pu1 5 begin:block pullup (neta) (netb); a <= #10 b ; pulldown (netc); large La0 large La1 4 b <= #10 c ; nor i4 (out, in1, in2, ...); c <= #10 d ; and i5 (out, in1, in2, ...); weak0 We0 weak1 We1 3 end nand i6 (out, in1, in2, ...); buf i7 (out1, out2, in); medium Me0 medium Me1 2 /* at end of block + 10 time units, a = 20, b = 30, bufif1 i8 (out, in, control); small Sm0 small Sm1 1 c = 40 */ tranif1 i9 (inout1, inout2, control); highz0 HiZ0 highz1 HiZ0 0 12.0 Gate Types, MOS and Bidirectional Gate level instantiation example
Switches // Gate level instantiations 12.1 Gate Delays Gate declarations permit the user to instantiate different gate-types and nor (highz1, strong0) #(2:3:5) (out, in1, The delays allow the modeling of rise time, fall time and turn-off in2); assign drive-strengths to the logic values and also any delays delays for the gates. Each of these delay types may be in the min:typ:- // instantiates a nor gate with out // strength of highz1 (for 1) and max format. The order of the delays are #(trise, tfall, tturn- // strong0 for 0 #(2:3:5) is the off). For example,
19 20 21 Quick Reference for Verilog HDL Quick Reference for Verilog HDL Quick Reference for Verilog HDL Verilog Delay Model disable function, endfunction #(delay) min:typ:max delay Synthesis Constructs if, else, else if #(delay, delay) rise-time delay, fall-time delay, input, output, inout each delay can be with The following is a set of Verilog constructs that are supported by most wire, wand, wor, tri min:typ:max synthesis tools at the time of this writing. To prevent variations in sup- integer, reg macromodule, module #(delay, delay, delay) rise-time delay, fall-time delay ported synthesis constructs from tool to tool, this is the least common and turn-off delay, each min:t- denominator of supported constructs. Tool reference guides cover spe- parameter yp:max cific constructs. supply0, supply1 task, endtask For trireg , the decay of the capacitive network is modeled using the rise-time delay, fall-time delay and charge-decay. For example, 14.0 Verilog Synthesis Constructs Since it is very difficult for the synthesis tool to find hardware with trireg (large) #(0,1,9) capacitor exact delays, all absolute and relative time declarations are ignored by // charge strength is large 14.2 Partially Supported Constructs // decay with tr=0, tf=1, tdecay=9 the tools. Also, all signals are assumed to be of maximum strength (strength 7). Boolean operations on X and Z are not permitted. The constructs are classified as Construct Constraints 13.0 Specify Blocks • Fully supported constructs — Constructs that are *, /, % when both operands constants, A specify block is used to specify timing information for the module in supported as defined in the Verilog Language Reference or 2nd operand power of 2. which the specify block is used. Specparams are used to declare delay Manual constants, much like regular parameters inside a module, but unlike • Partially supported — Constructs supported with always only edge-triggered events. module parameters they cannot be overridden. Paths are used to declare restrictions on them time delays between inputs and outputs. for bounded by static variables: Timing Information using specify blocks • Ignored constructs — Constructs that are ignored by the only use “+” or “-” to index. synthesis tool posedge, negedge always @ . specify // similar to defparam, used for timing only with • Unsupported constructs — Constructs which if used, specparam delay1 = 25.0, delay2 = 24.0; may cause the synthesis tool to not accept the Verilog primitive, Combinational and edge-sen- input or may cause different results between synthesis endprimitive sitive user defined primitives // edge sensitive delays -- some simulators table,endtable // do not support this and simulation. are often supported. (posedge clock) => (out1 +: in1) = <= (delay1, delay2) ; limitations on usage with // conditional delays 14.1 Fully Supported Constructs blocking assignment. if (OPCODE == 3’h4) (in1, in2 *> out1)
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14.3 Ignored Constructs - NOTES - - NOTES -
14.4 Unsupported Constructs
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Symbols C O V Verilog HDL Publications Order Form Automata Publishing Company $display, $write 5 case 14 Operator precedence 10 vectored 3 1072 S. Saratoga Sunnyvale Rd., Bldg. A107, Ste 325, $fdisplay, $fwrite 5 casex 14 San Jose CA-95129. U.S.A $finish 5 casez 14 P W Phone: 408-255-0705 Fax: 408-253-7916 $getpattern 5 compiler directives 3 Partially Supported Synthesis wait 16 $history 5 continous assignments 18 Verilog Publications: Constructs 24 wand 3 $hold, $width 5 Publication 1.Digital Design and Synthesis with Verilog HDL procedural assignments 18 while 15 $monitor, $fmonitor 5 D Publication 2.Digital Design and Synthesis with Verilog HDL+ pulldown 3 wire 2 Source diskette + Quick Reference for Verilog HDL $readmemb, $readmemh 5 delays 21 pullup 3 wor 3 $save, $restart, $incsave 5 disable 16 Name: ______Title: ______$scale 5 R X Company: ______$scope, $showscopes 5 E Address: ______$setup, $setuphold 5 reg, register 2 x, X 1 ______$showvars 5 Equality Operators 12 Relational Operators 11 City: ______$sreadmemb/$sreadmemh 5 Escaped identifiers 1 repeat 15 Z State: ______Zip: ______$stop 5 Expressions 10 reserved words 5 Ph: ______Fax: ______$strobe, $fstrobe 5 z, Z 1 $time, $realtime 5 F S /* */ 1 Publication 1 2 // 1 for 15 scalared 3 Quantity ‘autoexpand_vectornets 4 forever 15 Sequential edge sensitive UDP 9 fork ... join 13 Sequential level sensitive UDP 9 ‘celldefine, ‘endcelldefine 4 Price per book (see below) ‘default_nettype 4 Fully Supported Synthesis Con- Shift, other Operators 13 ‘define 4 structs 23 specify block 22 Shipping (see below) ‘expand_vectornets 4 function 16 specparam 22 ‘noexpand_vectornets 4 String symbols 1 Salex Tax (CA residents only, G @current rate) ‘ifdef, ‘else, ‘endif 4 supply0 3 supply1 3 ‘include 4 Gate declaration 19 Total amount due ‘nounconnected_drive 4 switch types 20 gate-types 19 P.O Number if any: ______‘protect, ‘endprotect 4 Synthesis Constructs 23 Charge my Visa/MC/AmExp. # ______‘protected, ‘endprotected 4 I Synthesis Ignored Constructs 25 Expires on: ______‘remove_gatename 4 Synthesis Unsupported Con- ‘noremove_gatenames 4 if, if ... else 13 structs 25 Integer literals 1 Publication 1 2 ‘remove_netname 4 T Qty-Price/copy (US$) (US$) ‘noremove_netnames 4 Identity Operators 12 1-4 59.95 65.95 ‘resetall 4 L task 16 ‘signed, ‘unsigned 4 tri0 3 5-9 54.95 60.95 ‘timescale 4 Logical Operators 11 tri1 3 ‘unconnected_drive 4 triand 3 10-19 49.95 54.95 M trior 3 20- 44 44.95 49.95 A trireg 3 Memories 3 45 - 99 39.95 44.45 Arithmetic Operators 11 module 6 U 100 - 500 34.95 39.00 B N UDP 7 Unary Expression 10 Shipping/copy 3.00 3.00 Binary Expressions 10 Named blocks 16 blocking assignment 19 Unary, Bitwise and Reduction Nets 2 Operators 12 For large volume discounts contact Automata Publishing Company non-blocking assignments 19
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