Hybrid Cross Coupled Differential Pair and Colpitts Quadrature Digitally Controlled Oscillator Architecture

electronics

Article Hybrid Cross Coupled Differential Pair and Colpitts Quadrature Digitally Controlled Oscillator Architecture

Igor Butryn * , Krzysztof Siwiec and Witold Adam Pleskacz

Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warsaw, Poland; [email protected] (K.S.); [email protected] (W.A.P.) * Correspondence: [email protected]

Abstract: Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power to be reduced. The DCO has been implemented in 110 nm CMOS technology. It generates output signal in frequency range from 1.52 GHz to 1.6 GHz and consumes 1.1 mW from 1.5 V supply voltage. The measured phase noise equals −116 dBc/Hz at 1 MHz offset from 1.575 GHz output signal.

Keywords: PLL; ADPLL; VCO; DCO; GNSS; current reused

Citation: Butryn, I.; Siwiec, K.; Pleskacz, W.A. Hybrid Cross Coupled 1. Introduction Differential Pair and Colpitts The digitally controlled oscillator is an important part of the All Digital Phase Locked Quadrature Digitally Controlled Loop (ADPLL) employed as a Local Oscillator (LO) in integrated transceivers. The DCO Oscillator Architecture. Electronics is responsible for the generation of the radio frequency (RF) signal that is served to the 2021, 10, 1132. https://doi.org/ mixer input in order to convert frequency. The most crucial parameters of the DCO are 10.3390/electronics10101132 the frequency sweep range and phase noise of the generated signal, as well as the power consumption and occupied area. Academic Editor: Egidio Ragonese ADPLL is a type of Phase Locked Loop (PLL) where some operations are performed in the digital domain instead of in the analog one [1]. One of the strongest advantages Received: 14 April 2021 of ADPLL is the implementation of the loop filter in a digital manner making capacitors Accepted: 7 May 2021 Published: 11 May 2021 obsolete. Consequently, an ADPLL occupies less area than an analog PLL. Additionally, a digital loop filter improves the flexibility of loop bandwidth control. Moreover, ADPLL is

Publisher’s Note: MDPI stays neutral easier to implement in a highly scaled CMOS technology [1]. with regard to jurisdictional claims in Development of low power and highly integrated transceivers is one of the goals published maps and institutional afﬁl- in modern wireless communication systems. Widespread use of mobile devices requires iations. signiﬁcant minimization of power consumption of the developed circuits. Extensive research has been carried out in order to minimize the dissipated power in wireless transceivers [2–4]. The oscillator is responsible for a big part of transceiver dissipated power. Therefore, minimization of the power consumed by the oscillator is one of the most important issues. Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. There are two types of oscillators that are widely implemented in integrated circuits: ring This article is an open access article oscillators and LC tank oscillators. Ring oscillators occupy less area in comparison with LC distributed under the terms and tank oscillators, because inductance in integrated circuits has large dimensions. However, conditions of the Creative Commons LC tank oscillators have better phase noise performance [5]. Since phase noise is an impor- Attribution (CC BY) license (https:// tant parameter in the GPS/Galileo application, the LC oscillator has been implemented in creativecommons.org/licenses/by/ RF frequency synthesizer in GPS/Galileo receiver [6]. There are several ways to reduce the 4.0/). consumed power in an oscillator. In reference [7] a study of a current reuse generator was

Electronics 2021, 10, 1132. https://doi.org/10.3390/electronics10101132 https://www.mdpi.com/journal/electronics Electronics 2021, 10, x FOR PEER REVIEW 2 of 15

Electronics 2021, 10, 1132 2 of 14 several ways to reduce the consumed power in an oscillator. In reference [7] a study of a current reuse generator was presented, a quadrature oscillator stacked with a divide-by-2 quadrature frequency divider circuit was described in [8], while [9] presents a gm en- presented,hanced oscillator. a quadrature The quadrature oscillator stacked DCO with(QDC aO) divide-by-2 architecture quadrature presented frequency in this dividerpaper circuitcombines was two described oscillator in architec [8], whiletures, [9] presentsi.e., the Colpitts a gm enhanced architecture oscillator. and the The cross quadrature coupled DCOpair architecture. (QDCO) architecture presented in this paper combines two oscillator architectures, i.e., theKnowing Colpitts the architecture importance and of theenergy cross saving coupled in wireless pair architecture. integrated systems the main goal Knowingof this work the is importance to develop of a energynew QDCO saving architecture in wireless that integrated meets systemsthe Global the Posi- main goaltioning of thisSystem work (GPS)/Galileo is to develop specification a new QDCO [3] architecture and consumes that meets less power the Global thanPositioning other os- Systemcillators (GPS)/Galileopresented in the speciﬁcation literature. The [3] andGPS/Galileo consumes requirements less power thanfor a otherfrequency oscillators syn- presentedthesizer are in described the literature. in Table The 1. GPS/GalileoThe GPS system requirements is different forfrom a other frequency communication synthesizer aresystems described because in Tableit has1 only. The one GPS receive system channel is different and no from adjacent other channels communication [3]. systems because it has only one receive channel and no adjacent channels [3]. Table 1. GPS/Galileo specification for frequency synthesizer. Table 1. GPS/Galileo speciﬁcation for frequency synthesizer. Output frequency 1.5754 GHz In-BandOutput Phase frequency noise <−80 dBc/Hz 1.5754 GHz Phase noise at 1In-Band MHz offset Phase from noise carrier <−80 dBc/Hz <−110 dBc/Hz Phase noise at 1frequency MHz offset from carrier frequency <−110 dBc/Hz Output signal type Differential and Quadrature Output signal type Differential and Quadrature

Section 2 describes the architecture of the developed hybrid oscillator. Section 3 showsSection simulation2 describes results the of architecture the circuit ofand the its developed comparison hybrid to other oscillator. architecture. Section3 showsMeas- simulationurement results results are of presented the circuit in andSectio itsn comparison4. Section 5 concludes to other architecture. the paper. Measurement results are presented in Section4. Section5 concludes the paper. 2. Novel Hybrid DCO Architecture 2. Novel Hybrid DCO Architecture The DCO is an important part of the ADPLL. It determines the frequency range of the outputThe DCO signal is an and important the phase part noise ofthe spectr ADPLL.al density It determines for frequencies the frequency above the range ADPLL of the outputbandwidth. signal Additionally, and the phase it noiseis the spectralmost po densitywer consuming for frequencies part of abovethe frequency the ADPLL synthe- band- width.sizer. The Additionally, new hybrid it isarchitecture the most power was design consuminged in partsuch ofa theway frequency that it combines synthesizer. the ad- The newvantages hybrid of architecturetwo popular was LC oscillators, designed in the such cross a way coupled that it pair combines and Colpitts the advantages ones. Figure of two 1 popularshows aLC model oscillators, of the thedesigned cross coupled hybrid pairoscillator and Colpitts. It consists ones. of Figure a Colpitts1 shows oscillator a model in of thegate-source designed feedback hybrid oscillator.gm-boosted It consistsarchitecture of a Colpitts[10], connected oscillator in parallel in gate-source to a cross feedback cou- gm-boostedpled pair oscillator architecture and a divide-by-2 [10], connected quadratu in parallelre frequency to a cross divider. coupled This pair solution oscillator aims andto aachieve divide-by-2 GPS/Galileo quadrature specification frequency with divider. lower Thisbias solutioncurrent in aims comparison to achieve to GPS/Galileoother oscil- speciﬁcationlator architectures. with lower bias current in comparison to other oscillator architectures.

FigureFigure 1. Model of the designed hybrid hybrid DCO. DCO.

2.1. Negative Conductance Implementation In the LC tank oscillator, oscillation starts when the negative conductance of the active device in the circuit is higher than the loss conductance of the LC tank [5]. There are a

few LC tank oscillator architectures described in the literature. The most common is the Electronics 2021, 10, x FOR PEER REVIEW 3 of 15

Electronics 2021, 10, 1132 2.1. Negative Conductance Implementation 3 of 14 In the LC tank oscillator, oscillation starts when the negative conductance of the active device in the circuit is higher than the loss conductance of the LC tank [5]. There are a few LC tank oscillator architectures described in the literature. The most common is the cross coupled differential pair oscillator, because of simple architecture and its differential cross coupled differential pair oscillator, because of simple architecture and its differen- nature [5,11]. Another popular oscillator design is the Colpitts architecture. The Colpitts os- tial nature [5,11]. Another popular oscillator design is the Colpitts architecture. The Col- cillator was originally developed as a single ended generator. However, differential signal pitts oscillator was originally developed as a single ended generator. However, differen- is required in many communication systems. Therefore, nowadays the Colpitts oscillator tial signal is required in many communication systems. Therefore, nowadays the Colpitts is widely implemented in differential architectures. The Colpitts oscillator provides good oscillator is widely implemented in differential architectures. The Colpitts oscillator phase noise performance and requires lower supply voltage in comparison to the cross provides good phase noise performance and requires lower supply voltage in compari- coupled pair circuit. However, it requires higher power consumption to guarantee the son to the cross coupled pair circuit. However, it requires higher power consumption to appropriate startup condition [7]. To relax the startup condition, the basic Colpitts archi- guarantee the appropriate startup condition [7]. To relax the startup condition, the basic tecture is modiﬁed. The Authors of [9] present a gm-boosted Colpitts architecture, where anColpitts additional architecture transistor is pairmodi wasfied. added The Authors to the typical of [9] differential present a Colpittsgm-boosted architecture. Colpitts ar- A gm-boostedchitecture, where Colpitts an oscillator additional was transistor used to developpair was the added novel to hybrid the typical architecture differential of DCO. Col- Apitts schematic architecture. of the A Colpitts gm-boosted oscillator Colpitts constituting oscillator a partwas ofused the to proposed develop hybrid the novel oscillator hybrid wasarchitecture presented of in DCO. Figure A2 .schematic Capacitors of C3 the and Colp C4 areitts addedoscillator to this constituting architecture a part to reduce of the proposed hybrid oscillator was presented in Figure 2. Capacitors C3 and C4 are added to the Miller effect of the Cgd of NM1 and NM2 transistors [8]. Figure3 shows a small signal modelthis architecture of the gm-boosted to reduce Colpitts the Miller oscillator. effect The of small-signalthe Cgd of NM1 negative and NM2 conductance transistors can be[8]. calculatedFigure 3 asshows [10]: a small signal model of the gm-boosted Colpitts oscillator. The small-signal negative conductance can be calculated as [10]: 2 2 1 gm1ω C1C2 + gm3ω C1(C1 + C2) Re(Yin) = − · 1 gω CC +gω C(C +C) (1) Re(Y ) = − ∙ 2 2 2 (1) 2 g + ω (C1 + C2) 2 m1g +ω (C +C)

wherewhere g m1gm1is is the the transconductance transconductance of of transistors transistors NM1 NM1 and and NM2, NM2, and and gm3 gism3 the is transcon-the trans- ductanceconductance of transistors of transistors NM3 NM3 and NM4.and NM4.

FigureFigure 2. 2.Schematic Schematic of of the the gm-boosted gm-boosted Colpitts Colpitts oscillator. oscillator.

Electronics 2021, 10, 1132 4 of 14 Electronics 2021, 10, x FOR PEER REVIEW 4 of 15

FigureFigure 3. 3. SmallSmall signal signal model model for for conductance conductance calculation. calculation.

ApartApart from from the the Collpits Collpits oscillator, oscillator, the the nega negativetive conductance conductance of of the the presented presented hybrid hybrid DCODCO architecture architecture is is implemented implemented also also by by the the cross cross coupled coupled pair pair generator. generator. This This oscillator oscillator isis connected connected in in parallel parallel to to the the LC LC tank tank as depicted inin FigureFigure1 1and and its its electrical electrical schematic schematic is ispresented presented in in Figure Figure4. 4. The The negative negative conductance conductance from from the the cross cross coupled coupled pair pair architecture architecture(gmCC (gmCC) is) connectedis connected in parallelin parallel to theto the oscillator oscillator tank. tank. Consequently, Consequently, gmCC gmCCis addedis added to theto thetransconductance transconductance of of the the active active part part of of the the ColpittsColpitts oscillatoroscillator and then the the small-signal small-signal negativenegative conductance conductance equals: equals: ( ) 1 gω2ω CC++gωω2 C( C++C) Re(Y) = −1 g∙m1 C1C2 gm3 C1 C1 C2 −g. (2) Re(Yin) = − ·2 g +ω(C +C ) − g . (2) 2 2 2 2 mCC gm1 + ω (C1 + C2) While gmCC equals [5]: While gmCC equals [5]: g +g g = , (3) gmNM5 +2gmPM1 gmCC = , (3) where gmNM5 is the transconductance of transistors2 NM5 and NM6 and gmNP1 is the transconductance of transistors PM1 and PM2. where gmNM5 is the transconductance of transistors NM5 and NM6 and gmNP1 is the transconductanceThis additional of conductance transistors PM1 relaxes and the PM2. startup condition of the Colpitts oscillator. The oscillationsThis additional are induced conductance with lower relaxes bias the current startup and condition consequently of the Colpittsthe power oscillator. dissi- patedThe oscillations by the oscillator are induced decreases with lower(this is bias discus currentsed andfurther consequently in Section the3). powerLC tank dissipated bias in presentedby the oscillator hybrid decreases oscillator (this is forced is discussed by voltage further on in PM1 Section and3 ).PM2 LC tankgates bias as indepicted presented in Figurehybrid 4. oscillator is forced by voltage on PM1 and PM2 gates as depicted in Figure4. FigureFigure 55 compares the conductance of of the active parts of the gm-boosted Colpitts oscillatoroscillator and and the the designed designed hybrid hybrid oscillat oscillator.or. The The conductance conductance was was calculated calculated using using EquationsEquations (1) (1) and and (2) (2) assuming thatthat thethe biasbiascurrent current was was 1 1 mA. mA. In In the the hybrid hybrid oscillator oscillator the thebias bias current current was was divided divided between between the Colpittsthe Colpitts oscillator oscillator part andpart the and cross the coupledcross coupled part in partdifferent in different proportions. proportions. The current The current biasing biasin theg Colpitts the Colpitts part ofpart the of hybrid the hybrid oscillator oscillator must mustbe high be high enough enough to bias to thebias divide-by-2 the divide-by- quadrature2 quadrature frequency frequency divider divider and maintainand maintain a low aspectral low spectral density density of the of phasethe phase noise noise of the of generatedthe generated signal signal which which is the is the advantage advantage of theof theColpitts Colpitts oscillator. oscillator. The The results results show show that that the conductancethe conductance in the in hybrid the hybrid oscillator oscillator is higher is higherthan that than in that the in gm-boosted the gm-boosted Colpitts Colpitts oscillator oscillator when biasedwhen biased by the by same the current.same current.

ElectronicsElectronicsElectronics 2021, 10 20212021, x ,FOR, 1010,, 1132 xPEER FOR REVIEWPEER REVIEW 5 of 1555 ofof 1415

FigureFigure 4. Schematic 4. Schematic of the of cross the coupledcross coupled pair oscillator. pair oscillator.

Figure 5. Comparison of the active-part conductance. FigureFigure 5. Comparison 5. Comparison of the of active-part the active-part conductance. conductance.

Electronics 2021, 10, x FOR PEER REVIEW 6 of 15

Electronics 2021, 10, 1132 6 of 14

2.2. Quadrature Signal Generation The GPS/Galileo receiver requires a quadrature signal [12]. There are a few ways to 2.2. Quadrature Signal Generation achieve a quadrature signal in an oscillator output. The first solution is coupling two identicalThe oscillators GPS/Galileo so that receiver the requiresphase differ a quadratureence between signal their [12 ].output There aresignals a few is ways90 de- to greesachieve [9]. aHowever, quadrature this signal solution in an significantl oscillator output.y increases The firstthe solutionoccupied is area coupling because two it iden- re- quirestical oscillators additional so inductance that the phase on chip. difference Another between solution, their described output signals in [13] is and 90 degrees[14], is an [9]. implementationHowever, this solution of poly significantlyphase filter to increases generate the quadrature occupied signal. area because This implementation it requires additional inductance on chip. Another solution, described in [13,14], is an implementation of suffers from variation of resistance and capacitance values in Process Corners and tem- poly phase filter to generate quadrature signal. This implementation suffers from variation perature. The third widely used solution is a divide-by-2 quadrature frequency divider of resistance and capacitance values in Process Corners and temperature. The third widely added to oscillator [15]. used solution is a divide-by-2 quadrature frequency divider added to oscillator [15]. A frequency divider occupies less area than an additional oscillator. Moreover, it can A frequency divider occupies less area than an additional oscillator. Moreover, it dissipate less power if it reuses the oscillator bias current. However, this solution has also can dissipate less power if it reuses the oscillator bias current. However, this solution some disadvantages, such as divider’s self-oscillation. In this work the divide-by-2 has also some disadvantages, such as divider’s self-oscillation. In this work the divide- quadrature frequency divider was implemented to generate the quadrature signal. by-2 quadrature frequency divider was implemented to generate the quadrature signal. Therefore, the presented hybrid oscillator was developed to generate output signal at Therefore, the presented hybrid oscillator was developed to generate output signal at frequency two times higher than required. A schematic of the frequency divider was frequency two times higher than required. A schematic of the frequency divider was presentedpresented in in Figure Figure 6.6. The The divide-by-2 quad quadraturerature frequency frequency divider divider was stacked with thethe Colpitts Colpitts oscillator. oscillator. This This was was possible possible because because the the Colpitts Colpitts architecture architecture requires requires lower lower supplysupply voltage. voltage. The The circuit circuit was was implemente implementedd in in Ultra Ultra Low Low Leakage Leakage (ULL) (ULL) CMOS CMOS 110 110 nm nm technology.technology. For For these these reasons reasons the the transistor transistor thre thresholdshold voltage voltage is is relatively relatively high high and and it it was was impossibleimpossible to to stack stack the the frequency frequency divider divider with with the the cross cross coupled coupled pair pair oscillator. oscillator. Since Since the the frequencyfrequency divider divider reusesreuses thethe oscillator oscillator bias bias current current the the dissipated dissipated power power is reduced, is reduced, which whichwas the was goal the of goal this of work. this work.

FigureFigure 6. 6. SchematicSchematic of of divide-by-2 divide-by-2 quadrature quadrature frequency frequency divider. divider.

2.3.2.3. Capacitor Capacitor Bank Bank TheThe frequency frequency of of the the oscillator’s oscillator’s output output si signalgnal depends depends on on the the input input control control signal signal thatthat consists consists of of a aseries series of of bits bits in in the the case case of of a aDCO. DCO. Therefore, Therefore, appropriate appropriate capacitor capacitor bank bank hadhad to to be be designed designed to to change change the the frequency frequency with with the the required required precision. precision. Figure Figure 77 presentspresents aa schematic schematic of of the the capacitor capacitor bank bank controlling controlling the the frequency frequency of of the the designed designed oscillator. oscillator. The The capacitorcapacitor bank bank is is di dividedvided into into 3 3 parts: parts: • Coarse tuning capacitors. • Fine tuning capacitors.

Electronics 2021, 10, x FOR PEER REVIEW 7 of 15

• Coarse tuning capacitors. • Fine tuning capacitors. • Delta sigma capacitors. The fine-tuning capacitor bank is controlled by a thermometer code signal and consists of 64 switched capacitor branches. The thermometer code is used here to limit the impact of local process variations between the individual capacitor branches. The fine-tuning bank determines the required frequency (1.5754 GHz) in spite of temperature variations. To obtain the required accuracy of the generated frequency it was necessary to develop a relatively small switched capacitance (simulations indicate a value of 200 aF to fulfill the GPS/Galileo requirements). There are many works done to study capacitance implementation in LC tank. The comparison of capacitor types in terms of their application in RF circuits was presented in [16]. Whereas in [17] authors present the analysis of the substrate capacity in the designed oscillator and its influence on the LC tank capacity. Unfortunately, the smallest capacitor available in the 110 nm Process Design Kit (PDK) is 51 fF. For this reason, in order to obtain capacitance change equal to 200 aF, it was necessary to design full custom switch capacitor, which was shown in Figure 8. The parasitic capacitance between metallization layers is used as a unit capacitor in the capacitor bank. The capacitance is changed from 840 aF to 1050 aF, which leads to frequency change of around 120 kHz. Simulation results of a single capacitor branch are presented in Figure 9. The bank of delta sigma capacitors consists of 4 capacitor branches that are controlled by delta sigma modulator and enable further improvement of the frequency resolution. The bank of the coarse tuning capacitors is used to compensate global process variations and voltage variations. In this work the maximum supply voltage change was assumed to be ±10% of the typical value (150 mV). This capacitor bank is controlled by an 8-bit binary signal. Changing a single bit changes the capacitance by 6.7 fF, which corresponds to one half of the fine-tuning bank range. The presented capacitor bank makes it possible to generate the output signal with the required frequency in spite of process, voltage and temperature (PVT) variations. GPS/Galileo application does not require oscillator with wide tuning range, therefore presented capacitor bank was design in such a Electronics 2021, 10, 1132 way to generate required frequency signal with minimum number of switch capacitors7 of 14 branches. Limited tuning range of DCO makes possible to use inductor with higher inductance value and higher quality factor, which resulting in easier startup condition for oscillator and better phase noise performance. Quality factor of inductor used in pre- •sentedDelta circuit sigma equals capacitors. approximately 10 in typical case.

FigureFigure 7.7. SchematicSchematic ofof thethe capacitorcapacitor bankbank inin thethe developeddevelopedoscillator. oscillator.

The fine-tuning capacitor bank is controlled by a thermometer code signal and consists of 64 switched capacitor branches. The thermometer code is used here to limit the impact of local process variations between the individual capacitor branches. The fine-tuning bank determines the required frequency (1.5754 GHz) in spite of temperature variations. To obtain the required accuracy of the generated frequency it was necessary to develop a relatively small switched capacitance (simulations indicate a value of 200 aF to fulfill the GPS/Galileo requirements). There are many works done to study capacitance implementation in LC tank. The comparison of capacitor types in terms of their application in RF circuits was presented in [16]. Whereas in [17] authors present the analysis of the substrate capacity in the designed oscillator and its influence on the LC tank capacity. Unfortunately, the smallest capacitor available in the 110 nm Process Design Kit (PDK) is 51 fF. For this reason, in order to obtain capacitance change equal to 200 aF, it was necessary to design full custom switch capacitor, which was shown in Figure8. The parasitic capacitance between metallization layers is used as a unit capacitor in the capacitor bank. The capacitance is changed from 840 aF to 1050 aF, which leads to frequency change of around 120 kHz. Simulation results of a single capacitor branch are presented in Figure9. The bank of delta sigma capacitors consists of 4 capacitor branches that are controlled by delta sigma modulator and enable further improvement of the frequency resolution. The bank of the coarse tuning capacitors is used to compensate global process variations and voltage variations. In this work the maximum supply voltage change was assumed to be ±10% of the typical value (150 mV). This capacitor bank is controlled by an 8-bit binary signal. Changing a single bit changes the capacitance by 6.7 fF, which corresponds to one half of the fine-tuning bank range. The presented capacitor bank makes it possible to generate the output signal with the required frequency in spite of process, voltage and temperature (PVT) variations. GPS/Galileo application does not require oscillator with wide tuning range, therefore presented capacitor bank was design in such a way to generate required frequency signal with minimum number of switch capacitors branches. Limited tuning range of DCO makes possible to use inductor with higher inductance value and higher quality factor, which resulting in easier startup condition for oscillator and better phase noise performance. Quality factor of inductor used in presented circuit equals approximately 10 in typical case. Electronics 2021, 10, x FOR PEER REVIEW 8 of 15

Electronics 2021, 10, 1132 8 of 14 Electronics 2021, 10, x FOR PEER REVIEW 8 of 15

Figure 8. The structure of the designed switch capacitor branch. FigureFigure 8.8. TheThe structurestructure ofof thethe designeddesigned switchswitch capacitorcapacitor branch.branch.

Figure 9. Simulation of the single capacitor branch. Figure 9. Simulation of the single capacitor branch. 3. Simulation Results 3. FigureSimulation 9. Simulation Results of the single capacitor branch. Transient simulations and phase noise simulations were carried out to determine the parameters3. TransientSimulation of simulations the Results developed and hybrid phase DCO.noise simula The designedtions were hybrid carried oscillator out to was determine compared the to parameters of the developed hybrid DCO. The designed hybrid oscillator was compared a gm-boostedTransient Colpittssimulations oscillator and phase based noise on the simula architecturetions were described carried out in [ 8to] anddetermine designed the to a gm-boosted Colpitts oscillator based on the architecture described in [8] and parametersby the Authors of the of developed this paper speciﬁcallyhybrid DCO. for Th thee designed purposes hybrid of comparative oscillator analysis.was compared Both designed by the Authors of this paper specifically for the purposes of comparative tooscillators a gm-boosted were developed Colpitts withoscillator the divide-by-2 based on quadraturethe architecture frequency described divider in circuit [8] and in analysis. Both oscillators were developed with the divide-by-2 quadrature frequency designedstack. The by cross the coupledAuthors differentialof this paper pair spec oscillatorifically wasfor notthe comparedpurposes of with comparative the other divider circuit in stack. The cross coupled differential pair oscillator was not compared analysis.two, because Both it requiresoscillators a higherwere developed supply voltage with to the stack divide-by-2 it with a divide-by-2 quadrature quadrature frequency with the other two, because it requires a higher supply voltage to stack it with a dividerfrequency circuit divider in stack. circuit. The Both cross oscillators coupled were differential simulated pair with oscillator 50 fF load was on not each compared output. divide-by-2 quadrature frequency divider circuit. Both oscillators were simulated with withThis loadthe isother introduced two, because by DCO it buffer,requires which a higher provides supply appropriate voltage signalto stack amplitude it with to a 50 fF load on each output. This load is introduced by DCO buffer, which provides divide-by-2the mixer input quadrature and drive frequency frequency divider divider circ inuit. feedback Both oscillators loop of ADPLL. were Thesimulated developed with appropriatehybrid oscillator signal amplitude achieves reliable to the mixer startup input conditions and drive at biasing frequency current divider of 0.7 in mA,feedback while 50 fF load on each output. This load is introduced by DCO buffer, which provides loopthe of gm-boosted ADPLL. The Colpitts developed oscillator hybrid needs oscillator 1.4 mA. achieves Figure 10reliable presents startup the startupconditions time at of appropriate signal amplitude to the mixer input and drive frequency divider in feedback biasingeach oscillator.current of The 0.7 hybridmA, while oscillator the gm-boosted has shorter Colpitts startup timeoscillator and dissipates needs 1.4 two mA. times Figure less loop of ADPLL. The developed hybrid oscillator achieves reliable startup conditions at 10power presents at thethe samestartup time. time Figure of each 11 oscillatoshows ther. The results hybrid of phase oscillator noise has simulation shorter startup for both biasing current of 0.7 mA, while the gm-boosted Colpitts oscillator needs 1.4 mA. Figure circuits. Phase noise at 1 MHz from carrier frequency equals −120 dBc/Hz in each circuit. 10 presents the startup time of each oscillator. The hybrid oscillator has shorter startup

Electronics 2021, 10, x FOR PEER REVIEW 9 of 15

time and dissipates two times less power at the same time. Figure 11 shows the results of phase noise simulation for both circuits. Phase noise at 1 MHz from carrier frequency equals −120 dBc/Hz in each circuit. The new hybrid architecture has a higher 1/f phase noise spectral density than gm-boosted Colpitts architecture. However, it is not a disadvantage due to the high-pass characteristic of transmitting a DCO phase noise to the ADPLL output. A summary of the comparison between the gm-boosted Colpitts oscillator and hybrid oscillator is presented in Table 2.

Table 2. Comparison between gm-boosted Colpitts and hybrid oscillators. Electronics 2021, 10, 1132 9 of 14 Gm-Boosted Oscillator Architecture Hybrid Oscillator Colpitts Oscillator Minimum bias current (mA) 1.4 0.7 The new hybrid architecture has a higher 1/f phase noise spectral density than gm-boosted Phase noise at 1 MHz (dBc/Hz) −120 −120 Colpitts architecture. However, it is not a disadvantage due to the high-pass characteristic Startup time (ns) 150 25 of transmitting a DCO phase noise to the ADPLL output. A summary of the comparison between the gm-boosted Colpitts oscillator and hybrid oscillator is presented in Table2.

Electronics 2021, 10, x FOR PEER REVIEW 10 of 15

FigureFigure 10. 10.SimulatedSimulated startup startup time time of hybrid of hybrid oscillator oscillator and and Colpitts Colpitts oscillator. oscillator.

FigureFigure 11. Simulated 11. Simulated phase phase noise noise spectral spectral density density for hybridfor hybrid oscillator oscillator and and Colpitts Colpitts oscillator. oscillator.

Electronics 2021, 10, 1132 10 of 14

Table 2. Comparison between gm-boosted Colpitts and hybrid oscillators.

Gm-Boosted Oscillator Architecture Hybrid Oscillator Colpitts Oscillator Minimum bias current (mA) 1.4 0.7 Phase noise at 1 MHz (dBc/Hz) −120 −120 Startup time (ns) 150 25

4. Measurement Results The developed hybrid oscillator was manufactured in Ultra Low Leakage 110 nm CMOS technology. Figure 12 presents a microphotograph of the fabricated circuit. Figures 13 and 14 compare post-layout simulations and measurement results of the phase noise performance and frequency sweep range, respectively. Phase noise performance and frequency sweep range were measured by using Signal Source Analyzer (SSA) with 50 Ohm input load. In order to carry out measurements, output buffer based on common source amplifier architecture was designed to drive SSA input load. Figure 13 shows differences between the measured and simulated phase noise performance. Presented phase noise performance results were measured and simulated for 1.574 GHz output frequency signal. For frequencies above 300 kHz from carrier signal, the measured phase noise spectral density is 2 dBc/Hz higher than simulated. This inaccuracy may result from process variations. The difference in phase noise performance for signals with carrier frequency offset less than 300 kHz is more significant, which is most likely due to imperfections in 1/f noise modeling in the PDK. Problems with 1/f noise modeling were observed also in other circuits on chip. Despite the difference between simulations and measurements results concerning phase noise spectral density at frequencies close to Electronics 2021, 10, x FOR PEER REVIEW 11 of 15 carrier, the designed oscillator fulfills the GPS/Galileo specification, because this low-band noise will be filtered by the ADPLL.

FigureFigure 12. 12.Microphotograph Microphotograph of of the the fabricated fabricated hybrid hybrid oscillator. oscillator.

Figure 13 shows differences between the measured and simulated phase noise performance. Presented phase noise performance results were measured and simulated for 1.574 GHz output frequency signal. For frequencies above 300 kHz from carrier signal, the measured phase noise spectral density is 2 dBc/Hz higher than simulated. This inaccuracy may result from process variations. The difference in phase noise performance for signals with carrier frequency offset less than 300 kHz is more significant, which is most likely due to imperfections in 1/f noise modeling in the PDK. Problems with 1/f noise modeling were observed also in other circuits on chip. Despite the difference between simulations and measurements results concerning phase noise spectral density at frequencies close to carrier, the designed oscillator fulfills the GPS/Galileo specification, because this low-band noise will be filtered by the ADPLL. The measured frequency sweep range of the manufactured oscillator is close to the simulations results. Measurement results prove that the developed switched capacitors branches work as intended. The difference between the measured and simulated output signal frequency could be caused by process variations, however the oscillator was designed to fulfill the GPS/Galileo specification in spite of process variations. Measurement results confirm that the DCO parameters are situated between extreme results of process corner simulations.

Electronics 2021, 10, x FOR PEER REVIEW 12 of 15

Electronics 2021, 10, 1132 11 of 14

Figure 13. Comparison between the measured and simulated phase noise of the presented DCO. FigureFigure 13. Comparison13. Comparison between between the measuredthe measured and and simulated simulated phase phase noise noise of the of presentedthe presented DCO. DCO.

Figure 14. Comparison between the measured and simulated frequency sweep range of the devel- Figure 14. Comparison between the measured and simulated frequency sweep range of the developed hybrid DCO. oped hybrid DCO. Figure 14. Comparison between the measured and simulated frequency sweep range of the developed hybrid DCO. The measured5. Conclusions frequency sweep range of the manufactured oscillator is close to the simulations5. Conclusions results.A Measurementnovel hybrid resultsdigitally prove controlled that the oscillator developed combining switched the capacitors architectures of the branches workcross as intended. coupled Thepair difference and Colpitts between oscillat theors measured was designed. and simulated The outputpresented oscillator A novel hybrid digitally controlled oscillator combining the architectures of the signal frequency could be caused by process variations, however the oscillator was de- cross coupled pair and Colpitts oscillators was designed. The presented oscillator signed to fulﬁll the GPS/Galileo speciﬁcation in spite of process variations. Measurement

Electronics 2021, 10, 1132 12 of 14

results conﬁrm that the DCO parameters are situated between extreme results of process corner simulations.

5. Conclusions A novel hybrid digitally controlled oscillator combining the architectures of the cross coupled pair and Colpitts oscillators was designed. The presented oscillator achieves the aim of this work, which was to develop an oscillator for a GPS/Galileo receiver and reduce the oscillator’s power consumption below the values presented in the literature. The novel hybrid architecture combines the advantages of the cross coupled pair and Colpitts architectures. The cross coupled transistor pair enables reliable startup to be achieved at a lower bias current in comparison to the Colpitts architecture. On the other hand, the Colpitts oscillator has a good phase noise performance and requires lower supply voltage, which makes it possible to add a divide-by-2 quadrature frequency divider stacked with the oscillator. Such a divider generates a quadrature signal without consuming additional current from the supply. The presented hybrid oscillator meets the GPS/Galileo speciﬁcation. It generates a quadrature signal at frequency of 1.52–1.60 GHz and dissipates 1.1 mW power. The spectral density of phase noise at 1 MHz from carrier frequency equals −116 dBc/Hz. Table3 compares the developed circuit to other circuits described in the literature. Even though the Figure of Merit (FOM) does not show the superiority of the presented DCO architecture over other circuits presented in the literature the hybrid system has the lowest power consumption and occupies the smallest area. Moreover, the presented oscillator was designed in aluminum CMOS 110 nm ULL technology. Aluminum metallization layers have higher resistance compared to copper connections, which causes a signiﬁcant degradation of the LC tank quality factor. Thus the proposed hybrid architecture obtains a comparable FOM using an aluminum technology with the added bonus of occupying a small area. This can be important, especially in commercial applications, as very often aluminum metal stack is used to reduce the fabrication cost. Small chip area is also desirable from the cost perspective.

Table 3. Comparison to other works.

This Work Ref. [7] Ref. [9] Ref. [15] Ref. [18] Ref. [19] Ref. [20] Center 1.575 2.445 2.035 1.52 1.575 1.57 5.96 frequency (GHz) Tuning 5.1 8.5 20.5 15.8 3.2 7.2 0.51 range (%) Phase noise at 1 MHz −116 −123 −127 −120 −112 −118.6 −98 (dBc/Hz) Power consumption 1.1 1.4 8.6 3.05 3.68 1.32 0.69 (mW) Supply 1.5 1.1 2 1.8 1.6 0.6 0.5 voltage (V) Type of measured measured measured measured measured measured measured results Differential Differential Differential Differential Differential Output and Differential and and and and Differential signal type Quadrature Quadrature Quadrature Quadrature Quadrature FoM −179.53 −189.0 −183.7 −179.17 −170.28 −184.4 −180.96 (dBc/Hz) Die area (mm2) 0.23 1.764 1.38 0.4 - 0.62 0.74 Electronics 2021, 10, 1132 13 of 14

The presented comparison shows that a hybrid of cross coupled pair and Colpitts digitally controlled oscillator reduces the required bias current. The presented novel architecture could facilitate the reduction of the power consumed in oscillators designed for other applications. Figure of Merit was calculated based on the following equation:

f P FoM = L(∆f) − 20 log osc + 10 log osc , (4) ∆f 1mW

where ∆f is offset frquency from carrier, L(∆f) is phase noise spectral density at ∆f, fosc is oscillator output signal frequency and Posc is oscillator disipated power.

Author Contributions: The work presented in this paper was a collaboration of all authors. RF and analog design, visualization, writing, I.B.; conceptualization, validation and RF design, K.S.; supervision, writing—review and editing, project administration, funding acquisition, W.A.P. All authors have read and agreed to the published version of the manuscript. Funding: This work was supported in part by the Polish National Centre for Research and Develop- ment under project No. POIR.04.01.04-00-0101/16. Data Availability Statement: The data presented in this study are available on request from the corresponding author. The data are not publicly available due to the ongoing project restrictions. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References 1. Staszewski, R.B. State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS. In Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 30 May–2 June 2010; pp. 1497–1510. 2. Steyaen, M.S.J.; De Mueer, B.; Leroux, P.; Bommans, M.; Menens, K. Low-voltage low power CMOS-RF transceiver design. IEEE Trans. Microw. Theory Tech. 2002, 41, 281–287. 3. Cheng, K.-W.; Natarajan, K.; Allstot, D.J. A Current Reuse Quadrature GPS Receiver in 0.13µm CMOS. IEEE J. Solid-State Circuits 2010, 45, 510–523. [CrossRef] 4. Liscidini, A.; Mazzanti, A.; Tonietto, R.; Vandi, L.; Andreani, P. Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell. IEEE J. Solid-State Circuits 2006, 41, 2832–2841. [CrossRef] 5. Ham, D.; Hajimiri, A. Concepts and methods in optimization of integrated LC VCOs. IEEE J. Solid-State Circuits 2001, 36, 896–909. [CrossRef] 6. Borejko, T.; Marcinek, K.; Siwiec, K.; Narczyk, P.; Borkowski, A.; Butryn, I.; Łuczyk, A.; Pietro´n,D.; Plasota, M.; Reszewicz, S.; et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069. [CrossRef] [PubMed] 7. Cheng, K.-W.; Chang, S.-K.; Huang, Y.-C. Low-Power and Low-Phase-Noise Gm-Enhanced Current-Reuse Differential Colpitts VCO. IEEE Trans. Circuits Syst. II Express Briefs 2019, 66, 733–737. [CrossRef] 8. Ji, X.; Wu, J.; Shi, L. Current reused Colpitts VCO and frequency divider for quadrature generation. In Proceedings of the 2011 International Conference on Electric Information and Control Engineering, Wuhan, China, 15–17 April 2011. 9. Li, X.; Shekhar, S.; Allstot, D.J. Gm-boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18-µm CMOS. IEEE J. Solid-State Circuits 2005, 40, 2609–2619. 10. Hong, J.-P.; Lee, S.-G. Low Phase Noise Gm-Boosted Differential Gate-to-Source Feedback Colpitts CMOS VCO. IEEE J. Solid-State Circuits 2009, 40, 3079–3091. [CrossRef] 11. Cross, M.; Young, D.J. CMOS cross-coupled VCO architecture comparison at 2 GHz and 16 GHz. In Proceedings of the 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, 20–23 October 2008. 12. Siwiec, K.; Borejko, T.; Pleskacz, W.A. PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. In Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cottbus, Germany, 13–15 April 2011; pp. 29–34. 13. Momeni, M.; Moezzi, M. A Low Loss and Area Efﬁcient RC Passive Poly Phase Filter for Monolithic GHz Vector-Sum Circuits. IEEE Trans. Circuits Syst. II Express Briefs 2019, 66, 1134–1138. [CrossRef] 14. Teo, T.H.; Yeoh, W.G. Low-Power Short-Range Radio CMOS Subharmonic RF Front-End Using CG-CS LNA. IEEE Trans-Actions Circuits Syst. II Express Briefs 2008, 55, 658–662. [CrossRef] 15. Park, K.G.; Jeong, C.Y.; Park, J.W.; Lee, J.W.; Jo, J.G.; Yoo, C. Current reusing VCO and divide-by-two frequency divider for quadrature LO generation. IEEE Microw. Wirel. Compon. Lett. 2008, 18, 413–415. [CrossRef] Electronics 2021, 10, 1132 14 of 14

16. Lim, Q.S.I.; Kordesch, A.V.; Keating, R.A. Performance comparison of MIM capacitors and metal ﬁnger capacitors for analog and RF applications. In Proceedings of the 2004 RF and Microwave Conference (IEEE Cat. No.04EX924), Selangor, Malaysia, 5–6 October 2004; pp. 85–89. [CrossRef] 17. Teo, T.H.; Xiong, Y.-Z.; Fu, J.S.; Tan, E.L. LC oscillator design at 10-GHz using substrate capacitance with scalable varactor parameters extraction technique. In Proceedings of the 2005 European Microwave Conference, Paris, France, 4–6 October 2005; p. 4. [CrossRef] 18. Gramegna, G.; Mattos, P.G.; Losi, M.; Das, S.; Franciotta, M.; Bellantone, N.G.; Vaiana, M.; Mandara, V.; Paparo, M. A 56-mW 23-mm/sup 2/ single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/ radio. IEEE J. Solid-State Circuits 2006, 41, 540–551. [CrossRef] 19. Ding, X.; Wu, J.; Chen, C. A Low-Power 0.6-V Quadrature VCO With a Coupling Current Reuse Technique. IEEE Trans. Circuits Syst. II Express Briefs 2019, 66, 202–206. [CrossRef] 20. Ikeda, S.; Lee, S.; Ito, H.; Ishihara, N.; Masu, K. A 0.5 V 5.96-GHz PLL With Amplitude-Regulated Current-Reuse VCO. IEEE Microw. Wirel. Compon. Lett. 2017, 27, 302–304. [CrossRef]