Homebrew RF Siganl Generator Colpitts FET Oscillator

HomeBrew RF Siganl Generator Colpitts FET Oscillator

THE OSCILLATOR

V1 is 9.0 Volts dc

Purpose and Function Create a signal which can be amplified for use in an RF frequency Generator.

Theory and Design  I have lost the reference for this circuit o But very similar to the Colpitts in the 2007 ARRL1  C1-C2 and L1 form the Resonator circuit  C3 provides coupling/ isolation to J1g  Positive feedback is provide by the C2 J1d connection  Many texts claim component selection is more black art than science using calculations 2  C1 –C2 were picked by available variable capacitors with typical ranges of 30- 110pf

 C3 was picked for best response  Scope must be on 10x to keep from overloading

Calculated Frequency  C1, C2, and L1 determine the frequency 1 o Ceq  1 1  1 CC 2 o C1,C2 represent a ganged variable capacitor =33 to110pf and c2=220 pF . When C1, C2 = 33pf  Ceqmin = 1/(1/33 +1/33)  Ceqmin = 16.5 pf . When C1, C2 = 68pf  Ceqmax = 1/(1/68+1/68)  Ceqmin = 34 pf

1  Resonate Frequency F 0  3 2 LC o L = 1 uH 1 o Fmax =  16.5pF*1.0uH2 o Fmax = 39.2 Mhz 1 o Fmin =  34pF*1.0uH2 o Fmin = 27.3 Mhz

 By similar means we calculate for their values of L1 o L1 = 10 uH . Fmax = 12.3 Mhz . Fmin = 8.63 Mhz o L1 = 100 uH . Fmax = 3.92 Mhz . Fmin = 2.73 Mhz

Bias  The FET forms a classic Source follower  Because there is little or no current into the Gate o There is no voltage drop across R1 o Using Kirkoffs voltage law we get Vgs = - Vs = -Id Rs . (Rs = R2)Vgs Vgs  IdssId 1(  4 Vp

. Idss and Vp are dependent on the FET and can be found in the data sheets  Vp is between 8.0 and 0 Volts 5 I will use the average of 4.0 volts  Idss is between 2.0 and 20.0 mA 5, I will use the average of 11.0 ma  Vgs o Vgs = needs to be less Vp to keep Id less than Idss o Vgs and therefore Vs needs to be high enough to allow for sufficient swing of the output signal . I choose Vgs = -1.5 Volts for max swing

5.1  Now we can compute maId 1(11  0.4 o Id = 8.69 ma  Rs = Vs/Id = 1.5V/7.78 = 192 ohms  Vg = 0 by design  Vd = 9V power supply  NOTE: The R required to achieve Vgs = -1.5V in simulation was 3.3K ohms o So these calculations are off by an order of magnitude o The model FET is not an exact match o Looking at the Data sheet 5 we see a large variance for Vgs and Idss. This and Reference 6 show that it is very difficult to calculate the biases for and FET with any degree of certainty

Amplitude  I was not able to calculate the amplitude of the output.

Harmonic Noise  I was not able to calculate the Harmonic noise of the output.

Simulation

 Simulations were over optimistic about magnitude and the ability to oscillate than a real circuit until the C1-C3 were made non- ideal by adding 10ohm series resistance, however this is then to pessimistic!

Frequency  C1, C2 = 33pf , L1 = 1uh => 36.8 Mhz

 Series1 550.000m  Series2 500.000m

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-50.000m 0.0 10.000M 20.000M 30.000M 40.000M 50.000M 60.000M 70.000M 80.000M 90.000M 100.000M

 C1, C2 = 33pf , L1 = 1uh => 36.8 Mhz  C1, C2 = 68pf , L1 = 1uh => 26.6 Mhz  C1, C2 = 33pf , L1 = 10uh => 11.6 Mhz  C1, C2 = 68pf , L1 = 10uh => 8.34 Mhz  C1, C2 = 33pf , L1 = 100uh => 3.75 Mhz  C1, C2 = 68pf , L1 = 100uh => 2.54 Mhz

Bias  Vd = 9.0  Vg = 0.0  Vs = 1.5

Amplitude  C1, C2, C1 = 33pf , L1 = 1uh => 2.0 Vp-p  C1, C2, C1 = 110pf , L1 = 1uh => 0.4 Vp-p  C1, C2, C1 = 33pf , L1 = 10uh => 11.0 Vp-p (Clipping)  C1, C2, C1 = 110pf , L1 = 10uh => 5.6 Vp-p  C1, C2, C1 = 33pf , L1 = 100uh => 11.0 Vp-p (Clipping)

 C1, C2, C1 = 110pf , L1 = 100uh => 11.0 Vp-p (Clipping)

Harmonic Noise  The values below are Vdb to the nearest peak in the frequency domain (harmonic distortion)  C1, C2, C1 = 33pf , L1 = 1uh => -24.5 db  C1, C2, C1 = 110pf , L1 = 1uh => -29.5 db  C1, C2, C1 = 33pf , L1 = 10uh => -25.8 db  C1, C2, C1 = 110pf , L1 = 10uh => -22.6 db  C1, C2, C1 = 33pf , L1 = 100uh => -28.0 db  C1, C2, C1 = 110pf , L1 = 100uh => -28.0 db

Real Circuit Frequency  C1, C2 = 33pf , L1 = 1uh => 27.8 Mhz  C1, C2 = 68pf , L1 = 1uh => 25.0 Mhz  C1, C2 = 33pf , L1 = 10uh => 10.9 Mhz  C1, C2 = 68pf , L1 = 10uh => 7.14 Mhz  C1, C2 = 33pf , L1 = 100uh => 3.50 Mhz  C1, C2 = 68pf , L1 = 100uh => 2.34 Mhz

Bias  I failed to measure these.

Amplitude  C1, C2, C1 = 33pf , L1 = 1uh => 3.0 Vp-p  C1, C2, C1 = 110pf , L1 = 1uh => 4.0 Vp-p  C1, C2, C1 = 33pf , L1 = 10uh => 8.0 Vp-p (Clipping)  C1, C2, C1 = 110pf , L1 = 10uh => 9.0 Vp-p  C1, C2, C1 = 33pf , L1 = 100uh => 9.0 Vp-p (Clipping)  C1, C2, C1 = 110pf , L1 = 100uh => 10.0 Vp-p (Clipping)

Harmonic Noise  The values below are Vdb to the nearest peak in the frequency domain (harmonic distortion)  C1, C2, C1 = 33pf , L1 = 1uh => -14 db  C1, C2, C1 = 110pf , L1 = 1uh => -14 db  C1, C2, C1 = 33pf , L1 = 10uh => -15 db  C1, C2, C1 = 110pf , L1 = 10uh => -20 db  C1, C2, C1 = 33pf , L1 = 100uh => -12 db  C1, C2, C1 = 110pf , L1 = 100uh => -30 db

 C1, C2 = 68pf L1 = 1uh o Top trace is Vosc o Bottom trace is FFT(Vosc)

 C1, C2 = 68pf L1 = 10uh o Top trace is Vosc o Bottom trace is FFT(Vosc)

 C1, C2 = 68pf L1 = 100uh o Top trace is Vosc o Bottom trace is FFT(Vosc)

 C1, C2 = 33pf L1 = 1uh o Top trace is Vosc o Bottom trace is FFT(Vosc)

 C1, C2 = 33pf L1 = 10uh o Top trace is Vosc o Bottom trace is FFT(Vosc)

 C1, C2 = 33pf L1 = 100uh o Top trace is Vosc o Bottom trace is FFT(Vosc)

Comparison  Comparison is at best reasonable o I attribute the decreased frequency in simulation to the capacitance of the other components o I attribute the decreased frequency in the real circuit to the capacitance of the set up (used a prototype board)

Real-Measured Simulation Calculated Frequency in Mhz C1, C2 = 33pf , L1 = 1uh 27.8 36.8 39.2 C1, C2 = 86pf , L1 = 1uh 25.0 26.6 27.3 C1, C2 = 33pf , L1 = 10uh 10.9 11.6 12.3 C1, C2 = 86pf , L1 = 10uh 7.14 8.34 8.63 C1, C2 = 33pf , L1 = 100uh 3.50 3.75 3.92 C1, C2 = 86pf , L1 = 100uh 2.34 2.54 2.73

Amplitude Vp-p C1, C2 = 33pf , L1 = 1uh 3.0 2.0 N/A C1, C2 = 86pf , L1 = 1uh 4.0 0.4 N/A C1, C2 = 33pf , L1 = 10uh 8.0 11.0 clipping N/A C1, C2 = 86pf , L1 = 10uh 9.0 8.5 N/A C1, C2 = 33pf , L1 = 100uh 9.0 11.0 clipping N/A C1, C2 = 86pf , L1 = 100uh 10.0 11.0 clipping N/A

Harmonic Noise db C1, C2 = 33pf , L1 = 1uh -14 -24.8 N/A C1, C2 = 86pf , L1 = 1uh -14 -29.5 N/A C1, C2 = 33pf , L1 = 10uh -15 -25.8 N/A C1, C2 = 86pf , L1 = 10uh -20 -22.6 N/A C1, C2 = 33pf , L1 = 100uh -12 -28 N/A C1, C2 = 86pf , L1 = 100uh -30 -28 N/A

Ve N/A 9.0 9.0 Vb N/A 0.0 0.0 Ve N/A 1.5 1.5

Conclusion This proved to my satisfaction that I wanted to use an FET in the Oscillator instead of a BJT because of the lower Harmonic Noise

When I discovered that the frame of the gang capacitor was had to be isolated from ground ans that it suffered frequency changes even when touching an insulated knob I dropped the Colpitts in favor of the Hartley Oscillator

References

1. UNKNOWN, The ARRL Handbook For Radio Communications, (ARRL 2007) p10.13, (Figure 10.12 A). 2. Harris, Frank, Crystal Sets to Sideband, (2006 Rev10), http://www.qsl.net/k3pd/chap10.pdf p3 online, accessed 2008. 3. Horowitz, Paul and Hill, Winfield, The Art Of Electronics Second Edition, (Cambridge University Press 1989) Section 1.22 Resonate Circuits and Active Filters p41. 4. Experimental Methods in RF Design Wes Hayward et al First Edition p 2.6 Fig 2.19 5. UNKNOWN, MPF102 N-Channel RF Amplifier, (FAIRCHILD 2004), http://www.fairchildsemi.com/ds/MP%2FMPF102.pdf, online, accessed 2008. 6. Horowitz, Paul and Hill, Winfield, The Art Of Electronics Second Edition, (Cambridge University Press 1989) Section 3.05 Manufacturing Spread of FET Characteristics, p122-127.

Before I dropped the Colpitts oscillator I did addition design on the other stages of a RF frequency Generator. Less comprehensive documentation on these experiments is recorded below.

THE BUFFER

Theory and Design  Connecting a 50 dummy load to the output of the capacitor drops the output to nothing  Of course the 50ohms greatly effects the 3.3K Rd resistor so we pick a 159pF coupling capacitor (159 pf = 50 ohms at 20 Mhz), but this still gives little or no output  So finally we try a common drain FET as a buffer, this should provide high input impedance and a gain just under 1

SIMULATION  Coupling o DC . Vout = .200mVp-p and Vosc has also dropped to just above this range o Coupling capacitor . 150 pF (50 ohms at 20 Mhz) 350mVp-p

. 15-1500pf no real difference  Output load o 50 Ohm with “matching” Cap at 159 pf . drops output to 90 mVp-p which is small but better than un- buffered circuit  J2d input is still 300mVp-p so this suggests impedance of cap is to large  Increasing C5 by 2 orders of magnitude has no effect o 50 Ohm with “matching” Cap at 159 pf . drops output to 90 mVp-p which is near ½ of J2d so this is a good match

THE AMP Theory and Design  Would like a higher amplitude and ability to adjust the amplitude so need to and amplifier section  Choose common emitter for high power gain  Start with previous design

 Min output is at vcc*re/re+rc  Gain = rc/re

 Imax = vb-.7/re o Assume 1ma and vcc/2 => re = 4.5K  Assume gain = 3 => Rc = 13.5K  The calculate Rbias to get vcc + .7  However max Ic = vcc/(re + re)   Gain ~ rc/re  Icmax = vcc/rc+re

SIMULATION  Start with previous design Add 50 ohm load dies so add emitter follower, can we loose fet drain follower

What I learned from this design  The JFET oscillator is less noisy than an equivalent BJT oscillator. As shown below the energy of the 1st harmonic is – 17dbV for the BJT and –12dbV for the JFET design. o BJT

o FET

C1, C2 = 68pf L1 = 1uh

 At higher frequencies it is necessary to model the series resistance of capacitors for better fidelity between real life and simulation

 Coupling Capacitors also affect the upper bandwidth of the previous stage. I usually model my coupling capacitors as the input to a stage only. As expected the higher value of the coupling capacitor the lower the lower cutoff frequency is. However as demonstrated below the coupling capacitor into the next stage also affects the upper cutoff frequency. o Unloaded amplifier and response

o Loaded amplifier C2 is to small

o Loaded amplifier with larger C2 has flatter response

 Next Stage Transistors have significant loading to high frequency signals. It seems that this is due to the BC depletion capacitance can greatly effect the upper frequency limit of a previous stage (as well as the current stage see below) o Unloaded amplifier

o Loaded with a second stage with decreased band width

o Loaded with capacitor equal to Capacitance BC note similar bandwidth to adding Q2

o Increased Re and Rc regains bandwidth Note however it is not possible to get the same bandwidth on the 2nd stage amp with the smaller RC and Re

o Putting an emitter follower between the stages nearly brings back bandwidth but slope of cutoff is higher

 The value of Ce to counter the roll off of an amplifier at higher frequencies.

 It appears that the most important transistor spice parameter for high frequency is cjc. This is the BC depleation capacitance discussed above! And found by replacing each spice parameter in a model one by one and noting the difference in frequency response.

 Gang capacitors use the frame as a common node. Therefore this common node would have to be the node connected to R1 above. This means that the frame would have to be insulated from ground, but even with an insulated knob touching the knob would allow the capacitance of my body to change the output frequency. Therefore I dropped the Colpitts design in favor of a Hartley design.