High-Frequency Oscillator Design with Independent Gate Finfet a Thesis

High-Frequency Oscillator Design with Independent Gate FinFET

A thesis presented to

the faculty of the Russ College of Engineering and Technology of Ohio University

In partial fulfillment

of the requirements for the degree

Master of Science

Yunus Kelestemur

December 2019

© 2019 Yunus Kelestemur. All Rights Reserved. 2

This thesis titled

High-Frequency Oscillator Design with Independent Gate FinFET

by

YUNUS KELESTEMUR

has been approved for

the School of Electrical Engineering and Computer Science

and the Russ College of Engineering and Technology by

Savas Kaya

Professor of Electrical Engineering

Mei Wei

Dean, Russ College of Engineering and Technology 3

ABSTRACT

YUNUS KELESTEMUR, M.S., December 2019, Electrical Engineering and Computer

Science

High-Frequency Oscillator Design with Independent Gate FinFET

Director of Thesis: Savas Kaya

There is an increasing demand for wireless communication because of its convenience for the system-on-chip (SoC) paradigm that integrates the whole system on a single chip. Most of SoC applications such as 5G mobile network, car radar, network-on- chip (NoC) communication require high-frequency oscillators. In particular, the wireless links that can be adapted for on-chip communication can greatly expand the power and latency concerns in future many-core (64 and above) computers. The transmitters in the

NoC routers would need very high-frequency wireless channels that must be driven by extremely compact and efficient oscillators that can operate as high as 500 GHz.

In this thesis, two high-frequency voltage-controlled oscillators are presented without using any varactors to control the frequency of oscillation. The independent gate

(IG) FinFETs are used to tune the oscillation frequency of the oscillators and simulations are carried out using Cadence Virtuoso design tools and BSIM-IMG transistor models inserted into a 65 nm RF-CMOS design kit. The first oscillator design is based on

Colpitts architecture using 65 nm IG-FinFETs. The oscillator has 165 GHz oscillation frequency with 3% tunability. The power consumption of the oscillator is 50mW and the area is less than 0.001mm2. The phase noise of the oscillator at 1 MHz is -70 dBc/Hz.

The second oscillator design is based on the cross-coupled push-push oscillator 4 architecture using 45 nm IG-FinFETs. The oscillator has 250 GHz oscillation frequency with 2% tunability. The power consumption of the oscillator is 12 mW and the area is less than 0.01mm2. The phase noise of the oscillator at 1 MHz is -82 dBc/Hz. Besides the novel oscillator topologies and their encouraging performance figures, this work also incorporates several other unique aspects, including the use of BSIM-IMG based models in connection with an RF-CMOS design kit, utilization of tunable transistor parasitics for

VCO design and incorporation of accurate modeling of 3D inductors obtained via 3D electro-magnetic solvers into the circuit analysis. Although the performance predictions are limited by the finite accuracy of the BSIM model at such elevated frequencies and by the lack of detailed layout rules for the IG-FinFETs, the work performed in this thesis lends strong credence to this transistor architecture for compact circuit development in analog mm-wave circuits in general and SoC wireless applications in particular.

5

TABLE OF CONTENTS

Page

Abstract ...... 3 List of Tables...... 7 List of Figures ...... 8 Chapter 1 : Introduction ...... 9 1.1 Overview ...... 9 1.2 Thesis Objectives ...... 12 1.3 Thesis Contributions and Layout ...... 12 Chapter 2 : Background ...... 13 2.1 MOSFET ...... 13 2.1.1 Operation ...... 14 2.1.2 Current-Voltage(I-V) Characteristics ...... 15 2.1.3 High-Frequency Model...... 17 2.1.4 Derivatives of MOSFET ...... 20 2.2 IG-FinFET ...... 22 2.2.1 Operation ...... 22 2.3 Oscillators ...... 25 2.3.1 Phase Noise ...... 26 2.4 Simulation tools ...... 27 2.4.1 Cadence Virtuoso CAD Environment ...... 28 2.4.2 BSIM ...... 28 2.4.3 Keysight Advanced Design Systems ...... 30 Chapter 3 : Colpitts Oscillator Design ...... 32 3.1 Colpitts Oscillator ...... 32 3.2 Design with IG-FinFET ...... 33 3.3 Simulation Results and Analysis ...... 36 3.4 Summary ...... 40 Chapter 4 : Cross coupled Push-Push Oscillator Design ...... 41 4.1 Cross Coupled Push-Push Oscillator ...... 41 4.2 Design with IG-FinFET ...... 44 4.3 Simulations Results and Analysis ...... 46 6

4.4 Summary ...... 51 Chapter 5 : Conclusions and Future Work ...... 52 5.1 Conclusions ...... 52 5.2 Future Work ...... 56 References ...... 58 Appendix A: BSIM Model File ...... 63 Appendix B: Netlist Files...... 65 Appendix C: Papers Contributed During The Course of This Degree ...... 67

7

LIST OF TABLES

Page

Table 5.1 : Similar contemporary oscillators ...... 54

8

LIST OF FIGURES

Page

Figure 2.1 : Top view of thin-body n-Channel MOSFET ...... 15 Figure 2.2 : Drain current vs Drain source voltage ...... 16 Figure 2.3 : Low-frequency small-signal model of MOSFET ...... 18 Figure 2.4 : Parasitic capacitances of a MOSFET ...... 19 Figure 2.5 : High-frequency small-signal model of a MOSFET ...... 20 Figure 2.6 : a) SOI FinFET, b) SOI tri-gate MOSFET, c) SOI π-gate MOSFET, d) SOI Ω-gate MOSFET, e) SOI gate-all-around MOSFET, f) bulk tri-gate MOSFET ...... 21 Figure 2.7 : IG-FinFET device structure ...... 23 Figure 2.8 : Oscillator system ...... 25 Figure 3.1 : Colpitts oscillator simplified biasing ...... 32 Figure 3.2 : Modified Colpitts oscillator with IG-FinFET ...... 34 Figure 3.3 : Small signal model of the modified Colpitts oscillator ...... 35 Figure 3.4 : IV curves of 65 nm IG FinFET with different back-gate bias ...... 37 Figure 3.5 : Change in oscillation frequency with back-gate bias voltage ...... 37 Figure 3.6 : Effects of gate width and length on oscillation frequency, power consumption and tuning range of the oscillator ...... 38 Figure 3.7 : Phase noise of the oscillator at different back-gate voltage ...... 39 Figure 4.1 : Negative resistance oscillator ...... 41 Figure 4.2 : Cross coupled oscillator active component schematic and small-signal model ...... 42 Figure 4.3 : (a) Simple push-push oscillator, (b) Cross coupled push-push oscillator ...... 43 Figure 4.4 : Schematic of the cross-coupled push-push oscillator with IG-FinFET ...... 44 Figure 4.5 : Small signal model of the cross-coupled pair with IG-FinFET ...... 45 Figure 4.6 : Electromagnetic simulation results of the inductor with 10µm radius ...... 47 Figure 4.7 : Effects of the back-gate bias on oscillation frequency, power consumption and power efficiency ...... 48 Figure 4.8 : Effects of gate width on oscillation frequency, power consumption and tuning range of the oscillator ...... 49 Figure 4.9 : Phase noise of the oscillator at different back-gate voltage ...... 50 Figure 4.10 : Power spectral density of the oscillator at -1V back-gate bias ...... 50 Figure 5.1 : Part of OWN router network ...... 56 9

CHAPTER 1 : INTRODUCTION

1.1 Overview

The transistor is the electronic switch that has enabled modern electronics which is now an integral part of our lives: We rely on transistors to communicate, capture, store and process information. These essential functions require a very large number of transistors. In some cases, such as information storage, there are alternative methods such as magnetic or optical to implement solutions without involving transistors. Even then, five-decades of advances in miniaturization of transistors and accompanying functional gains enabled solid-state storage solutions to be superior, more compact and more affordable. In other cases, such as information processing, there is no alternative to process information without transistors which could rival in performance. Alternatives such as spintronics, optical computing, and quantum computers are still in relatively early development stages and are not suitable for general consumer-grade applications or for mobile use. Therefore, the modern CMOS transistor technology is currently the best available solution for both storing and processing information by a long margin.

Vacuum tubes were used to control the current flow in circuits until 1947 when first point-contact transistors were discovered at Bell Labs in Murry Hill, NJ. At this time transistors were made from germanium, which changed with Henry Theurer of Bell Labs, who showed that high-quality silicon crystals could be drawn out of the molten silicon for building transistors. Hence silicon became the base material for building transistors around 1952. In 1957, the first integrated circuit was built by Jack Kilby at Texas

Instruments, who showed that several transistors and passive components can be 10 implemented on the same crystal at once. The next big jump in solid-state electronics was the development of field-effect transistors that utilized much less power for switching.

This has ushered a new era, starting from the early 1960s, for compact computers to be built using integrated circuit chips. [1] In 1965, Gordon Moore suggested that with material and fabrication advances, the number of transistors could double every two years, making integrated circuits more capable, smaller and cheaper at the same time. [2]

Until recently this goal was satisfied by continually reducing the sizes of the transistors.

However, the reduction of the size of the transistor alone was not enough to reach this goal, so the microprocessor designers increase the number of processing cores. This is needed to deal with the introduction of 5G of mobile networks, Internet of Things paradigm (wirelessly connected smart devices and appliances) and cloud computing.

With the increasing number of smart devices and the introduction of 5G data networks, we could expect a load increase in servers, which would imply that the servers would need even more complex and larger processor stacks. Hence the number of computing devices will continue to increase dramatically while their efficiency and reliability will become even more important. [3]

The increasing number of cores creates difficulties with the usage of shared resources and the amount of data to be moved around. The increasing number of cores also increases the difficulty to communicate with each other and the number of interconnections, especially in future servers expected to have hundreds of cores in one system. Optical-Wireless Network on chip (OWN) architecture is one proposed solution to optimize energy and delay in a high number of core systems. [4] It uses photonic 11 waveguides and switches as well as RF transceivers to create fixed and reconfigurable inter-connections between cores in addition to metal wired connections. OWN-like network-on-chip architectures (NoC) reduce wire complexity and improves power consumption [4]. However, acceptable performance and practical implementation of

NoCs heavily depend on the usage of extremely compact and efficient ultra-high- frequency (mm-wave or ~100 GHz) analog circuits. Such circuits are only possible by using the latest advanced in circuit design and the smallest transistor architectures. This thesis centers around such advanced circuit design practices for mm-wave circuits and ultra-compact transistor architectures.

Since the invention of the transistors, a lot of different modification to the original structure has been implemented to boost its performance, and reduce dimensions. The latest one in this series is the FinFET architecture that utilizes two closely coupled gates on either side a silicon ‘fin’ structure, that has become popular with its high ON/OFF current switching performance. FinFETs have been the standard CMOS transistor architecture in the last decade, especially due to their ultra-small (currently ~10nm) gate dimensions. However, these compact and twin-gated transistors are also very capable switches for analog mm-wave circuit design [14]. They can impact NoCs' designs and provide means to develop additional solutions for many-core computers. As a result, in this thesis, the focus has been the novel analog circuits, in particular, ultra-compact oscillators built using nanoscale FinFETs for wireless transceivers operating above 100

GHz. 12

1.2 Thesis Objectives

The objective of this thesis is to explore novel ultra-compact oscillators based on

FinFET devices that could be used for short-range, high-speed wireless communications like OWN architecture. In particular, Colpitts and push-push oscillator architectures that have tunable performance characteristics and are suitable for operation above 100GHz wireless transceivers have been considered. Besides designing and developing these novel circuits, an additional objective is to explore and optimize their operation for a small area and low phase noise which is crucial for NoCs applications.

1.3 Thesis Contributions and Layout

Following the current chapter that has provided the historical context and general motivation of the thesis, Chapter 2 briefly describes some of the electrical devices and useful tools and concepts that are used in this thesis. Chapter 3 proposes a compact voltage-controlled Colpitts oscillator design and illustrates its simulated capabilities.

Chapter 4 proposes a voltage-controlled push-push oscillator design based on the cross- coupled oscillator and similarly provides its performance using advanced CAD tools.

Both oscillators have been designed using the independent-gate fin field-effect transistor instead of conventional metal oxide semiconductor field-effect transistors in silicon. In the final chapter, the results and future work are discussed. The designed oscillators:

• have reduced the number of transistors using IG-FinFET

• are expected to have a small area and power consumption than its counterparts

• operate in frequencies from 100 GHz to 250 GHz

• are ideal for high bandwidth and small distance wireless router applications. 13

CHAPTER 2 : BACKGROUND

This chapter briefly describes some of the electrical devices and concepts that are used in both Chapters 3 and 4. First, it will explain what metal oxide semiconductor field- effect transistor (MOSFET) operates and how it behaves in high frequencies; how it is improved over time. After MOSFET the chapter describes what an independent-gate silicon fin field-effect transistor (IG-FinFET) is, a core component for the work in both chapter 3 and 4. After that, the chapter introduces the topology of the Colpitts and push- push oscillators. In the final section, it describes the simulation methods that are used in both chapter 4 and 5.

2.1 MOSFET

Simply stated, MOSFETs are voltage-controlled switches with a maximum current handling capability. The maximum current that passes through the device depends on the gate voltage level. When the gate voltage is above the threshold, for very low drive voltages, the current passing from drain to source electrodes increases linearly, much like a resistor, this is why it is named transistors. Eventually, this linear relationship saturates, and the current is simply controlled only by tthe gate voltage at higher drain-source voltages. There are other types of transistors like bipolar junction transistor (BJT) or heterojunction bipolar transistor (HBT), even vacuum tube elements, where the linear response is very narrow compared to a MOSFET. However, MOSFET is the most widely used transistor in the market. Because, it is the building block of CMOS by complementary integration of one n-type (electron channel) and one p-type (hole channel) transistor working in tandem. Even though conventional MOSFET is not used in 14 this work, understanding the MOSFET would help understand the IG-FinFET structure that has been the main transistor in our designs. For simplicity, the next section is based on n-Channel MOSFET, even though a similar description can be made for the p-channel counterpart. [5]

2.1.1 Operation

The n-Channel MOSFET has four terminals including the body connection which is usually connected to the ground/reference potential. Gate terminal has control over the current that flows through from drain to the source terminal. The cross-section of the n-

Channel MOSFET structure is illustrated in Figure 2.1. The gate terminal is separated from the silicon substrate with an insulator layer called gate oxide. If the gate voltage is positive, it creates an electric field that attracts electrons from the substrate. When the gate voltage is high enough to form an electron channel between source and drain, the current would start flow from the drain to the source provided drain is positively biased.

Otherwise, the device would not conduct current. The gate voltage that makes the device switch from a non-conductive state to the conductive state is called the threshold voltage

(VTH). If the drain voltage is substantially high, then the transistor would go into saturation mode. In the saturation mode, the current no longer depends on the drain voltage it becomes a function of the gate voltage. [5] 15

Figure 2.1 : Top view of thin-body n-Channel MOSFET [27]

2.1.2 Current-Voltage(I-V) Characteristics

The drain current (ID) behavior can be divided into two regions depending on the drain-source voltage (VDS). In the linear (triode) region, a channel is formed between drain and source, and it is not saturated (pinched-off) yet. In other words, we can express that VTH < VGS and VDS < VGS -VTH. In the triode region, the drain current function would be

푊 1 퐼 = µ 퐶 [(푉 − 푉 )푉 − 푉2 ] 퐷 푛 표푥 퐿 퐺푆 푇퐻 퐷푆 2 퐷푆 2.1

Where L is the gate length of the transistor, it is the distance between the source and drain junctions, and W is the width of the gate. Moreover, µn is the electron mobility of the silicon that models the velocity of electrons under a linear electric field response. Cox is 16 the oxide capacitance per unit area, it depends on the dielectric material that is used for gate oxide and its thickness. When VGS -VTH, also called “overdrive voltage”, becomes smaller than the drain-source voltage the device enters the saturation region. In this region, the drain current can be expressed as

1 푊 2.2 퐼 = µ 퐶 (푉 − 푉 )2 퐷 2 푛 표푥 퐿′ 퐺푆 푇퐻

Where L’Transconductance (gm) is defined to measure how well the device converts the gate voltage to the drain current. And it is defined as

휕퐼퐷 푊 푔푚 = | = µ푛퐶표푥 (푉퐺푆 − 푉푇퐻) 휕푉퐺푆 퐿 2.3 푉퐷푆 퐶표푛푠푡.

Figure 2.2 : Drain current vs Drain source voltage [5]

17

There are second-order effects that affect the drain current. One of them is channel length modulation, which causes the previous assertion that L’≤L. As the drain voltage increases, the depletion region around the drain region expands nd L’ (the effective gate length) gets reduced. This effect is called channel length modulation. It is easier to model channel length modulation, if we assume a first-order relationship between VDS and L’, i.e. L’=L/(1+ 휆VDS) and express the drain current as

1 푊 2.4 퐼 = µ 퐶 (푉 − 푉 )2(1 + 휆푉 ) 퐷 2 푛 표푥 퐿 퐺푆 푇퐻 퐷푆

The channel length modulation (휆) is one of the second-order effects. The other second- order effects such as electron velocity saturation at very high electric fields or body effect

(threshold’s dependence on body bias) are not relevant to this work, therefore; they are not discussed in this chapter. [5]

2.1.3 High-Frequency Model

In most of the digital applications, MOSFETs are used in either OFF or saturation mode. Since the ultimate aim is to include MOSFETs in general (SPICE) solvers that rely on fundamental circuit elements and evaluate operational performance as realistically as possible, several circuit models have been developed for a MOSFET that operates in the saturation region. One of them is the hybrid-π model and it is illustrated in Figure 2.3.

However, this model assumes that all the impedances of the parasitic capacitances are zero. This assumption is valid for low frequencies, but for high-frequency applications, the model needs a revision or inclusion of the external impedances in the design. 18

Figure 2.3 : Low-frequency small-signal model of MOSFET [5]

The parasitic capacitances of a MOSFET can be seen in Figure 2.4. Gate capacitance C6 is formed between gate and channel and it can be calculated as WLCox; C3 is formed between body and channel and it can be calculated as WL√푞휖푆𝑖푁푆푢푏 / (4휙퐹) .

Where q is the charge of an electron, and 휖푆𝑖 is the silicon permittivity which are constant values, the NSub is the density of impurities in the silicon substrate, and 휙퐹 is the semiconductor potential (Fermi level shifting) to induce the number of holes found in the

Si bulk. Ideally, there should not be an overlap between gate and drain or gate and source.

However due to fabrication techniques that are used to create the source and drain junctions, an overlap is formed between these junctions and the gate. Also, these overlap capacitances (Cov) are affected by the depletion layer that is formed around the source and drain junctions. The sizes of depletion layers that are formed around the source and drain junctions depend on the gate-source and gate-drain voltages. However, when the transistor in saturation C4 approximately equal to 2WLCox/3 +WCov and C5 approximately equal to WCov where Cov is the overlap capacitance per unit width. Junction capacitances 19

C1 and C2 are formed between source, drain, and substrate. These junction capacitances are dissected into two parts, one part is the bottom of the junction the other is the sidewall of the junction. Cj represents the bottom capacitance per unit area of the junction and Cjsw represents the sidewall capacitance per unit length of the junction. Depending on the geometry of the MOSFET the junction of the capacitance is calculated by adding the sidewall and the bottom capacitances of the junction.

Figure 2.4 : Parasitic capacitances of a MOSFET [5]

With the addition of the parasitic capacitors to the small-signal model of the

MOSFET, the high-frequency small-signal model of the MOSFET is obtained in Figure

2.5. Although there are other parasitic capacitances that are formed between adjacent transistors, at metal contacts or between metal contacts, these parasitic effects are ignored to simplify the analysis of the circuit. [5] 20

Figure 2.5 : High-frequency small-signal model of a MOSFET [5]

2.1.4 Derivatives of MOSFET

Gordon Moore has predicted that the number of transistors on a chip would double every other year in 1975. [2] Since then, this prediction has been validated until recent years. The chip makers have reduced the size of the MOSFET into its half in every other year. However, as the gate length becomes smaller, several issues have emerged such as the increase in leakage current, and inability to raise the max drain current allowed through the transistors. To combat these issues FinFET structure has been proposed in 2001. In FinFET the gate wraps around the channel which allows the gate to have more control over the channel compared to the conventional planar MOSFET. [11]

However, it has not been used in mass production until 2011, due to required changes to the standard fabrication techniques. Intel was the first company that has mass-produced the FinFET structure in their products. Another improvement has been done by using silicon-on-insulator (SOI) transistors. This helped to reduce the parasitic effects of the transistor. After the introduction of FinFET, several other structure types have been developed as illustrated in Figure 2.6. [10]. Although small differences exist in these 21 alternate forms, they all can be considered as different versions of the FinFET architecture that has now become the mainstay of CMOS technology. In all cases, there is a single gate design that overlaps around the main channel region.

Figure 2.6 : a) SOI FinFET, b) SOI tri-gate MOSFET, c) SOI π-gate MOSFET, d) SOI Ω-gate MOSFET, e) SOI gate-all-around MOSFET, f) bulk tri-gate MOSFET [10]

Another research area of MOSFET other than geometry is the materials that are used in the production of MOSFET such as substrate material, the gate oxide material, contact material. Improvement of the gate oxide material has allowed the engineers to build thinner gate oxides which improve the gate’s control over the channel. Several semiconductor materials have been proposed for channel formation instead of silicon such as III-V semiconductors, Ge, SiGe alloy, etc. Even though these materials improve 22 the electron and hole mobility, which increases the drain current and switching frequency, they are not used in mass-produced chips since these materials increase the complexity of the fabrication process which increases the manufacturing cost. [12]

2.2 IG-FinFET

Silicon fin field-effect transistor (FinFET) is operationally similar to the

MOSFET, albeit using twin gates that control the flow of the current. It is structurally significantly different from the MOSFET, with the gate electrode of the FinFET wrapping around all three sides of the silicon which can be seen in figure 2.6a. This structure improves the drain current at the on state and reduces the leakage current at the off state. However, in the independent-gate version of the silicon fin field-effect transistor

(IG-FinFET), the gate does not wrap around all three sides of the channel. Instead, the gates are placed at the two opposite sides of the silicon and isolated from one another electrically. Therefore, there are two gates in IG-FinFET which can be controlled independently, making it possible to control two channels using individual signals, which could be especially an asset in analog circuit engineering.

2.2.1 Operation

The IG-FinFET has two gates that control the flow of current between source and drain terminals. Throughout the thesis they are referred as the front (top) gate and back

(bottom) gates for practical reasons and clarity, although they are physically equivalent to one another. Similar to the MOSFET, the gates are separated from the silicon fins with an insulator. Applying positive voltage to the gates creates an electric field that attracts electrons from the substrate. When the electric field is strong enough to form an electron 23 channel between source and drain, the current would start to go through from drain to source. Otherwise, the device would not conduct current. In the case of IG-FinFETs, this can be done with two separate channels, if additional fabrication steps are used to disconnect and isolate them from each other.

Figure 2.7 : IG-FinFET device structure [28]

The gate voltages that make the device to switch from the non-conductive state to the conductive state is called the threshold voltage (VTH). If the drain voltage is substantially high, then the transistor would go into saturation mode. In the saturation mode, the current would no longer depend on the drain voltage it becomes a function of the gate voltages similar to MOSFET devices. However, due to extremely thin

(~typically 10nm or less) thickness of the silicon fin used in ultra-small (L < 22 nm) devices, the threshold voltage of one gate would also depend on the state of the other 24 gate. Since the distance between the gates and channels are so small both channels become electrostatically paired. [24] Moreover, such small dimensions also imply that quantum mechanical bound states can be observed even at room temperature by raising the lowest energy of the electrons, resulting in higher thresholds. Moreover, the precise position of the quantum mechanically correct electron concentration peak will move away from the insulator interface as the silicon fin gets even smaller or gate biases change, resulting in appreciable changes in the channel mobility. As a result, the threshold voltage, maximum drain current and unwanted gate leakage observed in IG-

FinFETs can be a complex problem, determined by the choice of insulator and channel material, final device geometry and actual bias conditions. For the purposes of the analog circuit design, it is sufficient to understand that actual dimensions and bias conditions will impact both transistor transconductance (gm) and parasitic capacitances. [26]

The FinFET devices have several advantages over the planar MOSFET devices.

The 3D structure of the FinFET and the double gate controls the device more efficiently.

Because of the device structure, it has lower leakage current and higher on current compared to the same width and length planar MOSFET devices. Which also improves the power efficiency of the device. [15] However, FinFET has some disadvantages as well. It has a more complicated fabrication process which reduces die yield significantly.

This increases the cost of manufacturing FinFET devices. Also, 3D geometry of the

FinFET and the large number of fins increases the parasitic capacitance of the transistor.

In this present work, we utilize such additional capacitive parasitics that can be changed 25 by the back-gate bias, to create tunable oscillators without resorting to additional integrated capacitors that would imply more area and power dissipation.

2.3 Oscillators

Oscillators are bi-stable systems that produce periodic changes at the output. They are essential elements in all electronic computation and communication systems. They are used to generate clock signals in digital microprocessors and generate the carrier signals used for transmission and modulation in communication systems. In general, oscillators do not require an external input signal to generate an output signal, except the tunable oscillators. The basic oscillator system is shown in Figure 2.8.

Figure 2.8 : Oscillator system

The transfer function of the oscillator is shown in equation 2.5. There is a specific point for H(s) to acquire oscillation in the system. That is called oscillation condition.

When H(s) = -1 gain would be infinite, and the system will become unstable, producing oscillations that would continue indefinitely.

푉표푢푡 퐻(푠) = 푉𝑖푛 1 + 퐻(푠) 2.5

26

There are different types of oscillators that are used in electronic systems such as ring oscillators, crystal oscillators, and LC oscillators. Ring oscillators consist of an odd number of inverters that are connected with one another and rely on the inherent delay on each state and output stage driving the first stage with a feedback loop. Crystal oscillators use piezoelectric nature of unique crystals to generate an oscillation resulting from resonant thermal vibrations at the atomic lattice. They have a very high Q factor and acceptable temperature stability. LC oscillators use an inductor (L) and capacitor (C) tank circuit to generate a suitable pole in H(s) function so that an appropriate oscillation condition can be met at the output node along with gain providing amplification circuit to sustain the oscillation. [5]

There are also voltage-controlled oscillators. They use known oscillator architectures, as listed above, with the addition of a tunable circuit element that adjusts the frequency of oscillation. This is not only a very desirable property that allows the user to adjust the oscillators operation range, but it is also very necessary in many cases.

Because, the fabrication process of semiconductors is not perfect with appreciable tolerances, the final oscillator circuit that has been designed and fabricated may not have the desired frequency. If a tunable element is incorporated, the frequency oscillation could be tuned externally to the desired frequency, even after fabrication.

2.3.1 Phase Noise

Phase noise is an important quality of the oscillators: it measures how stable and accurate is the oscillator over long periods. Due to parasitically coupled (thermal, mechanical and electromagnetic) signals in the environment and imperfections in the 27 materials used, the oscillator output could show a deviation from its ideal periodic behavior. The parasitic capacitances and resistances resulting from the imperfect device fabrication process could also contribute to the phase noise. All these factors lead to small random variations (noise) in the measured periods, which can be expressed as changes to the ideal (expected) phase. Phase noise is a very important figure of merit in many time sensitive applications such as master clocks in digital systems and radio communication. As a result of phase noise, the oscillation signal would not be a pure single sine wave, but rather a summation of several sine waves that are close to the oscillation frequency. Phase noise is defined as the power of the output signal at a given frequency away from the fundamental oscillation frequency and plotted as a function of this gap in frequency.[5]

2.4 Simulation tools

For nanoelectronics device and circuit engineering, computer-aided simulation tools are essential to design successfully working devices. They are needed because of the huge size of components (easily exceeding thousands, even in relatively simple circuits), very complex mathematical models, necessity include 2D/3D modeling of physical structure for accurate electro-magnetic and transport calculations. Such a large number of calculations and optimizations can only be done via a computer. In fact, with the ongoing development in the scaling down of transistors, even a single transistor circuit can become mathematically very complex when quantum mechanical details are incorporated. Consequently, we utilize several simulation tools in this work as outlined below. 28

2.4.1 Cadence Virtuoso CAD Environment

Cadence®’s electronic computer-aided design (eCAD) suite brings together dozens of specialized design, optimization, analysis, and integration tools on a common platform. Virtuoso is one of the main graphical user interfaces that allow interactions with integrated-circuit design toolset. Besides the digital and analog circuits simulations at various degrees of abstraction, Virtuoso also allows parsing description of the circuits to lower (physical masks) and higher functional netlists that can be used for timing analysis and verification in digital circuits as well as electromagnetic and thermal simulations on printed circuit boards. This is one of the most popular and reliable circuit simulators for integrated circuit designs on the chip level. The program provides a platform for integrated circuit design provided that the manufacturer or user provides the process design kit (PDK) that describes rules and available capabilities for the physical design and electrical characteristics of the components. The PDK`s are developed by foundries to match and simulate their fabrication process. In this work, we utilize 65 nm

RF-CMOS PDK (8rfCMOS) by Global Foundries (formerly IBM) that has been available for academic use and physical implementation via MOSIS, the non-profit foundry that allows multi-university runs for academic and research projects at a low cost.

2.4.2 BSIM

SPICE® is the publicly available circuit simulation engine that has been developed initially by the University of California Berkeley since the 1970s. It is adopted at the core of many commercial simulators that further develop them by building add-on functionalities and user interfaces. SPICE utilizes advanced mathematical models 29 developed for individual electronic components by researchers and manufacturers to accurately integrate commercial devices for simulation. BSIM is the main family of mathematical models for transistor simulation that is also developed at the University of

California, Berkeley. BSIM models can be integrated with Cadence’s Virtuoso environment and many other vendors utilize it to account for the accurate operation of advanced transistors. There are many BSIM model levels specifically developed for different transistor types such as FinFET, IG-FinFET, standard MOSFET, etc. Any of these BSIM model levels can be used in simulations with the Cadence Virtuoso.

However, they do not provide any physical layout model for the masks, which is part of the PDKs provided by actual manufacturers. In the present work, we utilize the BSIM-

IMG model that has been developed over the last decade for an accurate description of

IG-FinFET. [25]

The BSIM-IMG models the transistor using surface potentials, and integrated charge densities at the source and drain ends are obtained by solving the Poisson's equation in a fully depleted, lightly doped body. Since the surface potential equation is derived based on Poisson's equation, the model captures volume inversion effects very well and shows excellent scalability compared with 2D device simulation. Other important effects considered in the model are short channel effects, mobility degradation, velocity saturation, velocity overshoot, series resistance, channel length modulation, quantum mechanical effects included via first-order corrections, gate tunneling current, gate-induced-drain-leakage, and parasitic capacitance. [30] Although the symmetrically driven (two gates shorted) version of this model BSIM-CMG has been available more 30 than a decade, the independent-gate version has just become available recently, due to additional testing and accuracy improvements needed for it to be reliable. In general, it is important to remember that BSIM models are only as accurate as the experimental calibrations were done using the existing devices. Therefore, extrapolations to smaller dimensions and non-standard operation conditions can generate additional errors and complications if not performed with care. As a result, we keep the smallest gate dimensions at 32 nm in this work, despite the fact that smaller FinFETs can be as small as

10 nm currently.

2.4.3 Keysight Advanced Design Systems

In high-frequency RF and mm-wave designs, where the wave nature of the electric signal can no longer be ignored and wavelength approaches the physical dimensions, it is necessary to solve the fundamental electromagnetic problem (Maxwell equations) in full 2D/3D detail. Such accurate simulations can capture all parasitic

(unintended) couplings as well as more accurate features of elements such as antennas, inductors, and waveguides, which cannot be captured by the lumped (L, C, R) elements used in the SPICE solvers. To this end, we utilized Keysight’s ADS simulator that allows excellent integration between the e-Mag and circuit solvers. It has advanced meshing tools and mathematical solvers better suited for electromagnetic simulation problems in

2D/3D. The program simulates a given geometric structure with dielectric materials, metal contacts, and ground planes and can create an S-parameter file to be able to port the results to other systems. We carried out inductor simulations based on the description of the physical structure from the IBM’s 65 nm CMOS PDK and ported the results to 31

Virtuoso to get much better accuracy in high frequencies involved in the oscillator circuits.

32

CHAPTER 3 : COLPITTS OSCILLATOR DESIGN

In this chapter, a Colpitts oscillator design has been proposed for high frequency and short distance, wireless communication applications. The chapter starts with the explanations of both the original and proposed Colpitts oscillator designs. In the second part, the simulation results of the proposed design have been presented and discussed. In the last part, the summary of the simulation results and the possible future improvements have been presented.

3.1 Colpitts Oscillator

The Colpitts oscillator is one of the simplest oscillators designs with an LC tank circuit. Also, it only uses one inductor and one transistor which makes the oscillator area much smaller than other LC oscillators.

`

Figure 3.1 : Colpitts oscillator simplified biasing [7]

The start-up requirement for the topology in Figure 3.1 is, 33

2 푔푚 > 휔 퐶1퐶2푅푠 3.1 and the frequency of the oscillation is,

1 1 1 1 푓 = √ ( + ) 3.2 2휋 퐿 퐶1 퐶2

where 푔푚 is the intrinsic gain of the transistor in Figure 3.1. [6]. Conventionally, by tuning the capacitors (i.e. using varactors) this circuit could be turned into a voltage- controlled oscillator (VCO). However, this requires additional dedicated space and can also suffer from other imperfections of building a large area diode capacitor (varactor).

For large gm values (high gain transistors) with sufficiently small L and C values, the oscillator can reach very high-frequency operation.

3.2 Design with IG-FinFET

This oscillator is designed to work in high frequencies with a minimum area as a voltage-controlled oscillator. Also, it is designed to have sufficient power output at the inductor, since the inductor is going to be changed with an antenna for data transmission for the future work. The oscillation frequency with the minimum capacitors from the

65nm CMOS library is around 50 GHz which is less than required. In order to reduce the area and increase the frequency, all the capacitors are removed from the original Colpitts oscillator design. Moreover, the IG-FinFET is used to control the oscillation frequency of the circuit instead of a varactor, which also reduced the area of the oscillator. In order to save the area, the inductor is connected to the VDD supply, which eliminated the need for a biasing circuit for the transistor M1. For the current source of the Colpitts oscillator, an 34

IG-FinFET in with a bias voltage is used. The final oscillator circuit can be seen in Figure

3.2.

Figure 3.2 : Modified Colpitts oscillator with IG-FinFET [7]

With these changes, the oscillation condition and oscillation frequency have changed.

The new equation can be calculated using the small-signal model in Figure 3.3 of the modified design. The oscillation condition would be

2 푔푚푒푞 > 휔 퐶𝑔푠1(퐶푏𝑔푠1 + 퐶𝑔푑2 + 퐶푏𝑔푑2 )푅푠 3.3

where 푔푚푒푞 is the equivalent intrinsic gain of the transistor M1 and Rs is the resistance of

the inductor. The 퐶𝑔푠1is the parasitic capacitance between the front-gate and the source of

the M1 transistor. The 퐶푏𝑔푠1is the parasitic capacitance between the back-gate and the

source of the M1 transistor. The 퐶𝑔푑2 is the parasitic capacitance between the front-gate

and the drain of the M2 transistor. The 퐶푏𝑔푑2is the parasitic capacitance between the back- gate and the drain of the M2 transistor. Consequently, the oscillation frequency would be, 35

1 1 1 푓 = √ ( ) 2휋 퐿 퐶푡표푡푎푙 3.4 where Ctotal is the equivalent capacitance from the inductor’s ends. So Ctotal would be,

1 퐶 = + 퐶 푡표푡푎푙 1 1 𝑔푑1 + 퐶푏𝑔푠1 + 퐶𝑔푑2 + 퐶푏𝑔푑2 퐶𝑔푠1 3.5

where the 퐶𝑔푑1 is the parasitic capacitance between the front-gate and the drain of the M1

transistor. 퐶푏𝑔푠1is dependent on the gate-source voltage, in this case, Vbias voltage source in Figure 3.2.

Figure 3.3 : Small signal model of the modified Colpitts oscillator [7]

The modified Colpitts oscillators rely on the back-gate bias voltage to tune the oscillation frequency. And the simplified circuit reduces the area consumption. 36

3.3 Simulation Results and Analysis

For the circuit simulations, Cadence Virtuoso Analog Design Environment (ADE) and Spectre RF version 6.1.7 has been used. For the inductor, a one-turn spiral inductor with 10 µm radius is used which is the smallest inductor that is available in the 55 nm

BiCMOS library from ST Microelectronics. For the transistors, BSIM-IMG version

102.9.1 which is a transistor model of FinFET with independent gates, has been used.

The proposed design can be seen in Figure 3.2. The transistors both have 65nm gate length and 8µm gate width. For the following simulations, VCur has the same value with

VDD to simplify the design and reduce the area however, it can be fine-tuned for other applications of this oscillator.

The front-gate DC sweep results of the transistor with various back-gate bias is shown in Figure 3.4. The simulated transistor has 65nm gate length and 8µm width.

Increasing the transistor’s back-gate bias reduces the threshold voltage and increases the drain current of the transistors. This allows the designer to have more control over the transistors. Also increasing the back-gate bias voltage of the transistor, increases the length of the depletion region which in turn increases the parasitic capacitance of the transistor. Change in the parasitic capacitance of the transistor M1 of Figure 3.2, in the

Colpitts oscillator, changes the frequency of oscillation. With that, the frequency of oscillation can be tuned without varactors. This reduces both the area and the power consumption of the oscillator. 37

Figure 3.4 : IV curves of 65 nm IG FinFET with different back-gate bias [7]

The effect of the back-gate bias in the oscillation frequency of the proposed oscillator with 2V VDD is shown in Figure 3.5. Increasing back-gate bias reduces the oscillation frequency of the oscillator. Also, negative back-gate bias voltage has been used in order to improve the phase noise of the oscillator.

Figure 3.5 : Change in oscillation frequency with back-gate-bias voltage [7] 38

The effects of the gate width and gate length on various properties of the oscillator can be seen in Figure 3.6. The first subplot from the top shows the change in frequency depending on the gate width at different gate lengths. The middle subplot shows the tuning range of the oscillator depending on the gate width at different gate lengths. The tuning range of the oscillator is the difference between the maximum frequency of oscillation which is at -1V back-gate bias voltage and the minimum frequency of oscillation which is at 0V back-gate bias voltage. And the last subplot shows the power consumption of the oscillator depending on gate width at different gate lengths. For this simulation, VDD is chosen to be 1V.

Figure 3.6 : Effects of gate width and length on oscillation frequency, power consumption and tuning range of the oscillator [7]

The simulated phase noise at 1 MHz with 0V back-gate bias is -70dBc/Hz. As the back-gate bias goes to -2V, the phase noise gradually deteriorates to -65dBc/Hz. The 39 phase noise can be improved by additional circuitry or by reducing the oscillation frequency. When the inductor changed such that the frequency of oscillation is 65GHz, the simulated phase noise is -90.5dBc/Hz. Even though the phase noise of the oscillator is a little bit lower than its counterparts, it is enough for short-range, on-off keying communication applications which is the targeted application for the proposed oscillator.

As seen in Figure 3.6 reducing gate length increases the frequency of oscillation and reduces power consumption. However, it also reduces the tuning range of the oscillator. In order to have a reasonable tuning range 65nm process is chosen for this project. For the gate width of the transistor, 8µm has been chosen, which was the minimum possible gate width for the oscillator in order to have oscillation. For the transistors that have gate width less than 8µm, the gain of the transistor M1 is not enough to start the oscillation.

Figure 3.7 : Phase noise of the oscillator at different back-gate voltage [7] 40

3.4 Summary

The proposed voltage-controlled on-chip oscillator has an oscillation frequency centered around 160GHz and has a 3% tunable oscillation frequency range. The frequency of the oscillation is tuned from the back-gate of the M1 transistor which can be seen in Figure 3.2. Also, the oscillator is derived from the Colpitts oscillator. Both of these design decisions have allowed the oscillator to have a small form factor. The complete oscillator has only one inductor and two transistors which would occupy

0.0012mm2 area on the chip.

Even though the proposed oscillator needs improvement on phase noise for some applications, it would be enough for an on-off keying transmitter which is the intended target. This oscillator is designed to work in a high-frequency RF transmitter with on-off keying modulation for short-range communication. However, this design could not reach the required frequency which was around 300GHz therefore, push-push oscillator design is explored in Chapter 4. 41

CHAPTER 4 : CROSS COUPLED PUSH-PUSH OSCILLATOR DESIGN

In this chapter, a cross-coupled push-push oscillator design has been proposed for high frequency and short distance, wireless communication applications. The chapter starts with the explanations of both cross-coupled and the proposed oscillator design. In the second part, the simulation results of the proposed design have been presented and discussed. In the last part, the summary of the simulation results and the possible future improvements have been presented.

4.1 Cross Coupled Push-Push Oscillator

Negative resistance oscillators are one of the most common oscillator configurations. The oscillation occurs if the active component generates the energy equal to the lost energy on the inductor and capacitor. In other words, the active component behaves like a negative resistance that is why it is called a negative resistance oscillator.

Since the resistances cancel each other, the LC circuit would oscillate indefinitely with a period of 2휋√퐿퐶 .

Figure 4.1 : Negative resistance oscillator

The cross-coupled oscillator is one of the configurations of the negative resistance oscillators. The cross-coupled core circuit can be seen in Figure 4.2. The input resistance 42 of the active component can be engineered to have a negative value. This would generate the lost energy on the passive components of the oscillator.

Figure 4.2 : Cross coupled oscillator active component schematic and small-signal model

The input impedance of the active component can be calculated as

2푟0 2 4.1 푍𝑖푛 = + 1 − 푔푚푟0 푗휔(퐶𝑔푠 + 4퐶𝑔푑)

where 푟1 = 푟2 = 푟0 the internal resistances of the transistors, 퐶𝑔푠1 = 퐶𝑔푠2 = 퐶𝑔푠 the gate-

source parasitic capacitances of the transistors, 퐶𝑔푑1 = 퐶𝑔푑2 = 퐶𝑔푑 the gate-drain

parasitic capacitances of the transistors, and 푔푚1 = 푔푚2 = 푔푚 the transconductances of the transistors since the transistors are matched. When this cross-coupled pair connected to the oscillator, the transistors would require additional biasing circuits in order to operate the transistors. Instead of using one inductor, two inductors connected to the VDD are used to avoid the need for additional biasing circuits. Also, instead of the capacitor, varactors are used to control the oscillation frequency. Both additions to the oscillator are common practice for voltage-controlled oscillator design with cross-coupled pair. [5] 43

Due to non-linearities on the oscillator circuit, higher harmonic oscillations are created by the oscillator. The push-push oscillators extract the second harmonic of the oscillator. Which achieves higher frequencies than fmax of the transistors that are used in oscillator core. The second harmonic simply can be extracted by adding two oscillation signals with a 180o phase difference. One way of doing that is by using three inductors as in Figure 4.3(a). The final circuit would look like Figure 4.4. Since the input impedance of the cross-coupled pair (4.1) and the inductor have some capacitance, the LC tank is already created without the additional capacitors.

Figure 4.3 : (a) Simple push-push oscillator, (b) Cross coupled push-push oscillator

Oscillation condition would be

2푟0 4.2 > 푅푃 푔푚푟0 − 1 44 where RP is the equivalent resistance of the inductor network which is parallel to the cross-coupled pair. Normally, instead of being grater, it should be equal to the RP which would improve the phase noise of the fundamental oscillation. However, the output of the push-push oscillator would have a larger power output with the increase of the nonlinearity of the fundamental oscillation. [9]

4.2 Design with IG-FinFET

With the IG-FinFETs the oscillator would become a voltage-controlled oscillator without using varactors. Since changing the back-gate voltage of the transistors would change the input capacitance of the cross-coupled pair, the oscillation would be changed without varactors. Also, an additional current source is introduced to the design to limit the output amplitude change, as the back-gate bias voltage of the transistors change. The capacitor at the output is added to improve the phase noise of the oscillator.

Figure 4.4 : Schematic of the cross-coupled push-push oscillator with IG-FinFET [16] 45

o Since the oscillation at M1 has 180 phase difference with the oscillation at M2, the signals cancel each other out at source connection of M1 and M2. Therefore, it would creates a virtual ground for small signal analysis. The small-signal model of the oscillator can be seen in Figure 4.5.

Figure 4.5 : Small signal model of the cross-coupled pair with IG-FinFET

The input impedance of the cross-coupled pair when the transistors are matched can be calculated as,

2푟푒푞 2 4.3 푍𝑖푛 = + 1 − 푔푚푟푒푞 푗휔(퐶푏𝑔푑 + 퐶𝑔푠 + 4퐶𝑔푑) where 푟1푒푞 = 푟2푒푞 = 푟푒푞 are the equivalent internal resistances of the IG-FinFETs,

퐶𝑔푠1 = 퐶𝑔푠2 = 퐶𝑔푠 , 퐶𝑔푑1 = 퐶𝑔푑2 = 퐶𝑔푑, 퐶푏𝑔푑1 = 퐶푏𝑔푑2 = 퐶푏𝑔푑 are the parasitic

capacitances of the IG-FinFETs, and 푔푚1 = 푔푚2 = 푔푚 are the equivalent transconductances of the IG-FinFETs. The oscillation condition would be -RP > real (Zin) where RP is the equivalent resistance of the inductor network that is parallel to the cross- coupled pair. And the oscillation frequency can be calculated as where L1=L2=L 46

1 4.4 푓푝푢푠ℎ−푝푢푠ℎ = 휋√퐿(퐶푏𝑔푑 + 퐶𝑔푠 + 4퐶𝑔푑)

It can be seen from equation 4.4 oscillation that frequency is dependent on Cbgd (back- gate to drain capacitance) and it can be tuned by changing the back-gate bias voltage of the transistor.

4.3 Simulations Results and Analysis

For the circuit simulations, Cadence Virtuoso Analog Design Environment (ADE) and Spectre RF version 6.1.7 have been used. For the inductor designs, the 55 nm

BiCMOS library from ST Microelectronics is used. Moreover, electromagnetic simulation is performed on the inductor and S parameters of the inductor are imported to

Cadence Virtuoso for better accuracy. Advanced Design Systems (ADS) 2011.05 software from Keysight is used for that electromagnetic simulation. For the transistors,

BSIM-IMG version 102.9.1 which is a transistor model of IG-FinFET with independent gates, has been used. The proposed design can be seen in Figure 4.4. All of the transistors have 45nm gate length. To simplify the design and reduce the area, gates of the transistor

M3 are connected to the VDD however, it can be fine-tuned for other applications of this oscillator. Since the transistor merely serves as a current source for the oscillator.

Even though this oscillator contains four inductors, three of them are identical.

For the small inductors, the electromagnetic simulation results are presented in Figure

4.6. The inductance of the inductor has increased by 6% around 250Ghz compared to its expected value. Also, in Figure 4.6, the layout of the inductor can be seen. The inductor is designed to have an octagonal shape; in order to match the inductor from the 55nm 47

BiCMOS library from ST Microelectronics. It also has similar dielectric and conductive material. Due to the complex structure of the inductor’s dielectrics, the designed inductor does not have the exact same architecture with the inductor from the 55nm BiCMOS library from ST Microelectronics. The actual inductor is expected to improve the simulation results. A spiral inductor with four turns and 40µm radius is used from the

55nm BiCMOS library from ST Microelectronics, for the large inductor. As it is explained in Section 4.2, the connection point of the inductor to the transistors’ sources is a virtual ground therefore, the large inductor L4 does not operate in high frequency. Since electromagnetic simulations are used to predict the behavior of the devices at high frequencies, it is not necessary for the inductor L4.

Figure 4.6 : Electromagnetic simulation results of the inductor with a 10µm radius [16]

The effects of the back-gate bias in the oscillation frequency, power consumption and output power of the proposed oscillator with 1V VDD are shown in Figure 4.7. 48

Increasing back-gate bias increases the oscillation frequency and the drain efficiency of the oscillator. Also, negative back-gate bias voltage has been used in order to improve the phase noise of the oscillator.

Figure 4.7 : Effects of the back-gate bias on oscillation frequency, power consumption and power efficiency [16]

In Figure 4.8, the effects of the gate width on oscillation frequency, tuning range and power consumption of the oscillator can be seen. The first subplot from the top shows the gate width dependence at different back-gate bias voltages. The middle subplot shows the tuning range of the oscillator depending on the gate width. The tuning range of the oscillator is the difference between the maximum frequency of oscillation which is at

-1V back-gate bias voltage and the minimum frequency of oscillation which is at 0V back-gate bias voltage. And the last subplot shows the power consumption of the oscillator depending on gate width at different back-gate bias voltages. For this simulation, VDD is chosen to be 1V. In order to have a reasonable tuning range and high 49 oscillation frequency, the 45nm process is chosen for this project. For the gate width of the transistor, 26µm has been chosen which was the minimum possible gate width for the oscillator in order to have oscillation. Also, it produced the highest oscillation frequency.

For the transistors that have gate width less than 26µm, the negative resistance of the active component is not enough to start the oscillation.

Figure 4.8 : Effects of gate width on oscillation frequency, power consumption and tuning range of the oscillator [16]

The simulated phase noise at 1 MHz with 0V back-gate bias is -82dBc/Hz. As the back-gate bias goes to -1V the phase noise gradually deteriorates to -76dBc/Hz. The phase noise can be improved by additional circuitry or by reducing the oscillation frequency. Even though the phase noise of the oscillator is a little bit lower than its counterparts; it is enough for short-range, on-off keying communication applications which is the targeted application for the proposed oscillator. 50

Figure 4.9 : Phase noise of the oscillator at different back-gate voltage [16]

Figure 4.10 : Power spectral density of the oscillator at -1V back-gate bias [16]

In Figure 4.10, the power spectral density of the oscillator at -1V back-gate bias voltage is shown. Since the oscillator uses push-push architecture, the oscillator oscillates 51 at the second harmonic frequency. Because of that, power at the frequency oscillation is below 0dB.

4.4 Summary

The frequency of oscillation of the proposed voltage-controlled on-chip oscillator is 245GHz with a 2% tunable oscillation frequency range. The frequency of the oscillation is tuned from the back-gates of the transistors M1 and M2 from 0V to -1V which can be seen in Figure 4.4. The oscillator has a small form factor. The entire oscillator has an area of 0.0108mm2. Also, it can be further improved to 0.0036mm2 by removing the L4 inductor. The L4 inductor is used to improve the phase noise of the oscillator so, it can be removed for less phase-sensitive applications to save the chip area.

Even though the proposed oscillator needs improvement on phase noise for some applications, it would be enough for an on-off keying transmitter which is the intended target. This oscillator is designed to work in a high-frequency RF transmitter with on-off keying modulation for short-range communication. Even though, this design could not reach the required frequency which was around 300 - 400GHz, it can be improved by using custom inductors such that they have smaller inductances. Also, a triple push oscillator design could be explored with the current inductors. However, that would increase the area of the oscillator and reduce the output power. 52

CHAPTER 5 : CONCLUSIONS AND FUTURE WORK

This chapter is intended to summarize and put in context the outcomes of the research project described in this thesis, along with a description of possible future efforts and how it may be possible to further develop the designs presented in this work.

5.1 Conclusions

Most modern conveniences and high-value economic developments today heavily depend on the presence of capable, compact and low-cost computational and communication platforms. At the heart of modern computers and smartphones is the

CMOS technology that can integrate billions of transistors in a single chip to process and store information. As a result, the development of more capable and compact CMOS integrated circuits can have an immediate and large impact on many walks of life.

However, as the end of conventional transistor scaling is imminent and a competitive alternative technology is yet to be formulated, further advances on CMOS engineering must also include better circuit design and creative use of existing transistor architectures.

Consequently, we focused on this thesis on the effective use of the current dominant transistor architecture, known as FinFET, and its advantages can present for very high- frequency circuits and analog applications.

The core of our work has included re-design and optimization of two well-known and efficient oscillator topologies, Colpitts and push-push oscillators, using independent- gate FinFET transistors for mm-wave (100-300GHz) range. Such compact, efficient and tunable oscillators are key to build on-chip wireless networks and other integrated wireless systems in the next decade. Both designs take advantage of independent-gate 53 control in FinFETs and gate-dependent parasitic capacitances to improve tunable characteristics and reduce circuit complexity, which resulted in more compact and efficient oscillators

In more specific terms, the first proposed circuit, the Colpitts oscillator avoids using additional capacitances and transistors by tapping into relatively larger parasitic capacitances and tunable characteristics of the FinFETs. It can reach 167 GHz range with

~3% tunability and phase noise figure -70dBc/Hz. That is acceptable for the simplistic

OOK-transceiver designs. The second push-push oscillator can reach even higher frequencies such as 250 GHz by coupling and phase cancellation of two oscillators with similarly tunable characteristics. Furthermore, the second design also utilizes a more realistic representation of the inductors at the frequency of interest 200-350 GHz by integrating s-parameter representation of the inductor from the 3D electromagnetic solver. Both oscillators have a limited tuning range compared to their counterparts. The main reason for that is neither of the oscillators uses varactors or capacitors in order to reduce the area of the oscillator. The frequency is tuned using the voltage bias applied to the back-gates of the IG-FinFET. Table 5.1 summarizes some of the important characteristics of the proposed circuits and compares them with similar works published in the literature using 65nm MOSFET technology. Clearly, the proposed designs offer a remarkable saving in power and area, due to their compact nature and minimalist design.

However, the IG-FinFETs were adapted into the 65nm RF-CMOS design-kit which is not based on experimental data but it is modeled using a new BSIM-IMG device model. This was done because there are no commercially available vendors or design kits for IG- 54

FinFETs. Since BSIM-IMG does not incorporate all the parasitics in a practical transistor above 100 GHz, the simulated performance metrics are best-case scenarios and they may deteriorate in practical design as much as 50%. Not all models, parasitics, and material parameters used in the current work were optimized for and checked against experiments above 100 GHz. However, even in such pessimistic outcomes, the proposed designs will present a competitive option for oscillator design in RF-CMOS circuit design due to their compact nature. Heat is another factor that might affect our simulation results. In our simulations, the chip temperature is assumed to be constant at 300K. Since the designed oscillators do not have resistors except parasitic loses and the RF output power level is very low, Joule heating is not expected to impact the oscillators` performance. The designed oscillators were intended for NoCs applications which demand extremely short

Table 5.1 : Similar contemporary oscillators

Process fmin(GHz) fmax(GHz) Pin(mW) Area(mm2) Phase noise (dBc/Hz) Ref. 40nm CMOS 529.2 550.8 18 0.15 -69.6 at 1MHz [17]

65nm CMOS 334.6 341.4 1540 3.9 -93 at 1MHz [18]

65nm CMOS 284.5 296.5 325 0.36 -78 at 1MHZ [19]

65nm CMOS 286 290 275 0.285 -87 at 1 MHz [20]

65nm CMOS 258.2 261.8 800 2.3 -78.3 at 1MHz [21]

65nm CMOS 127 140 NA 0.13 -104.9 at 25MHz [22]

65nm CMOS 113.6 118.8 NA 0.21 -85.3 at 1MHz [23]

65nm IG-FinFET 158 162 50 0.0012 -70 at 1MHz [7]

45nm IG-FinFET 245 250 12 0.01 -82 at 1MHz [16]

55 wireless connections. If a higher signal level is required, this aspect must be reconsidered by solving coupled heat and circuit equations.

The designed oscillators are extremely compact and have low energy consumptions. They are a good fit for low power on-chip applications. With the high operating frequencies, they can be used in small distance and high data transmission routers such as the OWN wireless routers.[4] General features of the OWN architecture for many-core processor design are given in Figure 5.1. The colored cores in the figure indicate which wireless routers communicate with one another. And the entire system is assumed to have 1024 cores connected with wired, wireless and optical networking routers in a hierarchical manner. Due to limited bandwidth, the system has only 16 wireless channels, connecting corner routers in different optical networks together, thereby shortening the number of hops to connect distant elements in the network. These channels require wireless routers to operate in unique frequencies. Our oscillators can be coarsely tuned by changing the width of the transistors to produce required carrier frequencies for such routers. 56

Figure 5.1 : Part of OWN router network [4]

5.2 Future Work

The work presented in this thesis may be considered as an example to explore the potential of FinFET for analog/RF circuit engineering in general and tunable oscillator design above 100GHz in particular. Although the state-of-the-art industry-grade design

(Cadence) and simulation (Synopsys TCAD) tools were used along with realistic design- kits from Global Foundries (formerly IBM), future efforts can include additional details and realism by integrating two-port S parameters for the actual antennas and mm-wave waveguides, which must be extracted from 2D/3D electromagnetic simulations. This requires adaption of a smaller 32nm RF-CMOS back-end process from the industry that will describe the geometry/layout of components as it becomes widely available for 57 academic use. When such a detailed process description is available, then it will also be possible to design other key components of the OOK (on/off keying) transceiver including power amplifier (PA), low-noise amplifier (LNA) and envelop detector. This will pave the way to realize an ultra-compact wireless link for on-chip communication that can be built and tested for further refinement.

A number of additional tasks that can be pursued as an extension to this work would include the design of additional oscillators that minimize or eliminate the use of inductors and increase the frequency of operation and tuning range such as cancellation of higher-order harmonics and non-linear transistor characteristics. Despite the likely end of conventional Moore’s scaling in the next few years, there are continual refinements to transistor structure (e.g. graphene or newer III-V on-silicon transistors) and models

(improved quantum/tunneling corrections, self-heating effects, and Harmonics-Balance approximation) that are especially significant for the analog/RF design; Therefore it would be important to repeat and refine the oscillator designs based on these higher-order models, which only makes sense once more accurate process parameters are adapted.

Lastly, it would help if the future simulations also consider local and global chip heating effects for the additional accuracy of the operating conditions of the oscillator characteristics.

58

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APPENDIX A: BSIM MODEL FILE

*** BSIM-IMG Sample Modelcard for NMOS ***

**************************************************************** ** The BSIM-IMG sample modelcard is fitted to BSIM-IMG102.5 ** ** at the end of phase II CMC evaluation. ** **************************************************************** + AGIDL = 95.6e-12 .model nmos1 bsimimg + LAGIDL = 11.01e-15 + TYPE = 1 + BGIDL = 1.1e9 + WELLTYPE = -1 + TNOM = 27.0 + LBGIDL = 0.0 + CHARGEMOD = 0 + EGIDL = 1.042 + CHARGEWF = 0.0 + LEGIDL = -1.0e-3 + RDSMOD = 1 + PGIDL = 890.0e-3 + GIDLMOD = 1 + LPGIDL = 19.40e-3 + IGCMOD = 1 + TGIDL = -4.0e-3 + IGBMOD = 1 + LTGIDL = -96.0e-6 + NBODY = 1.0e22 + AGISL = 95.6e-12 + XL = 0.0 + LAGISL = 11.01e-15 + DLC = 7.0e-9 + BGISL = 1.1e9 + DLCIGS = 4.0e-12 + LBGISL = 0.0 + DLCIGD = 69.78e-9 + EGISL = 1.042 + TOXP = 2.4e-9 + LEGISL = -1.0e-3 + POXEDGE = 1.076 + PGISL = 890.0e-3 + EOT1 = 2.8e-9 + LPGISL = 19.4e-3 + EOT2 = 7.7e-9 + TGISL = -4.0e-3 + EOT1P = 1.092e-9 + LTGISL = -96.0e-6 + TSI = 12.0e-9 + MEXP = 4.0 + LPRWB = 11.0e-3 + AMEXP = -110e-3 + PHIG1 = 4.55 + BMEXP = 1.0 + RSW = 130.0 + PCLM = 5.0e-3 + RDW = 130.0 + APCLM = 9.0e-3 + ARSW = 15.0 + BPCLM = 300.0e-9 + BRSW = 200.0e-9 + PCLMG = 0.0 + RSWMIN = 0.0 + PTWG = 0.0 + RDWMIN = 0.0 + APTWG = 8.0 + PRT = -2.0e-3 + BPTWG = 300.0e-9 + PRWB = 0.0 + PTWGB = 0.0 + PRWG = 0.0 + APTWGB = 0.0 + KBG0PW = 1.25 + BPTWGB = 300.0e-9 + KBG0NW = 1.2 + PTWGB2 = -300.0e-3 + KBG1PW = 0.0 + APTWGB2 = 4.0 + KBG1NW = 0.0 + BPTWGB2 = 300.0e-9 + KBG2PW = 0.0 + PTWGT = 0.0 + KBG2NW = 0.0 + AIGC = 10.99e-3 + BPFACTORPW = 800.0e-3 + BIGC = 281.0e-6 64

+ CIGC = 9.0e-3 + BUA = 40.0e-9 + PIGCD = 0.0 + LUA = 0.0 + AIGS = 7.5e-3 + UA1 = 0.0 + BIGS = 1.104e-3 + UC = -30.0e-3 + CIGS = 133.2e-18 + AUC = -10.0e-3 + CDSC = 2.7e-3 + BUC = 40.9e-9 + CDSCD = 444.1e-12 + UC1 = 0.0 + CBGCBG = 1.2e-3 + UD = 50.0e-3 + CBGCBG0 = 1.4e-3 + UDB = 0.0 + CBGCBG0P = 700.0e-6 + AUDB = 130.0e-3 + CBGCBGP = 600.0e-6 + BUDB = 50.0e-9 + CBGCBGD = 3.1e-3 + UCS = 2.0 + CFS = 1.0e-12 + UCSTE = 0.0 + CGSL = 42.0e-12 + EU = 2.5 + CIT = 19.67e-6 + AEU = 0.0 + DBGNW = 120.0e-3 + BEU = 200.0e-9 + DBGPW = 120.0e-3 + UTL = -100.0e-6 + DROUT = 400.0e-3 + UTE = -1.0 + DSC0 = 0.0 + VSAT = 80.5e3 + DSC1 = 10.0e-9 + AVSAT = 0.0 + DSUB = 200.0e-3 + BVSAT = 300.0e-9 + PHIN = 50.0e-3 + LVSAT = 0.0 + DVT0 = 380.0e-3 + DELTAVSAT = 1.0 + DVT1 = 145.0e-3 + AT = 0.0 + ETA0 = 80.5e-3 + VSATB = 0.0 + ETAB = -1.0e-3 + AVSATB = 0.0 + ETAMOB = 3.1 + BVSATB = 300.0e-9 + K1RSCE = 0.0 + WR = 1.0 + KSATIV = 1.0 + AIGBACC = 15.1e-3 + KT1 = -100.0e-3 + BIGBACC = 0.0 + KT1L = 0.0 + CIGBACC = 60.0e-3 + KT2 = 0.0 + NIGBACC = 1.0 + KT2L = 2.0e-9 + AIGBINV = 4.71e-3 + LINT = 0.0 + BIGBINV = 90.0e-6 + LPE0 = 12.0e-9 + CIGBINV = 5.2e-3 + PDIBL1 = 0.0 + EIGBINV = 1.9 + PDIBL2 = 0.0 + NIGBINV = 7.2 + PVAG = 0.0 + NBG = 5.0e23 + U0 = 43.0e-3 + ALPHA0 = 1.0 + UP = 9.5e-9 + ALPHA1 = 1.0 + LPA = 1.033 + BETA0 = -7.0 + LU0 = 0.0 + IIT = -1.0 + UA = 80.0e-3 + LOVS = 41.0e-9 + AUA = 60.0e-3 + RTH0 = 0.0

65

APPENDIX B: NETLIST FILES

Netlist for cross-coupled oscillator

V6 (net017 0) vsource dc=vdd type=dc

V10 (net026 0) vsource dc=2 type=dc

V3 (net021 0) vsource dc=vbias type=dc

M7 (net6 net017 0 net017) nmos1 w=40u l=45n

M8 (net6 net017 0 net017) nmos1 w=40u l=45n

M6 (net6 net017 0 net017) nmos1 w=40u l=45n

L6 (net8 net6 0) ind_mmw_8m4x0y2z1u nbturns=2.0 d=50.0 w=4.0 lpe=0

C0 (net020 _net0) capacitor c=1p

NPORT8 (net017 0 net020 0) nport interp=linear thermalnoise=yes \

usewindow=yes datafmt=touchstone noisemodel=internal \

file="ind_s11_10u_50ohm_0_GHz.s2p"

NPORT0 (net020 0 net028 0) nport interp=linear thermalnoise=yes \

usewindow=yes datafmt=touchstone noisemodel=internal \

file="ind_s11_10u_50ohm_0_GHz.s2p"

NPORT2 (net020 0 net037 0) nport interp=linear thermalnoise=yes \

usewindow=yes datafmt=touchstone noisemodel=internal \

file="ind_s11_10u_50ohm_0_GHz.s2p"

M0 (net028 net037 net8 net021) nmos3 w=width l=length

M2 (net020 net026 0 net026) nmoscol w=wdt l=length

M1 (net037 net028 net8 net021) nmos3 w=width l=length 66

Netlist for Colpitts oscillator

M3 (_net0 net012 0 net012) nmoscol w=3u l=length

M9 (net011 _net0 net6 net030) nmos1 w=width l=length

M2 (net6 net07 0 net07) nmos2 w=width l=length

V1 (net07 0) vsource dc=vcur type=dc

V3 (net011 0) vsource dc=vdd type=dc

V2 (net030 0) vsource dc=vbias type=dc

L2 (_net0 net011 0) ind_mmw_8m4x0y2z1u nbturns=1.0 d=50.0 w=0.6 lpe=0

V6 (net012 0) vsource val1=1 val0=0 delay=40n rise=1p fall=1p \

period=18.54p type=bit data="p1" rptstart=1 rpttimes=100

67

APPENDIX C: PAPERS CONTRIBUTED DURING THE COURSE OF THIS

DEGREE

• Rohit, Y. Kelestemur, J.C. Runyon S. Kaya, “Development of Capacitive Wearable Patches and Bands for Data Fusion in Complex Physical Activities,” 2019 IEEE International Flexible Electronics Technology Conference (IFETC), Vancouver, BC, Canada, 2019.

• Rohit, Y. Kelestemur, J.C. Runyon S. Kaya, " Wearable Capacitive Patches for Data Fusion Biomedical & Physical Activity," 2019 IEEE 62st International Midwest Symposium on Circuits and Systems (MWSCAS), Dallas, TX, 2019.

• S. Laha, S. Kaya, N. Dhinagar, Y. Kelestemur and V. Puri, "A Compact Continuous Non- Invasive Glucose Monitoring System with Phase-Sensitive Front End," 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS), Cleveland, OH, 2018, pp. 1-4. doi: 10.1109/BIOCAS.2018.8584693

• Y. Kelestemur, S. Laha, S. Kaya, A. Kodi, H. Xin and A. Louri, "Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs," 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, ON, Canada, 2018, pp. 332-335. doi: 10.1109/MWSCAS.2018.8623958

• Y. Kelestemur, S. Laha, S. Kaya, A. Kodi, H. Xin and A. Louri, "mm-Wave tunable colpitts oscillators based on FinFETs," 2017 IEEE 18th Wireless and Microwave Technology Conference (WAMICON), Cocoa Beach, FL, 2017, pp. 1-6. doi: 10.1109/WAMICON.2017.7930274

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