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Formal Specification of Instruction Set Processors and the Derivation Of Abstract HARCOURT EDWIN ALAN Formal Sp ecication of Instruction Set Pro cessors and the Derivation of Instruction Schedulers Under the Direction of Jon Mauney and Thomas K Miller I I I We present two techniques for formally sp ecifying an instruction set pro cessor at the pro grammers view the architecture view and the timing view From the timing sp ecication we show how to derive an instruction scheduler for the pro cessor One technique addresses architecture sp ecication that is the information required to write correct programs At the architectural level we present a functional semantics that captures the prop erty that instructions are functions from pro cessor state to pro cessor state The second sp ecication technique addresses the programmers view of the timing of the pro cessor that is the needed information required to write temp orally ecient programs We present a technique for formally describing at a highlevel the timing prop erties of pip elined sup erscalar pro cessors We illustrate the technique by sp ecifying and simulating a hypothetical pro cessor that includes many features of commercial pro cessors including delayed loads and branches interlocked oatingp oint instructions and multiple instruc tion issue As our mathematical formalism we use SCCS a synchronous pro cess algebra designed for sp ecifying timed concurrent systems Putting our sp ecication to use we show how to construct an instructionscheduler from the sp ecication by deriving appro priate parameters needed for instruction scheduling These parameters include instruction latencies illegal instruction combinations resource constraints and instructions that may b e issued in parallel The Formal Sp ecication of Instruction Set Pro cessors and the Derivation of Instruction Schedulers by Edwin Alan Harcourt A dissertation submitted to the Graduate Faculty of North Carolina State University in partial fulllment of the requirements for the Degree of Do ctor of Philosophy Computer Science Raleigh Approved by Cochair of Advisory Committee Cochair of Advisory Committee Biography Edwin A Harcourt received a BS in Computer Science from the State University of New York at Plattsburgh in In he received an MS in Computer Engineering and in a PhD in Computer Science b oth from North Carolina State University ii Contents List of Figures viii Introduction The Architecture Level Organization Detail vs Timing Detail Static Instruction Scheduling Outline of Dissertation Mathematical Sp ecications and Related Research Hardware Description Languages Formal Sp ecication Languages Sequential Formalisms Formalisms of Concurrency and Time Compiler Co de Generator Generation Languages Resource Requirements A Marion Extension Other Pro cessor Features Summary The Sp ecication Language Zo o Functional ISA Sp ecication Denotational Semantics Semantic Algebras The Semantics of ISAs iii Notation The Syntactic Domain The Semantic Actions The Valuation Function Action Implementation Co de Generation Discussion Instruction Timing Architecture and Organization Delayed Instructions Multicycle Instructions Resource Constraints Multiple Instruction Issue Motivation Functions Dont Work SCCS A Synchronous Calculus of Communicating Systems A Small Example SCCS Syntax Connecting Pro cesses An Algebra of Actions Extensions to SCCS Transition Graphs The Op erational Semantics of SCCS Examples A ZeroDelay and a UnitDelay Wire Logic Gates FlipFlop iv Sp ecifying a Pro cessor Our example micropro cessor Timing Constraints The SCCS Sp ecication Instruction Formats as Actions Dening the Registers Register Lo cking Dening Memory Instruction Pip eline Instruction Issue Arithmetic Instructions Integer Load and Store Instructions The Branch Instruction Interlocked FloatingPoint Instructions FloatingPoint Registers The Fadd instruction Structural Constraints Mo deling Finite Resources Multicycle Floatingp oint Instructions A Normal Form Register Lo cking Resource Requirements Undened Instruction Sequences Summary Multiple InstructionIssue Pro cessors An Integer Float Sup erscalar Instruction Issue An Integer Integer Sup erscalar Data Dep endencies or Data Hazards Sp ecifying Data Hazards v An Integer Integer Float Sup erscalar Simulation The Reactive View Simulation A Simple Example Example An Illegal Instruction Sequence Example A FloatingPoint Vector Sum Instruction Scheduling Instruction Scheduling Constraints Instruction Scheduling Algorithms Deriving Instruction Scheduling Parameters Preliminaries Derivation of Scheduling Parameters The Algorithm Determining Illegal Instruction Sequences A Mo dal Logic for SCCS Using the logic in a pro cessor Determining Possible MultipleIssue Instructions Computing the Resource Usage Functions Particulate Actions and Agent Sorts Resources and Actions Deriving the Resource Usage Functions Summary Conclusions and Future Research Programmers Timing View Instruction Scheduling Future Research vi Interrupts Cache Mo del Verication and Synthesis Formal Metho ds A Example circuits in the Concurrency Workbench A Simple Logic Gates .
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