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Title 10-nm CMOS : a design study on technology requirement with power/performance assessment

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Author Liu, Minjian

Publication Date 2007

Peer reviewed|Thesis/dissertation

eScholarship.org Powered by the California Digital Library University of California UNIVERSITY OF CALIFORNIA, SAN DIEGO

10-nm CMOS — A Design Study on Technology Requirement with

Power/Performance Assessment

A dissertation submitted in partial satisfaction of the

requirements for the degree Doctor of Philosophy

in

Electrical Engineering (Applied Physics)

by

Minjian Liu

Committee in charge:

Professor Yuan Taur, Chair Professor Prabhaker Bandaru Professor Chung-Kuan Cheng Professor Yu-Hwa Lo Professor Deli Wang

2007

The dissertation of Minjian Liu is approved, and it is acceptable in quality and form for publication on paper:

Chair

University of California, San Diego

2007

iii DEDICATION

To my mom Zhou YuYing, my dad Liu DongLin and my husband Yang Yang.

iv TABLE OF CONTENTS

SignaturePage...... iii

Dedication ...... iv

TableofContents ...... v

ListofFigures...... vii

ListofTables ...... viii

Acknowledgments ...... ix

Vita...... xi

Abstract ...... xii

1 Introduction ...... 1 1.1 CMOS Scaling — Reaching the Limit ...... 1 1.2FundamentalLimitingFactors ...... 4 1.2.1 Non-scaling electron thermal voltage ...... 5 1.2.2 Gate-oxidescalinglimit ...... 8 1.3OrganizationofThesis ...... 10

2 BackgroundandMethodology ...... 12 2.1MOSFETScalingTheory ...... 13 2.2LeakageCurrentsinStatic ...... 17 2.2.1 Tunneling through gate insulator ...... 19 2.2.2 Band-to-bandtunneling ...... 21 2.2.3 Source-to-drain direct tunneling ...... 21 2.3ProblemsToBeAddressed ...... 22 2.4Methodology...... 24

3 Short Channel Effect and Threshold Voltage Design ...... 27

v 3.1 Depletion Layer Depth and Gate Dielectric Thickness ...... 30 3.1.1 Properties of high-K dielectrics ...... 32 3.1.2 Choice of high-K dielectric for 10-nm CMOS ...... 33 3.2 Gate Electrode: Metal Gate vs. Poly-Silicon ...... 34 3.3 Doping Profile Design for Threshold Voltage Requirements ..... 38 3.3.1 Retrogradedopingprofile ...... 39 3.3.2 Quantum-mechanicaleffect ...... 42 3.3.3 Threshold voltage lowering by counterdoping ...... 45 3.4LaterallyNonuniformDoping...... 51 3.5 Effect of Source-Drain Junction Depth on Short Channel Effect. . . 55

3.6 Vt LoweringbyForwardBodyBias...... 56 3.7EffectofThickerGateOxide ...... 61

4 Optimization of Gate Overlap and Source/Drain Doping Lateral Gradient 63 4.1 CMOS Performance Metric — Inverter Delay ...... 67 4.2 Optimum Gate Overlap for an Abrupt Source - Drain Profile . ... 69 4.3 The Effect of Source-Drain Doping Gradient on Performance .... 73 4.4 Band-to-Band Tunneling Current ...... 77

5 The Scaling Limit of Power Supply Voltage from Noise Margin Consid- erations...... 86 5.1 Device Assumptions for Noise Margin Study ...... 90 5.2NoiseMarginforCMOSNANDCircuits ...... 90 5.3 Minimum Power Supply Voltage from Noise Margin Considerations . 96

6 Scalingto10nm—Bulk,SOIorDGMOSFETs? ...... 101 6.1SOICMOS...... 103 6.2DGMOSFET ...... 106 6.3 10 nm: Bulk MOSFET is the More Likely Candidate ...... 109

7 Conclusion...... 112

Bibliography...... 115

vi LIST OF FIGURES

Figure 1.1: A brief chronology of the major milestones in the develop- mentofVLSI ...... 2 Figure 1.2: Trends in lithographic feature size, and number of transis- tors per chip for DRAM and microprocessor chips...... 3 Figure 1.3: The scaling trend of CMOS technology node and channel length...... 4

Figure 1.4: History and trends of power-supply voltage (Vdd), threshold voltage (Vt), and gate-oxide thickness (tox) vs. channel length for CMOSlogictechnologies...... 5 Figure 1.5: Measured (dots) and simulated (solid lines) tunneling cur- rents in thin-oxide polysilicon-gate MOS devices. The dashed line indicates a tunneling current level of 1A/cm2 [8]...... 9

Figure 2.1: The band diagram of the channel in an n-MOSFET. The potential barrier is controlled by the gate voltage. When the chan- nel length decreases, the barrier is increasingly affected by the drain voltage especially when the drain is tied at su ...... 15 Figure 2.2: Simplified geometry for analyzing 2-D effects in a short- channel MOSFET. The white area in silicon represents the deple- tion regions where mobile carriers are swept away by the built-in as well as the applied fields of the gate and betwee ...... 16 Figure 2.3: The operation of an inverter. When the gate voltage is switched from zero to Vdd, output node is discharged through n- MOSFET. Therefore n-MOSFET is called a pull-down device. Sim- ilarly, p-MOSFET acts as a pull-up device...... 19 Figure 2.4: Leakage currents of an n-MOSFET are shown in different status. When the FET is ”ON”, the major leakage source is the gate tunneling current. When the FET is ”OFF”, the major three leakage currents are shown in the band diagram...... 20 Figure 2.5: Schematic band diagram of a P-N junction under reverse bias (a) energy-momentum picture for indirect tunneling (b). The minimum tunneling distance is wT,min [25]...... 22

Figure 3.1: Constant scale length λ contours (solid lines) in a tox-Wd design plane, assuming SiO2 or ǫsi/ǫox = 3. The dotted line marks the boundary on which the ideality factor m equals 1.3. The interc 28

vii Figure 3.2: Constant gate-insulator dielectric constant contours in a ti/λ-Wd/λ plane...... 31 Figure 3.3: Band diagram showing polysilicon-gate depletion effects when a positive voltage is applied to the n+ polysilicon gate of a p-type MOScapacitor...... 35 Figure 3.4: The illustration of the three regions for analytically solving scale length when the polysilicon depletion is not negligible. tp is the polysilicon depletion depth, ti is the gate insulator thickness and Wd istheSidepletion ...... 36

Figure 3.5: Scale length λ vs. polysilicon doping concentration Np for different ti, ǫi and normal surface field Es...... 37 Figure 3.6: A schematic diagram showing the low-high (retrograde) step doping profile, x = 0 denotes the silicon-oxide interface ...... 40 Figure 3.7: The structure of extreme retrograde doping profile. For a 10-nm n-type MOSFET, the doping levels are labeled...... 42 Figure 3.8: The drain current vs. gate voltage for 10-nm n-type MOS- FET with extreme retrograde doping profile at drain voltage of 50 mVand1V...... 44 Figure 3.9: An illustration of the doping concentration (a) and band diagram (b) for MOS with uniform doping, extreme retrograde doping and counterdoping in the vertical direction. The surface field, which is the slope of the potential/energy band a ...... 47 Figure 3.10: The structure of 10-nm n-type MOSFET with counterdop- ing profile. The doping type and concentration are labeled in each region. Counterdoping thickness is 3 nm. Source/drain deep junc- tion (14 nm) is assumed. Gate work function is the sam ...... 48 Figure 3.11: The doping profile along the parallel cut 1 nm below the interface...... 49 Figure 3.12: The doping profile along the parallel cut 7 nm below the interface...... 49 Figure 3.13: The doping profile along the perpendicular cut in the middle of the device. The location of x=0 is the gate oxide/silicon interface. 50 Figure 3.14: The drain current versus gate voltage for drain voltage of 50 mV and 1 V respectively. The threshold voltage at low drain bias is 0.28 V which is obtained by linear extrapolation. DIBL is 85 mV/V and subthreshold swing is 100 mV/decade...... 50 Figure 3.15: Schematic doping contours of SUPER-HALO profile.... 51

viii Figure 3.16: The illustration of HALO doping for channel length of 10 nm. HALO pockets of 4-nm are kept laterally on each side next to the source-drain region. The region between the HALO pockets has the same doping concentration as the substrate in ...... 52 Figure 3.17: The electrostatic potential contour of a 10-nm n-MOSFET with HALO doping. The doping profiles are illustrated in Fig- ure 3.16. The bias condition is Vs = 0 and Vg = Vd =1V...... 53 Figure 3.18: Threshold voltages are plotted as a function of the channel length for MOSFETs without HALO doping and with two other HALO doping profiles as shown in Figure 3.16...... 54 Figure 3.19: Threshold voltages versus body bias are plotted with dif- ferentextractionmethods...... 59 Figure 3.20: The electrostatic potential contour for 10-nm MOSFET with forward body bias of 0.5 V. The gate voltage is at 0.33 V whichisthethresholdvoltage...... 60 Figure 3.21: The leakage current of a diode under forward bias condition. The diode under study has the doping concentration same as the source and substrate doping of a 10-nm n-MOSFET...... 60 Figure 3.22: The threshold voltage and the drain-induced barrier low- ering (DIBL) versus channel length for effective oxide thickness (EOT) of 0.4 nm and 0.8 nm. The threshold voltage is for the drain voltage at 1 V. For thicker oxide thickness, the ...... 62

Figure 4.1: The illustration of the optimum gate length as a result of the trade-off between current drive and miller capacitance. (a) shows that the gate is too long and large overlap capacitance degrades theperformance. (c)showsthatthegateis ...... 66 Figure 4.2: The schematic of the 3-stage ring oscillator setup. At each node (n1, n2 and n3), a loading capacitance can be added to mea- sure the loaded delay. The current source is added to provide a pulse signal to “kick” the circuit start ...... 67 Figure 4.3: The node voltages are plotted versus time for three-stage ring oscillator. The period of the oscillation is given by n(τn +τp)= 2nτ where τ =(τn + τp)/2 is the the delay of an inverter...... 68 Figure 4.4: Switching delay of a 3-stage ring oscillator vs. gate overlap for the abrupt S/D doping profile. Open circles are for the intrinsic delay. Asterisks are for the delay with a loading of 20 fF at each stage...... 70

ix Figure 4.5: The illustration of an n-MOSFET with extended gate insu- lator. Below the gate, all dimensions, contacts and doping profiles are the same as those in previous 10-nm MOSFET design. SiO2 is coveredontopofthedevices...... 71 Figure 4.6: The intrinsic delay for CMOS with high-K gate insulator extension as shown in Figure 4.5, as a comparison, intrinsic delays for CMOS without high-K gate extension are also plotted. . . . . 72 Figure 4.7: Drain current vs. gate voltage for σ = 3 nm. The location of S/D (x0) is labeled next to each curve. Increasing S-D separation (more negative x0) leads to reduced Ion and Ioff . The solid line (x = 4.6nm)represe ...... 74 0 − Figure 4.8: Ioff vs. Ion curves for different S/D lateral doping straggles. Each curve is generated by varying the S-D separation...... 75 Figure 4.9: Source doping profiles for different lateral straggles when the off-current is the same as the abrupt 10 nm case. The lateral gradient (LG) is defined as the slope at the point where the doping is1/10ofthepeakdoping...... 76

Figure 4.10: The on-currents (Vds = Vgs = 1V) are plotted vs. the overlap length for source/drain gradient of 0, 3.2, 5.4 nm/decade . 76 Figure 4.11: Intrinsic delay vs. gate overlap length for different S/D lateralgradients(LG)...... 78 Figure 4.12: Switching delay with a load capacitance of 20 fF/stage vs gate overlap length for different S/D lateral gradients (LG)..... 78 Figure 4.13: The electric field (absolute value) contour of a 10-nm n- MOSFET with Vg = Vs = 0 and Vd = Vdd...... 80 Figure 4.14: The band diagram of the region where largest band bending appears in the drain junction. The device under study is shown in Figure 4.13. Electrons are tunneling from the substrate to the drainregion.Thebanddia ...... 81 Figure 4.15: Circuit diagram of a two-input CMOS NAND gate. The transistors are labeled N1, N2 and P1, P2. The bias condition is alsolabeledatthenodes...... 82 Figure 4.16: The electric field contour of 10-nm MOSFET under bias condition of Vs =0.8 V, Vg = 1 V, Vd = 1 V. The stream line shown is perpendicular to the electric field contour and passes through the highest field point of the drain junction...... 83

x Figure 4.17: The band diagram of the region where large band bending appears. The device under study is shown in Figure 4.16. The electron tunneling direction is labeled in each case. In (a), a vertical cutismadealongthec ...... 85

Figure 5.1: The transfer curves of an inverter with Vdd of 1 V and 0.2 V respectively. For each Vdd, Vt is kept at 1/4 of Vdd. The slope of the linear transition region is degraded as Vdd decreases. Noise marginisthelargest...... 88 Figure 5.2: Noise margin for NAND logic circuits with multiple transfer curves depending on different combinations of inputs. In Figure (a), one-gate-switching curve a is the leftmost curve with the lowest transition voltage and all-gates-switching ...... 89 Figure 5.3: The definition and the generation of the maximum low VLmax and the minimum high VHmin signal ...... 92

Figure 5.4: “Eye diagram” for a 3-way NAND gate logic circuit. Vin and Vout are normalized to the supply voltage. Curve A is generated by switching all inputs together. Curve B is generated by switching one input while tying the other two ...... 93

Figure 5.5: The output voltage and Vx are plotted versus input swing for Vdd of 0.4 V. The solid curve is for bottom switching and the dash-dotlineisfortopswitching...... 94 Figure 5.6: Voltage transfer characteristics for different width ratios with fixed Vt. Noise margin is zero for width ratio of 3 (dash- dot lines) but larger than zero for width ratio of 0.6 (solid lines) wheretheleftmostcurveandtheflipp ...... 95 Figure 5.7: For a fixed supply voltage, in this case — 0.4 V, work func- tion is adjusted to reach the zero noise margin condition. Threshold voltageof0.155Visobtained...... 97

Figure 5.8: Minimum supply voltage versus nominal Vt at room tem- ◦ perature (27 C) for 3-way NAND circuits. Vt/Vdd < 1/3 defines the high performance region. The minimum supply voltage is 0.43 V...... 98 ◦ Figure 5.9: Minimum supply voltage versus nominal Vt at 100 C for 3- way NAND circuits. The result obtained at room temperature is also plotted as comparison. Vt/Vdd < 1/3 defines the high perfor- mance region. The minimum supply vol ...... 99

Figure 6.1: The structure of bulk, fully-depleted SOI and DG-MOSFET.102

xi Figure 6.2: The summary of technology requirements of 10-nm bulk MOSFET...... 103 Figure 6.3: Field patten inside of a short channel SOI shows the strong sourceanddraincoupling[60]...... 104 Figure 6.4: The double gate MOSFET structure for 2-D field analysis. 107

Figure 6.5: The normalized gate insulator thickness (ti/λ) vs. the nor- malized depletion width (Wd/λ)...... 108 Figure 6.6: The ultimate DG-MOSFET design...... 109 Figure 6.7: Possible orientations of double-gate MOSFET on a silicon wafer. Type I is a planar structure, Type II and III are vertical structure. Type III is also called FinFET...... 110

xii LIST OF TABLES

Table 3.1: Selected materials and electrical properties of high-K gate dielectrics [33]. RTA means rapid thermal anneal...... 33

Table 5.1: Vt roll-off assumption in the 2-D device simulation...... 90

xiii ACKNOWLEDGEMENTS

I would like to express my deepest gratitude to my advisor, Professor Yuan

Taur for accepting me as his student and giving me the chance to do this work.

This work would not have been possible without Professor Taur. Getting into the semiconductor field is one of the most important opportunities that affect my life deeply. I would not be where I am if not for him.

Many thanks to my committee members, Professor Prabhaker Bandaru, Chung-

Kuan Cheng, Yu-Hwa Lo and Deli Wang for taking their time to participate as committee members, to review my dissertation and give me valuable comments.

I would also like to thank my coworkers as well as my many good friends, in particular, Huaxin Lu, Bo Yu, Wei Wang, Ming Cai and Wei-Yuan Lu. My experiences at UCSD would not have been as enjoyable and rewarding without them. Their inspiration and encouragement helped me tremendously during my study in UCSD. Without them, the journey to my Ph.D would be much more difficult and unbearably lonely.

Last, but not least, I want to express sincere gratitude to my family. Thanks to my husband, Yang Yang, for his patience, support and valued assistance during the course of my graduate study. Thanks to my parents for their un-conditional love and continual support. This dissertation is dedicated to them.

The text of Chapter 4, in part, is a reprint of the material as it appears in “The

xiv Effect of Gate Overlap and Source/Drain Doping Gradient on 10-nm CMOS Per- formance” by Minjian Liu, Ming Cai, Bo Yu and Yuan Taur, IEEE Transaction on

Electron Devices, Dec. 2006. The dissertation author was the primary researcher of this paper.

The text of Chapter 5, in part, is the reprint of the material as it appears in

“Scaling Limit of Power Supply Voltage from Noise Margin Considerations”, by

Minjian Liu, Ming Cai and Yuan Taur, Proceedings of SISPAD, Sep. 2006. The dissertation author was the primary researcher of this paper.

The text of Chapter 6, in part, is the reprint of the material as it appears in

“Scaling to 10 nm, Bulk, SOI or DG MOSFET?”, by Minjian Liu, Wei-Yuan Lu,

Wei Wang and Yuan Taur, Proceedings of ICSICT, Oct. 2006. The dissertation author was the primary researcher of this paper.

xv VITA

2000 B.S. in Materials Science and Engineering Tsinghua University, Beijing, China 2001 M.S. in Materials Science and Engineering University of California, San Diego, USA 2007 Ph.D. in Electrical Engineering (Applied Physics) University of California, San Diego, USA

PUBLICATIONS

M. Liu, M. Cai, B. Yu and Y. Taur, “Effect of Gate Overlap and Source/Drain Doping Gradient on 10-nm CMOS Performance”, IEEE Trans. Electron Devices vol. 53, pp. 3146-3149, Dec. 2006. M. Liu, M. Cai and Y. Taur “The Scaling Limit of Power Supply Voltage from Noise Margin Considerations”, SISPAD, Sep. 2006, pp. 287-289. M. Liu, W. Lu, W. Wang and Y. Taur “Scaling to 10 nm: Bulk, SOI or Double- Gate MOSFETs?”, ICSICT, Oct. 2006. M. Cai, M. Liu and Y. Taur, “Simulation Study of the Noise Figure of nanometer- gate nMOS Transistors near the Scaling Limit”, to be published by Solid State Electronics. B. Yu, H. Lu, M. Liu and Y. Taur, “Accurate Explicit Models for Double-Gate and Surrounding-Gate MOSFETs”, submitted to IEEE Trans. Electron Devices. M. Liu and F. Hellman, “Magnetic and Transport Properties of Amorphous Tb-Si Alloys Near the Metal-Insulator Transition”, Phys. Rev. B. 67, 054401 2003.

FIELDS OF STUDY

Major Field: Electrical Engineering Studies in Applied Physics Professor Yuan Taur

xvi ABSTRACT OF THE DISSERTATION

10-nm CMOS — A Design Study on Technology Requirement with

Power/Performance Assessment

by

Minjian Liu

Doctor of Philosophy in Electrical Engineering (Applied Physics)

University of California, San Diego, 2007

Professor Yuan Taur, Chair

The scaling of CMOS technology has progressed rapidly for three decades, con- tributing to the superior performance and dramatically reduced cost per function for modern integrated circuits. As the CMOS dimension, in particular, the chan- nel length approaches the nanometer regime (< 100nm), however, static power dissipation increases precipitously due to increasing leakage currents arising from quantum mechanical tunneling and electron thermal energy. To extend CMOS scaling to 10 nm while still gaining significant performance benefit, alternative device structures or materials are being studied extensively. This work considers the device design and technology requirements of scaling bulk MOSFET to the

xvii ultimate limit of 10 nm.

For control of short channel effects, the 2-D scale length theory provides a guideline for CMOS device design. A scale length of less than 7 nm is required for 10-nm MOSFET with acceptable short channel effect. High-K dielectric is needed to replace silicon dioxide so that an effective oxide thickness of 0.4 nm can be obtained without inducing detrimental gate tunneling leakage. High body doping level of above 1019 cm−3 is required to control the depletion width to 5 nm.

Metal gate would be needed to replace polysilicon gate to avoid poly-depletion effect. Counterdoping in the surface channel layer is necessary in order to lower the threshold voltage to 0.2 - 0.3 V.

Also studied in this work are optimum gate-to-source/drain overlap length and the effect of source/drain lateral gradient on circuit performance. An inverse source/drain lateral gradient smaller than 3 nm/decade is needed to avoid excessive source/drain series resistance. Regions where the source/drain doping level drops below 7 1019 cm−3 should not be left un-gated. ×

In order to manage the increasing active power due to the increasing integration level, the scaling limit of power supply voltage is studied based on noise margin considerations. Mixed-mode simulation of a three-way NAND gate is used to study the minimum noise margin condition with the threshold roll-off taken into account. It is shown that a minimum supply voltage of 0.5 V is required for high performance CMOS circuits.

xviii 1

Introduction

1.1 CMOS Scaling — Reaching the Limit

In the last thirty years or so, the strongest growth area of the semiconductor industry has been in silicon very-large-scale-integration (VLSI) technology. The sustained growth in VLSI technology is fueled by the continued shrinking of transis- tors to ever smaller dimensions. The benefits of miniaturization — higher packing densities, higher circuit speeds, and lower power dissipation — have been key in the evolutionary progress leading to today’s computers and communication sys- tems that offer superior performance, dramatically reduced cost per function, and much reduced physical size. A brief chronology of the major milestones in the development of VLSI is shown in Figure 1.1.

The first metal-oxide-semiconductor field-effect transistor (MOSFET) using

SiO2 as the gate insulator was fabricated in 1960 [1]. The major breakthrough in

1 2

Figure 1.1: A brief chronology of the major milestones in the development of VLSI

the level of integration came in 1963 with the invention of CMOS (complimentary

MOS), in which both n-channel and p-channel MOSFETs are constructed simulta- neously on the same substrate. Since CMOS circuit has negligible standby power dissipation, engineers have been able to integrate hundreds of millions of CMOS transistors on a single chip and still have the chip readily air-coolable. Advances in lithography and etching technologies have enabled the industry to scale down transistors in physical dimensions, and to pack more transistors in the same chip area. The exponential increase of the integration level has been known as Moore’s law [2]. Such progress, combined with a steady growth in chip size, resulted in an exponential growth in the number of transistors and memory bits per chip. The recent trends and future projections in these areas are illustrated in Figure 1.2. 3

Figure 1.2: Trends in lithographic feature size, and number of transistors per chip for DRAM and microprocessor chips.

Since 1992, Semiconductor Industry Association (SIA) has been publishing road-maps for semiconductor technology [3]. These roadmaps represent a consen- sus outlook of industry trends, taking history as guide. Today, the smallest feature in CMOS transistors, the gate length, is below 100 nm. As shown in Figure 1.3,

65-nm technology is in production and 20-nm channel length (45-nm technology) is under research [4, 5]. 10 nm is expected to be reached in 10 years. This trend leads to exponentially increasing leakage currents due to quantum mechanical tunneling and non-scaling of electron thermal voltage. No emerging devices on the horizon are viable to replace CMOS in a VLSI environment.

In an effort to extend CMOS scaling to beyond the conventional bulk device limit of about 20 nm gate length [6], intense research activities are focused on 4

Figure 1.3: The scaling trend of CMOS technology node and channel length

alternative materials and device structures including high-K gate dielectrics, high mobility strained silicon channel, ultra thin silicon-on-insulator (SOI), and double- gate (DG) MOSFETs [7]. It is therefore appropriate at this time to study compre- hensively the necessary technology requirements for realizing 10-nm CMOS with power/performance assessment. Because of some fundamental limiting factors dis- cussed in the following section, 10 nm is considered to be the ultimate limit of the

CMOS scaling and poses as a design challenge.

1.2 Fundamental Limiting Factors

When the dimensions of MOSFET are scaled down, both the voltage level and the gate-oxide thickness must also be reduced. While the electron thermal 5 voltage (kT/q) is a constant for room-temperature electronics, the ratio between the operating voltage and the thermal voltage inevitably shrinks. This leads to high source-to-drain leakage currents stemming from the thermal diffusion of electrons.

At the same time, the gate oxide has been scaled to a thickness of only a few atomic layers, where quantum-mechanical tunneling gives rise to a sharp increase in gate leakage currents [8]

1.2.1 Non-scaling electron thermal voltage

Figure 1.4: History and trends of power-supply voltage (Vdd), threshold voltage (Vt), and gate-oxide thickness (tox) vs. channel length for CMOS logic technologies.

Figure 1.4 shows the scaling trend of power-supply voltage (Vdd), threshold volt- age (Vt), and gate-oxide thickness (tox) as a function of CMOS channel length [9]. 6

Below 0.1 µm, threshold voltage deviates from the past scaling behavior due to the non-scaling of electron thermal voltage. The subthreshold leakage current can be expressed exponentially as following:

qV I exp( t ) (1.1) off ∝ −mkT where m is body coefficient which is 1.1 to 1.4 typically. The off-state leakage current would increase by about ten times for every 0.1-V reduction of Vt. The standby power constraint requires that the minimum threshold voltage is about

0.2 V at the operating temperature [10].

The saturation of threshold voltage leads to a saturation of the power-supply voltage as well. This is because that the increase of the ratio of Vt/Vdd would degrade performance. For high-performance CMOS, a Vt/Vdd ratio of < 0.3 is desired [11]. More importantly, power supply voltage is reluctant to deviate from its standard level. For the most advanced microprocessors in production today, the supply voltage is still at 1.2 V. The consequence of non-scaled Vdd is the increasing active power of a CMOS chip, given by

2 Pac = CswVddf (1.2)

where Csw is the total node capacitance being charged and discharged in a clock cycle, and f is the clock frequency. As CMOS technology advances, clock frequency goes up. The total switching capacitance is likely to increase as well, as one tries to integrate more circuits into the same or even larger chip area. The active power is increasingly high. The active power of Intel microprocessor Pentium II was 7 only 12 Watts. Pentium 4 was about 50 W in the year of 2000 while the first dual-core microprocessor—Pentium D reached the power level of 115 Watts when it was introduced in 2005. Fortunately, with better parallel architecture design,

Intel’s Core 2 Dual processor—Conroe, launched in July 2006 has 40% less power compared to the Pentium D. Conroe processors are built on 65 nm technology node, which has gate length of 35 nm. When the gate length shrinks one third for

10-nm CMOS, the number of transistors may increase from current 200 million ∼ to a billion. If the power supply voltage is still kept at current 1.2 V, the power above 150 Watts can easily be reached unless major breakthroughs in platform level design appear. In the ultimate scaling limit, voltage below 1 V is desired.

To scale down supply voltage, another limit is set by noise margin. Noise margin is required to maintain the self-consistency of logic signal. From a funda- mental point of view, in binary digital logic, minimum permissible logic swing is the smallest swing that is still large enough to maintain two distinct logic states and it was shown that this level is around 3 4kT/q. However, the minimum − supply voltage increases as the non-linearity of noise margin degrades due to the combination of multiple inputs and threshold voltage variation. As the channel length is scaled down, the threshold voltage variation due to channel length vari- ation or short channel effect becomes more prominent. This degrades the noise margin and therefore limits the power supply voltage scaling. This problem will be studied in Chapter 5. 8

1.2.2 Gate-oxide scaling limit

The saturation of Vdd also means that the field has been gradually rising over the generations. Increasing field leads to the increase of leakage currents, especially the gate insulator tunneling current. The gate-oxide thickness has been decreasing to keep adverse short channel effect under control. As the oxide thickness approaches the physical limit of 1 nm, the thin oxide film is subject to quantum-mechanical tunneling. This leakage is dominated by turned-on n-MOSFETs, in which electrons tunnel from the silicon inversion layer to the positively biased gate. p-MOSFETs have a much lower leakage than n-MOSFETs because there are very few electrons in the p+ polysilicon gate available for tunneling to the substrate, and hole tunneling has a much lower probability. Figure 1.5 is a plot of the measured and simulated thin-oxide tunneling current versus voltage in polysilicon-gate MOSFETs [8]. For the state-of-the-art transistor with 35 nm gate length, the gate oxide is 1.2 nm which corresponds to 100 A/cm2 gate tunneling current at supply voltage of 1 V.

Suppose gate width is ten times of gate length and one chip holds 108 transistors, the gate leakage power is 1.5 Watts. If the gate oxide is scaled by the same ratio as the channel length to 0.4 nm as the channel length reaches 10 nm, the gate leakage currents can be estimated through tunneling equation. In Schr¨odinger equation:

~2 d2ψ + V (x)ψ(x)= Eψ(x) (1.3) −2m dx2 where V(x) is the electron potential, ψ(x) is the wave function, proportional to exp( x/t ) where t is the tunneling distance. This leads to the tunneling current − 0 0 9

ψ(x)2 exp( 2x/t ). According to Figure 1.5, tunneling current increases three ∝ ∝ − 0 orders from tox of 2 nm to tox of 1.2 nm. Another 0.8 nm decreases of tox from 1.2 nm to 0.4 nm means the gate tunneling current being 3 orders higher. Although the area of a single gate scales down 10 times, the total area stays approximately the same as the number of transistors increases. Static power stemming from gate tunneling alone is 1500 Watts, enough to burn the chip down! The gate-oxide limit is considered to be 0.8 nm. To go beyond this limit requires a major breakthrough in terms of new materials and technologies.

Figure 1.5: Measured (dots) and simulated (solid lines) tunneling currents in thin- oxide polysilicon-gate MOS devices. The dashed line indicates a tunneling current level of 1A/cm2 [8]. 10

1.3 Organization of Thesis

This thesis is organized as following:

Chapter 2 reviews research background and presents methodology of this study.

The state-of-art high-performance CMOS technologies with gate length of 35 nm are first introduced. Shrinking bulk MOSFET in the nano-meter region requires a scaling guideline. Several scaling theories are introduced and one of which will be used extensively in this study. A major task of designing a 10-nm MOSFET is to control the leakage currents in standby status so that the standby power is under control. Therefore the possible leakage current sources are discussed. Design considerations and methodologies for advanced CMOS design are presented.

Chapter 3 describes the short channel effect and threshold voltage control. The static power is a major limiting factor of CMOS scaling. To control thermal leakage current, 2-D scale length theory is used as a design guideline of this thesis. The high-K gate dielectric is studied. The choice of gate electrode — metal gate or polysilicon gate is discussed. Ideal threshold voltage between 0.2 to 0.3 V may not be obtained by simply following the scale length theory. Non-uniform doping profile in the vertical direction is needed for adjusting threshold voltage. The application of abrupt counterdoping near the surface is shown to effectively lower the threshold voltage which otherwise is too high due to high electric field at the interface. HALO doping which counteracts the threshold voltage roll-off is required for 10 nm bulk MOSFET design. The forward bias is added as a comparison with 11 the non-body-biased devices. The gate oxide with different thickness is studied to show the limit of scaling to 10 nm.

Chapter 4 studies the optimum gate-to-source/drain overlap and the require- ment of source/drain lateral gradient. The trade-off between overlap capacitance and series resistance leads to an optimization length of gate-to-source/drain over- lap. Series resistance as a result of graded source/drain doping profile plays an important role in CMOS performance. A method which is based on the off-current is developed to study the effect of source/drain doping gradient on performance.

Chapter 5 presents the scaling limit of power supply voltage from noise margin considerations. In order to control the active power, scaling limit of power supply voltage is studied as a result of power and performance trade-off. The non-linearity characteristics of noise margin degrade with threshold voltage roll-off for multiple fan-in logic. The worst case switching condition is defined and minimum power supply voltage is obtained for high performance CMOS logic.

Chapter 6 reviews alternative MOSFET structures — SOI and double-gate

MOSFETs. The scaling guideline and 10-nm design space of SOI and double-gate

MOSFETs are discussed. The technology requirements are compared with that of bulk MOSFET.

Chapter 7 concludes the thesis with some final remarks. 2

Background and Methodology

The best IDSAT vs. IOFF characteristics reported to date in industry is demon- strated by Ranade et. al. [12]. State-of-art high performance CMOS transistors with 35 nm gate length is achieved for 65 nm technology node. The transistor features NiSi metal gate, uniaxial strained silicon channels and 1.2-nm gate oxide.

Due to the implementation of metal gate and strained Si technology, record high drive current was achieved—NMOS IDSAT = 1.75 mA/µm, PMOS IDSAT = 1.06 mA/µm(Vds =1.2 V, with Ioff = 100 nA/µm). Compared with 90 nm technology node (Lgate = 45 nm) [13], the gate length is scaled down while the gate oxide is not scaled to avoid high gate leakage current. The drive current gain is obtained through enhanced channel strain and ultra-shallow junction engineering. The ap- plication of metal gate is to mitigate the gate depletion effect but the near mid-gap work function leads to high threshold voltage. Although the work function of the

NiSi gate can be modulated by doping the polysilicon film prior to Ni deposition,

12 13

Vt variation can be induced with either incomplete or excessive NiSi formation [12].

To further scale down the gate length relies on more advanced technology inven- tions. Before going into the details of 10-nm CMOS design, we first introduce the scaling theory which serves the guideline for our 10-nm CMOS design. Next, leak- age currents stemming from thermal injection and quantum-mechanical tunneling are investigated. At the end of this chapter, several questions to be addressed in this thesis are discussed.

2.1 MOSFET Scaling Theory

For many years, the shrinking of MOSFETs has been governed by the ideas of scaling [14, 15]. The basic idea is to scale the device voltages and the device dimensions (both horizontal and vertical) by the same factor, so that the electric

field remains unchanged. This is called constant-field scaling [14]. Although this constant-field scaling provides a basic guideline to the design of scaled MOSFETs, the requirement of reducing the voltage by the same factor as the physical dimen- sions is too restrictive because of the subthreshold nonscaling and the reluctance to depart from the standardized voltage levels of the previous generations. Over the generations of scaling, the oxide field has been increasing rather than staying constant. To accommodate this trend, more generalized scaling rules have been created, in which the electric field is allowed to increase[16].

However the preceding scaling rules do not tell a designer how short he can make 14 a MOSFET for given doping profiles and layer thicknesses. They only describes how to shrink a known good design. Furthermore, since the build-in potentials are not usually scaled, the rules are inaccurate any way. Empirical relationship was found between the parameters, such as supply voltage, junction depth, oxide thickness and body doping, and the minimum channel length for long-channel

MOSFETs [17]. The proposed empirical relation is:

2 1/3 Lmin = A[xjtox(wx + wd) ] (2.1)

where Lmin is the minimum channel length for which long-channel subthreshold behavior will be observed, A is a proportionality factor, xj is the junction depth, tox is the oxide thickness, and ws + wd is the sum of source and drain depletion depths which depend on the body bias and the doping level. Although this equation allows a more flexible miniaturization than the scaling of all device parameters by the same factor, it is limited to the channel length above 1 µm and oxide thickness above 10 nm. It was a useful summary of the results, but could not give physical insight for CMOS design since this equation is not derived from the field effect.

To find the minimum gate length at each generation of technology, one must analyze the two-dimensional (2-D) field effects inside the MOSFET. Proper control of 2-D effect is needed otherwise the subthreshold leakage current would degrade.

Below threshold voltage, current does not drop immediately to zero. Rather, it decreases exponentially, with a slope on the logarithmic scale inversely propor- tional to the thermal energy kT. This is because some of the thermally distributed 15 electrons at the source of the transistor have high enough energy to overcome the potential barrier controlled by the gate voltage and flow to the drain. The poten- tial barrier is illustrated in Figure 2.1. When the MOSFET is not properly scaled,

2-D effect is significant. This barrier is more controlled by the drain voltage than by the gate voltage which leads to threshold voltage roll-off or drain induced bar- rier lowering. 2-D field effects are normally done numerically using complex 2-D simulation tools, but analytical analysis provides more insight about the minimum channel length [18].

Figure 2.1: The band diagram of the channel in an n-MOSFET. The potential barrier is controlled by the gate voltage. When the channel length decreases, the barrier is increasingly affected by the drain voltage especially when the drain is tied at supply voltage.

The 2-D effect in the subthreshold region is considered in which the free carriers in the channel can be neglected. A rectangle is formed by the boundary of the gate depletion region, the gate electrode, and the source and drain region, as depicted in Figure 2.2 [19]. It consists of a silicon depletion region of thickness Wd and an oxide region of thickness tox. At the interface, the vertical field (Es) obeys the boundary condition, ǫsiEx,si = ǫoxEx,ox, where ǫsi, ǫox are the permittivities of 16

Figure 2.2: Simplified geometry for analyzing 2-D effects in a short-channel MOS- FET. The white area in silicon represents the depletion regions where mobile car- riers are swept away by the built-in as well as the applied fields of the gate and between the substrate and the source and drain. The solution to the electrostatic potential is reduced to that of a 2-D boundary-value problem for the rectangular bounded by heavy dark lines.

silicon and oxide, respectively. For lateral field (Ey) tangential to the interface, the boundary condition is Ey,si = Ey,ox, independent of the dielectric constants.

Two-dimensional effects can be characterized by the aspect ratio of this rectangle.

When the horizontal dimension, i.e., the channel length, is at least twice as long as the vertical dimension, the device behaves like a long-channel MOSFET, with its threshold voltage insensitive to channel length and drain bias. For channel lengths shorter than that, the 2-D effect becomes significant, and the minimum surface potential (ψs) which determines the threshold voltage is controlled more 17 by the drain than by the gate. The characteristic vertical dimension is called scale length. By properly matching the boundary conditions of both components of electric fields at the silicon-insulator interface, one can derive a scale length λ that is a solution to the following equation [18]:

ǫsitan(πtox/λn)+ ǫoxtan(πWd/λn)=0 (2.2)

Since the higher order of λ has negligible effect on the channel potential, only the

first order term λ1 is considered. For further reference, all λ in the rest of the thesis means the first order term. The maximum potential barrier in a MOSFET has a channel length L dependence: exp( πL/2λ) [19], therefore the ratio L/λ ∝ − is a fundamental measure of the strength of the 2-D effect. For the short-channel

Vt roll-off and the drain-induced barrier lowering (DIBL) to be acceptable, the above exponential factor must be much less than 1. This means that the minimum useful channel length is about 1.5-2.0 times λ [11]. Since λ is larger than the oxide thickness (tox) or the depletion width (Wd) depending on whichever is larger, to scale down λ requires the reduction of both tox and Wd. 2-D scale length theory serves as the guideline of our MOSFET design.

2.2 Leakage Currents in Static

With more than 109 transistors per chip, static power is a major factor lim- iting scaling. Besides thermal leakage currents, tunneling currents, as a result of increasing electric field inside decanano-meter MOSFET, are increasing and may 18 become the dominant leakage source. These tunneling currents include the tun- neling current through gate insulator, the source-to-drain direct tunneling and the band-to-band (Zener) tunneling from body to drain. In order to compare the con- tribution of each leakage source to the static power, the MOSFET static status is first considered. The most basic circuit unit in logic is an inverter which con- sists of an n-channel MOSFET and a p-channel MOSFET in series between the power supply terminals (see Figure 2.3). A major attribute of an inverter is that it dissipates power during switching but has negligible standby power dissipation.

But as CMOS is scaled down with increasing leakage current, the static power dissipation is increasingly problematic. When the input gate voltage is Vdd, the output drain node is ground, n-MOSFET is in “ON” state and p-MOSFET is in

“OFF” state. While the gate voltage is switched to ground, output drain node is

Vdd, n-MOSFET is “OFF” and p-MOSFET is “ON”. For each state, the leakage sources are similar for n-MOSFET and p-MOSFET. The following discussions are for n-MOSFET, which can also be applied to p-MOSFET.

For n-MOSFET in the “ON” state, both source and drain nodes are grounded and the gate is at Vdd. The leakage came from the current tunneling from the gate to the channel through the insulator. In the “OFF” state, the source and gate nodes are grounded while the drain is tied at Vdd. Besides the gate insulator tunneling current at the edge of the gate near the drain, there is also subthreshold leakage current, the source-to-drain direct tunneling and the band-to-band tunneling in the drain region. The leakage currents are illustrated in Figure 2.4. Each tunneling 19

Figure 2.3: The operation of an inverter. When the gate voltage is switched from zero to Vdd, output node is discharged through n-MOSFET. Therefore n-MOSFET is called a pull-down device. Similarly, p-MOSFET acts as a pull-up device.

leakage is examined in the following:

2.2.1 Tunneling through gate insulator

Consider a MOS capacitor with an n-type polysilicon-gate and p-type substrate.

When a large positive bias is applied to the gate electrode, electrons in the strongly inverted surface can tunnel into or through the oxide layer and hence give rise to a gate current. When electrons tunnel into the conduction band of the oxide layer, it is called Fowler-Nordheim tunneling [20, 21]. When the oxide layer is very thin, 20

Figure 2.4: Leakage currents of an n-MOSFET are shown in different status. When the FET is ”ON”, the major leakage source is the gate tunneling current. When the FET is ”OFF”, the major three leakage currents are shown in the band diagram.

say 4 nm or less, then instead of tunneling into the conduction band of the SiO2 layer, electrons from the inverted silicon surface can tunnel directly through the forbidden energy gap of the SiO2 layer. This is called direct tunneling. The theory of direct tunneling is more complicated than that of Fouler-Nordheim tunneling, and there is no simple dependence of the tunneling current density on voltage or electric field [22, 23]. The direct tunneling can be very large for thin oxide layers.

Direct tunneling current is important in MOSFETs of very small dimensions, where the gate oxide layers can be as thin as 2-3 nm [24]. The gate tunneling current of thin-oxide MOSFETs was shown in Figure 1.5. To scale down the MOSFET 21 vertical dimensions for short channel effect control, alternative materials have to be used to replace SiO2 to avoid gate-tunneling-leakage-induced high static power in 10-nm CMOS design.

2.2.2 Band-to-band tunneling

When the electric field across a reverse-biased P-N junction approaches 106

V/cm, significant current flow can occur due to tunneling of electrons from the valence band of the p-region into the conduction band of the n-region. A schematic band diagram is shown in Figure 2.5. The band-to-band tunneling poses as a limit to CMOS scaling. In bulk CMOS, a heavily doped and reverse-biased P-N junction exists between the drain of the transistor and the substrate especially when heavy doping (for example, HALO) in the vicinity of source/drain region is used to suppress short channel effect. To study the tunneling current of 10-nm CMOS design, the band diagram should be evaluated. The most sensitive parameter affecting tunneling is the minimum tunneling distance (wT min). As shown in P. M.

Solomon et. al. [25], the tunneling distance is correlated with the tunneling current by comparing the measurement data of PN junction with the simulation results.

2.2.3 Source-to-drain direct tunneling

As CMOS channel length is scaled to 10 nm or below, the question arises is whether source-to-drain direct tunneling is the dominant leakage. In [26], different values of channel length (3 nm to 20 nm) were selected to examine the dependence 22

Ec /e

Ev /e

w T min

E

Ec

q

Ev ΓΧ k

Figure 2.5: Schematic band diagram of a P-N junction under reverse bias (a) energy-momentum picture for indirect tunneling (b). The minimum tunneling distance is wT,min [25]

of source-to-drain tunneling on channel length. It was shown that source-to-drain tunneling is negligible for devices with channel lengths > 10 nm but it begins to dominate the off-state when the channel length shrinks to 3 nm region. Therefore in the 10 nm design study, source-to-drain direct tunneling was not taken into account.

2.3 Problems To Be Addressed

Both the standby power and the active power of a processor chip will increase precipitously below 100-nm technology generation. To extend CMOS scaling to the 23 shortest channel length possible while still gaining significant performance benefit, an optimized design based on new materials and technologies is needed. The trade- off between power and performance is a constant challenge in scaling CMOS to 10 nm. In designing 10-nm CMOS, several problems need to be considered first:

Bulk MOSFET is the mainstream VLSI technology for the last three decades.

The scaling limit is considered to be 20 nm previously, mainly due to the high gate leakage current as the gate oxide is thinning down to its limit. On the other hand, high-K dielectric has been under extensive study. Many dielectrics are shown to be promising candidates. By replacing silicon dioxide with high-K, the electrical thickness of the insulator can be effectively reduced to contain short channel ef- fect while avoiding high gate leakage current. The questions are: Is high-K gate dielectric required for scaling to 10 nm? If so, how thin should it be and how high a dielectric constant should it have?

The implementation of polysilicon gate was a key breakthrough in CMOS tech- nology. However, the poly-gate depletion effect is getting worse as the channel length is scaling down. With the increasing attention toward high-K dielectric, polysilicon gate shows more disadvantages compared to metal gate electrode due to reliability issues and fermi-level pinning. Then the question raised is what kind of gate electrode is needed from both work function/threshold voltage and gate depletion points of view?

As channel length is scaled down, the performance is expected to increase as 24 a result of the decrease in the intrinsic channel resistance. However the extrinsic series resistance does not scale proportionately and is becoming a significant part of the total device resistance. How shallow and highly doped do the source and drain junctions need to be? What kind of doping gradient is accepted for 10 nm

CMOS? Furthermore, for a source/drain doping gradient, is there an optimum gate length exists? If so, what is it and how to define it when the source/drain doping is graded instead of abrupt?

To reduce active power, the power supply voltage needs to be scaled down.

But how low can the power supply voltage and threshold voltage be scaled without running into noise margin problems in logic circuits when tolerances are taken into account?

Finally, silicon-on-insulator and double-gate have been a research focus for many years. They are considered as promising candidates to extend CMOS scaling to 10 nm. Based on the design study of 10-nm bulk MOSFET and other research on SOI and DG MOSFETs, which device structure is more likelyto reach 10 nm

— bulk, SOI or DG MOSFETs?

2.4 Methodology

With the channel length of 10 nm as the major objective of this research, the design of a MOSFET with acceptable short channel effect will follow the 2-D scale length theory by D. Frank [18]. The scale length consists of the thickness and the 25 permittivities of both the depletion region in the channel and the gate insulator.

The choices of gate insulator and channel doping can therefore be made. On the other hand, the realization of these choices depend on the development of process technology. Based on the knowledge of current research on MOSFET process, advanced technologies are assumed. Although these assumptions may be beyond current manufacturing capabilities, they will be required for extending CMOS scaling to 10 nm. Based on the 10-nm MOSFET with controlled short channel effect, threshold voltage is adjusted to lie in 0.2-0.3 V. The design can be verified using 2-D finite-element-size structure editor (MDRAW) and the device simulator

(DESSIS).

A standard mobility degradation model is used to include the effects of impu- rity scattering, surface phonon and surface roughness scattering, and the high field effects [27]. The subthreshold properties are studied using drift-diffusion model.

Quantum-mechanical effect is important when the field normal to the interface is above 106 V/cm. This effect shifts threshold voltage up for another 0.1 to 0.3 V depending on the electric field. The Vt shift can be obtained through theoretical calculation based the relationship of quantum-mechanical surface potential shift with the surface normal field. In the simulator (DESSIS) setup, by introducing

1-D Schr¨odinger equation to the MOSFET channel, IV characteristics can be sim- ulated. 1-D Schr¨odinger equation is the most sophisticated quantization model.

Simulations with this model tend to be slow and often lead to convergence prob- lems. This restricts the application of this model in our study to single device 26 analysis.

The power and performance are evaluated based on the 10-nm CMOS design.

The accurate analysis of the high current status requires calibrated physical trans- port models. In short channel devices, mobility no longer plays a significant role on performance. Furthermore, the electrons experience the combination of velocity saturation and ballistic transport. The drift-diffusion model which is suitable for the subthreshold operation does not give an accurate prediction of the on-current.

On the other hand, it can still be used to examine the relative performance. In the study of the source/drain doping gradient, the inverter delay which is proportional to the drive current is used as a performance metric. Although the absolute value of the on-current can not be obtained, the relative change due to the source/drain series resistance variation can still provide an insight for the source/drain gradient design. 3

Short Channel Effect and

Threshold Voltage Design

Short channel effect is the decrease of the MOSFET threshold voltage as the channel length is reduced. It is especially pronounced when the drain is biased at a voltage equal to that of the power supply (high drain bias) which is known as drain- induced barrier lowering. In this chapter, 10-nm CMOS design considerations are based on the 2-D scale length model [18] which has been introduced in Chapter 2.

The scale length expression is repeated here:

ǫsitan(πtox/λ)+ ǫoxtan(πWd/λ)=0 (3.1)

The solution to the scale length equation 2.2 is plotted in Figure 3.1 in the form of constant-λ contours in a t W design plane. ox − d

In the 2-D scale length theory, a key parameter is the gate depletion width, Wd,

27 28

Figure 3.1: Constant scale length λ contours (solid lines) in a tox-Wd design plane, assuming SiO2 or ǫsi/ǫox = 3. The dotted line marks the boundary on which the ideality factor m equals 1.3. The intercepts represent design points which satisfy both the scale length and the subthreshold slope requirements. within which the mobile carriers (holes in the case of n-MOSFETs) are swept away by the applied gate field. The gate depletion width reaches a maximum, Wdm, at the onset of strong inversion (threshold voltage) when the surface potential (ψs) or band bending is such that the electron concentration at the surface equals the hole concentration in the bulk substrate. This is the standard ψs =2ψB condition, with ψB =(kT/q)ln(Na/ni), where Na is the substrate doping concentration and ni is the intrinsic carrier concentration of silicon. For uniformly doped cases,

4ǫsiψB 4ǫsikTln(Na/ni) Wdm = 2 = 2 (3.2) s q Na s q Na

From equation 3.2, depletion width is inversely proportional to the square root of doping concentration. As a result, the doping concentration increases toward 29 short channel devices, leading to high threshold voltage.

Another key parameter is the oxide thickness which should also be reduced in order to achieve small λ for short channel devices. In addition to the 2-D scale- length requirement, the ratio between tox and Wd must also be kept small in order for the inverse (log) subthreshold current slope [11],

kT ǫ t S = m(ln10) = (1+ si ox )(ln10)kT/q (3.3) q ǫoxWd to be close to the ideal (ln10)kT/q value, or 60 mV/decade at room temperature.

Here m is usually referred to as the ideality factor which measures the gate-voltage swing required per unit of change in the electron potential (or band bending) at the silicon surface. It can be expressed as:

m = ∆Vg/∆psis =1+3tox/Wd (3.4)

for the gate insulator of SiO2.

A reasonable upper limit is tox/Wd = 0.1, or m=1.3, as indicated by the dot- ted curve in Figure 3.1. This gives a long channel inverse subthreshold slope of

80 mV/decade. The intercepts of the dotted curve with the constant-λ con- ∼ tours lie in a region where the vertical fields dominate, and λ W +(ǫ /ǫ )t , ∼ d si ox ox obtained by replacing the oxide region with an equivalent silicon region of thick- ness (ǫsi/ǫox)tox [19]. The design points, or the intercepts, can then be solved as t = (1 1/m)(ǫ /ǫ )λ. This means that for L (1.5 2.0)λ and m =1.3, ox − ox si min ∼ − the required oxide thickness is t L /20 to L /25 [11]. ox ∼ min min 30

3.1 Depletion Layer Depth and Gate Dielectric Thickness

For channel length of L = 10 nm, λ 5 to 6.7 nm leads to t 0.4 to 0.5 ∼ ox ∼ nm and W 5 nm for m = 1.3. The doping profile to achieve W of 5 nm and d ∼ d to control the threshold voltage to 0.2 - 0.3 V will be studied in the next section.

Here the gate insulator requirement is discussed first.

As shown in Chapter 2, SiO2 of 4-5 A˚ cannot be tolerated even for high- performance systems due to the un-acceptably high gate tunneling current. A gate dielectric with a dielectric constant substantially higher than that of SiO2 will achieve a smaller equivalent oxide thickness (EOT) even with a physical thickness

(ti) much larger than that of the SiO2 (tox). The gate tunneling current can be reduced or eliminated using high-K gate insulator. The effective gate oxide thickness is:

ǫox EOT =( )ti (3.5) ǫi where ǫi is the permittivity of the gate insulator and ti is its thickness. The scale- length equation is valid for the high-K gate insulator as well. One simply replaces

ǫox and tox with ǫi and ti:

ǫsitan(πti/λ)+ ǫitan(πWd/λ)=0 (3.6)

The advantage of replacing gate oxide with high-K dielectric can be seen in

Figure 3.2 where constant dielectric constant contours are plotted on the normal- ized gate insulator thickness (ti/λ) vs. normalized depletion width (Wd/λ) plane. 31

Scale length is solved using equation 3.6. For t W , as seen in the lower right i ≪ d region of Figure 3.2, λ W +(ǫ /ǫ ) t . For a given scale length and depletion ∼ d si i × i width requirement, gate insulator with higher dielectric constant can afford larger thickness. As long as ti < Wd (see the region where Wd/λ > 0.5 in Figure 3.2), the scale length is limited by 2ti, i.e. λ > 2ti.

A thick high-K gate insulator not only relieves the tunneling current through gate insulator but also helps mitigate the impact induced by the process variation of gate insulator thickness. However replacing the SiO2 with a material having different dielectric constant is not as simple as it may seem. From thermal stability issues to mobility degradation, the properties of high-K dielectrics will be discussed and the choice of high-K gate for this study will be made.

Figure 3.2: Constant gate-insulator dielectric constant contours in a ti/λ-Wd/λ plane. 32

3.1.1 Properties of high-K dielectrics

In order to replace the SiO2, the high-K material bulk and interface properties must be comparable to those of SiO2, which are remarkably good. Basic mate- rial properties such as thermodynamic stability with respect to silicon, stability under thermal conditions relevant to microelectronic fabrication, low diffusion co- efficients, and thermal expansion match are critical. In addition, charge trapping and reliability issues for the gate dielectrics are particularly important considera- tions.

Thermal stability with respect to silicon is an important consideration, since high-temperature anneals are generally employed to activate dopants in the source/drain as well as the polysilicon gate. Although many binary and ternary oxides are predicted to be thermally stable with respect to silicon [28], recent research on high-dielectric-constant gate insulators have focused primarily on binary metal ox- ides such as Ta2O5, TiO2, ZrO2, HfO2, Y2O3, La2O3, Al2O3, and Gd2O3 and their silicates [29]. The dielectric constant of these materials generally ranges from 10 to 40, which is about a factor of 3 to 10 higher than that of SiO2. Leakage current reduction from 103 to 106 , in comparison with SiO of the same electrical × × 2 thickness, is generally achieved experimentally for high-K gate dielectrics [30].

A large silicon-to-insulator energy barrier height is desirable because the gate direct-tunneling current is exponentially dependent on the (square root of the) barrier height [31]. In addition, hot-carrier emission into the gate insulator is also 33

Table 3.1: Selected materials and electrical properties of high-K gate di- electrics [33]. RTA means rapid thermal anneal.

Dielectric Dielectric Bandgap Conduction Leakage Thermal sta- constant (eV) band offset current bility w.r.t. (bulk) (eV) reduction silicon (MEIS w.r.t. SiO2 data) ◦ SiO2 3.9 9 3.5 N/A >1050 C ◦ Si3N4 7 5.3 2.4 >1050 C 2 3 ◦ Al2O3 10 8.8 2.8 10 -10 1000 C, RTA ∼ 2 3× ∼ Ta2O5 25 4.4 0.36 10 -10 Not thermody- ∼ × namically sta- ble with silicon 4 5 Y2O3 15 6 2.3 10 -10 Silicate forma- ∼ × tion 4 5 ◦ HfO2 20 6 1.5 10 -10 950 C ∼ 4 5× ∼ ◦ ZrO2 23 5.8 1.4 10 -10 950 C ∼ ∗ × ∼ ZrSiO4 6 1.5 ∗ HfSiO4 6 1.5

related to the same barrier height [32]. The high-K material should therefore not only have a large bandgap, but also have a band alignment which results in a large barrier height. Table 3.1.1 compares the properties of the common high-K gate dielectrics reported in the literature.

3.1.2 Choice of high-K dielectric for 10-nm CMOS

HfO2 has emerged as one of the most promising high-K gate dielectric [34].

The effective oxide thickness (EOT) of HfN/HfO2 gate stack has been successfully scaled down below 10 A.˚ The excellent leakage and long term reliability even after

1000◦C RTA have been demonstrated [35]. To further scale the EOT to 4 to 5 A˚ 34 faces severe challenges. It is not yet clear if a satisfactory solution exists. Due to lower barrier height compared to SiO2, the physical thickness of high-K dielectric is limited to 2 nm, otherwise high gate leakage current will be induced. The interfacial layer between the high-K dielectric and Si substrate has to be nearly eliminated. Dielectric constant of HfO2 is about 20 which leads to 0.4 nm EOT for 2-nm physical thickness. This forms the initial assumption for 10-nm CMOS design. Furthermore, EOT of 0.8 nm will be considered and the performance loss will be studied.

3.2 Gate Electrode: Metal Gate vs. Poly-Silicon

The use of polysilicon gates is a key advance in modern CMOS technology, since it allows the source and drain regions to be self-aligned to the gate, thus eliminats parasitics from overlay errors [36]. However, the poly-gate depletion effect is especially pronounced in the short channel devices.

Figure 3.3 shows the band diagram of an n+-polysilicon-gated p-type MOS capacitor biased into inversion. Since the oxide field points in the direction of accelerating a negative charge toward the gate, the bands in the n+ polysilicon bend slightly upward toward the oxide interface. This depletes the surface of electrons and forms a thin space-charge region in the polysilicon layer which lowers the total capacitance. Besides the degradation of on-current, poly-depletion width will also degrade the short channel effect which can be understood through the scale length 35

Figure 3.3: Band diagram showing polysilicon-gate depletion effects when a posi- tive voltage is applied to the n+ polysilicon gate of a p-type MOS capacitor

theory.

For short channel devices, when the poly-depletion effect is prominent, the scale length should be solved from the three-region model instead of the two- region model. The three regions are illustrated in Figure 3.4 in vertical direction: the silicon depletion width (Wd), the insulator thickness (ti) and the polysilicon depletion depth (tp). By equalizing the depletion charge on both sides of the gate insulator, poly-gate depletion depth tp can be expressed as:

Esǫsi tp = (3.7) qNp

where Es is the surface electric field normal to the interface, q is the electron charge and Np is the doping concentration of polysilicon gate.

6 For a 10-nm MOSFET, Es can be easily raised up to 10 V/cm. Since polysilicon 36

Figure 3.4: The illustration of the three regions for analytically solving scale length when the polysilicon depletion is not negligible. tp is the polysilicon depletion depth, ti is the gate insulator thickness and Wd is the Si depletion width. The corresponding permittivity is labeled.

20 −3 doping level can not go above 10 cm due to grain boundary issues, tp of at least

1 to 2 nm is induced depending on the surface field — comparable to the gate dielectric thickness. As a result, scale length increases and short channel effect degrades. The scale length can be solved analytically from the three-region scale length equation:

ǫi 1 1 2 tan(πtp/λ)tan(πti/λ)tan(πWd/λ) = tan(πWd/λ)+ tan(πti/λ) ǫsi ǫsi ǫi 1 + tan(πtp/λ) (3.8) ǫsi

With the assumption of Wd = 5 nm, the first order scale length λ is plotted vs. the doping concentration of polysilicon (Np) for different combinations of ti, ǫi and

20 −3 the normal surface field Es, as shown in Figure 3.5. Below Np = 10 cm , scale 37 length increases rapidly with decreasing polysilicon doping or increasing surface

field. Since the scale length can easily go beyond 7 nm according to Figure 3.5, the short channel effect becomes worse. Therefore polysilicon gate is not suitable for 10-nm CMOS design.

10 ti=2nm, ε =5ε ,Es=2 MV/cm i ox ti=2nm, ε =5ε ,Es=1 MV/cm i ox 9 ti=1nm, ε =2ε ,Es=2 MV/cm i ox ti=1nm, ε =2ε ,Es=1 MV/cm i ox 8 (nm) λ 7

6 20 21 22 23 log(N cm−3) p

Figure 3.5: Scale length λ vs. polysilicon doping concentration Np for different ti, ǫi and normal surface field Es.

A metal gate not only eliminates the polysilicon depletion effect, it also has several other advantages. High-K gate dielectric is required for scaling to 10 nm.

If polysilicon gate is used, the dielectric film must be able to withstand rapid thermal anneals up to at least 950◦C for dopant activation in the polysilicon gate.

Using a low-temperature process, the employment of a metal electrode relieves many thermal stability issues. For example, high threshold voltage will be induced due to the Fermi-level pinning at the polysilicon/metal-oxide interface [37, 38]. 38

The engineering of the high-K/Si as well as metal/high-K interfaces is identified as the most important factor for achieving EOT 1 nm with good performance ≪ and reliability [39].

3.3 Doping Profile Design for Threshold Voltage Require-

ments

From a device design point of view, the most important consideration is the control of threshold voltage which is related to the gate electrode work function

φm and the channel doping profile:

Qd Vt = Vfb +2ψB + − (3.9) Cox where Qd is the depletion charge and Vfb is the flat band voltage which equals to the work function difference between the metal gate and the silicon substrate [11]:

V = φ φ (3.10) fb m − s

In Equation 3.9, the interface charge is not considered since it is usually negli- gible in model VLSI technology. For short channel bulk MOSFET, heavy doping is needed to control short channel effect but this leads to large depletion charge

Q . For n-MOSFET, φ is located at the Si valence band. In order to lower V , | d| s t the ideal metal work function φm should be located above Si conduction band.

Similarly for p-MOSFET, metal work function below Si valence band is needed.

Unfortunately there is no known metals that have such work functions, the metal 39 work function is assumed to be located at the conduction band and valence band of Si for n-MOSFET and p-MOSFET respectively.

The minimum scale length of 6.7 nm was obtained for 10 nm channel length with L =1.5λ requirement. For EOT W , ≪ d

λ W +3EOT (3.11) ∼ d

This leads to the depletion width Wd of 5.5 nm for EOT =0.4 nm.

As shown in equation 3.2, Wd is inversely proportional to the (square root of) doping concentration in the uniform case. Doping concentration in the mid-1019 or higher is therefore required. Threshold voltage in uniform doping case is:

√4ǫsiqNaψB Vt = Vfb +2ψB + (3.12) Cox

Depletion width and threshold voltage are coupled through the doping con- centration (Na), and therefore cannot be varied independently for given Vfb and tox. For narrow depletion width required by 10-nm CMOS design, the doping con- centration of mid-1019 cm−3 leads to high threshold voltage. This issue can be addressed through nonuniform channel doping profile.

3.3.1 Retrograde doping profile

With the increase of body doping to control short channel effect, low-high

(retrograde) doping profile has been introduced as CMOS is scaled below 0.2 µm.

The doping profile of low-high doping is shown in Figure 3.6. Such a profile is 40 formed using higher-energy implants that peak below the surface. It is assumed that the maximum depletion width extends into the higher-doped region. The

Figure 3.6: A schematic diagram showing the low-high (retrograde) step doping profile, x = 0 denotes the silicon-oxide interface

threshold voltage in this case is reduced as a result of depletion charge reduction:

qNaWd q(Na Ns)xs Vt = Vfb +2ψB + − (3.13) Cox − Cox

The third term represents the contribution from the depletion charge which de- creases as Ns is reduced. Ns is zero in the extreme retrograde case. To further lower the threshold voltage through depletion charge reduction, Ns could be neg- ative which corresponds to counterdoping. For now, retrograde doping profile is

first considered. As a result of the depletion charge reduction, the surface electric

field Es is lowered according to Gauss’s Law:

E = Q /ǫ (3.14) s − d si 41

On the other hand, the maximum depletion width (long-channel) Wd is in- creased compared to the uniform case,

2 2ǫsi q(Na Ns)xs Wd = (2ψB + − ) (3.15) sqNa 2ǫsi

In order to lower the threshold voltage without increasing the depletion width, consider the extreme retrograde case where N = 0 and x W . In order to s s ≈ dm ′ meet the condition of x W , the concentration beyond x must be raised to N s ≈ dm s a ′ so that x (4ǫ ψ /qN )1/2. In this case, the threshold voltage can be reduced s ≫ si B a to half of that in the uniform case and can be expressed as:

ǫsi/xs Vt = Vfb +2ψB + 2ψB (3.16) Cox

Now consider a 10-nm n-MOSFET with Wd = 5 nm, the extreme retrograde

21 −3 doping requires the doping concentration below xs to be about 10 cm . The structure of such n-type MOSFET is shown in Figure 3.7 with the doping profiles labeled. High-K gate dielectric with effective oxide thickness of 0.4 nm is assumed.

Metal gate with work function same as n+ Si is applied in the simulation. The doping profile in each region is assumed to be uniform and infinitely abrupt. For

EOT of 0.4 nm and Wd = xs = 5 nm, the threshold voltage is about 0.26 V according to Equation 3.16. This value may seem to be a suitable one for high- performance CMOS operation, but it in fact is a under-estimated result because the quantum-mechanical Vt shift was not taken into consideration. 42

12 nm

Metal Gate







ǫ ǫ







i =5 ox







t nm



























i =2



























5nm zero









Source doping









Drain



















20 14nm









1.5 1020 10 nm









1.5 10









21









×









×(n) 1 10 (p)









(n)









×

~ ~ 6 1019 (p) ×

Figure 3.7: The structure of extreme retrograde doping profile. For a 10-nm n-type MOSFET, the doping levels are labeled.

3.3.2 Quantum-mechanical effect

As gate voltage applied to a MOSFET is near or above its threshold voltage, a thin inversion layer is formed where carriers are confined in a potential well very close to the silicon interface. The well is formed by the oxide barrier (essentially infinite except for tunneling calculations) and the silicon conduction band, which bends down severely toward the surface due to the applied gate field. Because of the confinement of motion in the direction normal to the surface, inversion-layer electrons must be treated quantum-mechanically as 2-D electron gas [40], especially at high normal fields. Thus the energy levels of the electrons are grouped into 43 discrete subbands, each of which corresponds to a quantized level for motion in the normal direction, with a continuum for motion in the plane parallel to the

5 surface. When the surface electric field Es is larger than 10 V/cm, the subband spacings become greater than kT and the total inversion charge per unit area

QM under quantum mechanical consideration (Qi ) is significantly less than that of the classical case (Qi), which means that additional band bending is required to achieve the same inversion charge per unit area as the classical value. The classical

QM threshold condition, ψs =2ψB, should therefore be modified to ψs =2ψB +∆ψs ,

QM QM 6 where Qi (ψs = 2ψB + ∆ψs ) = Qi(ψs = 2ψB). Beyond 10 V/cm, only the

QM lowest subband is occupied by electrons, and ∆ψs can be expressed as: E QM E0 kT 8πqmd s ∆ψs ln( 2 ) (3.17) ≈ q − q h Nc where E0 is the lowest subband in the valley with twofold degeneracy:

E 9hq s 2/3 E0 = [ ] (3.18) 16√2md where h =6.63 10−34 J-s is Planck’s constant, and m (= 0.92m ) is the effective × d 0 mass of electrons perpendicular to the surface in the lowest subband and m0 is the free electron mass.

QM Knowing ∆ψs , one can easily calculate the threshold voltage shift due to the quantum effect:

QM dVg QM QM ∆Vt = ∆ψs = mψs (3.19) dψs where m = 1+3EOT/Wdm. For a 10-nm MOSFET with extreme retrograde doping as discussed previously, the surface field Es =2ψB/xs is 2.2 MV/cm. According to 44

QM equation 3.17 and 3.19, the ∆ψs is 0.23 V and the quantum-mechanical threshold

QM voltage shift ∆Vt is 0.3 V for m = 1.3. This leads to a Vt of 0.56 V, too high for high-performance CMOS application.

This estimation can be confirmed through simulation. 2-D finite-element sim- ulation tool is used to model the 10-nm MOSFET with extreme-retrograde dop- ing profile. Use the structure shown in Figure 3.7, simulation is performed using drift-diffusion transport with 1-D Schr¨odinger equation added to capture quantum- mechanical effect. The threshold voltage is about 0.54 V. The drain current vs. gate voltage is shown in Figure 3.8.

-2 -3

10 1.5x10

Vds=1V

-3

10

Vds=0.05V

-4

10

-3

1.0x10

-5

10

-6

10

-4

(A/um) 5.0x10 -7

10 ds I

-8

10

-9

0.0 10

-10

10

-0.2 0.0 0.2 0.4 0.6 0.8 1.0

Vgs (V)

Figure 3.8: The drain current vs. gate voltage for 10-nm n-type MOSFET with extreme retrograde doping profile at drain voltage of 50 mV and 1 V. 45

Furthermore, the device doping profile in the simulation is highly ideal. The solid solubility of dopants are limited. Arsenic has the highest solid solubility of about 2 1021 cm−3, but the number of electrically active dopants, which can × contribute free electrons, are much less. The electrical solubility is merely 2 1020 × cm−3 [41]. The anneal after ion-implantation only makes the profile graded. Taken these factors into account, the highest active doping that can be achieved in the substrate is N = 1 1020 cm−3. To maintain depletion width of 5 nm, x of 3 a × ∼ s nm is needed according to equation 3.15. Since the ground plane doping profile can not be achieved in practice, the threshold voltage will be another 0.1 to 0.2

V higher. As a result, alternative approaches are needed to bring the threshold voltage down.

3.3.3 Threshold voltage lowering by counterdoping

Further reduction of Vt can be accomplished by either counterdoping the chan- nel or forward-biasing the substrate. A forward substrate bias also helps improve short channel effects, as it effectively reduces the built-in potential between the source-drain and the p-type substrate. However, forward substrate bias also causes source junction leakage, increases the drain-to-substrate capacitance, and degrades the subthreshold slope and body effect. The possibilities of forward-biasing a 10- nm CMOS will be investigated in Section 3.6. Without the external bias condition added, counterdoping is therefore required to keep threshold voltage in the appro- priate range. 46

Employing counterdoping is to apply a shallow n-type implant for n-MOSFETs, and an n-p junction is formed near the surface. At zero gate voltage, the n-type region is depleted of electrons by the gate field so there is no conduction between the source and the drain. The depletion charge is less than that in the retrograde case, the threshold voltage is therefore lower. As long as the depleted charge Qd is not positive, the electric field points in the direction of accelerating a nega- tive charge toward the gate and surface channel is maintained. When the n-type doping is increased to a point that the depletion charge is positive, the surface

field at threshold is negative and the MOSFET is called a buried-channel device, as inversion first takes place at a point of maximum potential below the surface.

In a buried-channel device, the carriers flow in the region away from the surface, therefore the mobility is improved without the surface roughness scattering. How- ever, the short channel effect is inherently worse than that of a surface-channel device [42]. In 10-nm CMOS design, buried-channel should be avoided and the surface counterdoping should be well controlled.

The effect of counterdoping (both the surface channel and the buried channel) on the surface field is illustrated in Figure 3.9. Doping profiles of uniform, extreme retrograde and counterdoping are shown in Figure 3.9 (a). In order to achieve the same depletion width, the doping concentration below Wd is increased for extreme retrograde and counterdoping profiles. The band diagram of the channel in the vertical direction (x) is plotted in (b). The band bending is 2ψB and the electric

field is proportional to the slope of the energy band. The surface field decreases 47

N , Channel a doping Na

0 x

Ns

(a)

Uniform doping Ec Extreme retrograde 2ψB Counterdoping Buried channel

Ev

(b)

Figure 3.9: An illustration of the doping concentration (a) and band diagram (b) for MOS with uniform doping, extreme retrograde doping and counterdoping in the vertical direction. The surface field, which is the slope of the potential/energy band at the surface in (b), is lowered by reducing the depletion charge. 48 as the doping profile changes from uniform doping to extreme retrograde and to counterdoping. In the buried channel case, the electric field of zero is located below the surface and the surface field changes sign.

12 nm

Metal Gate







ǫ ǫ







i =5 ox







t nm



























i =2

















19



















6 10 (n)









Source × Drain



















20 14nm









1.5 1020 10 nm









1.5 10



















×









×(n)









(n)



















1 1020 (p) × ~ ~ 6 1019 (p) ×

Figure 3.10: The structure of 10-nm n-type MOSFET with counterdoping profile. The doping type and concentration are labeled in each region. Counterdoping thickness is 3 nm. Source/drain deep junction (14 nm) is assumed. Gate work function is the same as n+ Si work function.

By applying counterdoping, the third term in Vt expression (Equation 3.9) decreases due to the surface field reduction. For the same reason, the quantum- mechanical Vt shift is also reduced. Therefore counterdoping has two-fold benefits in terms of lowering the threshold voltage. 49

20

1.8x10 ) -3

20

Source Drain 1.6x10 cm (

20

1.4x10

20

1.2x10

20

1.0x10

19

8.0x10

surface counterdoping

19

6.0x10

19 Doping Concentration Concentration Doping

4.0x10

-0.03 -0.02 -0.01 0.00 0.01 0.02 0.03

Parallel direction at 1 nm below surface (um)

Figure 3.11: The doping profile along the parallel cut 1 nm below the interface.

)

20 Source Drain

-3 1.6x10 cm 20 ( 1.2x10

19

8.0x10

19

4.0x10

n-type

0.0

p-type

19

-4.0x10

19

-8.0x10 Doping Concentration Concentration Doping

-0.03 -0.02 -0.01 0.00 0.01 0.02 0.03

Parallel direction at 7 nm below surface (um)

Figure 3.12: The doping profile along the parallel cut 7 nm below the interface. 50

19

8.0x10 ) surface counterdoping -3

19 cm

( 4.0x10

n-type

0.0

p-type

19

-4.0x10

substrate

19

high doping to control SCE

-8.0x10

20 Doping Concentration Concentration Doping

-1.2x10

0.000 0.004 0.008 0.012 0.016 0.020

Perpendicular direction in the center (um)

Figure 3.13: The doping profile along the perpendicular cut in the middle of the device. The location of x=0 is the gate oxide/silicon interface.

-2

0.0025 10

Vds=1V

-3

10

Vds=0.05V 0.0020

-4

10

0.0015

-5

10

-6

0.0010 10

(A/um)

-7

10 ds

0.0005 I

-8

10

0.0000

-9

10

-10

-0.0005 10

-0.2 0.0 0.2 0.4 0.6 0.8 1.0

Vgs (V)

Figure 3.14: The drain current versus gate voltage for drain voltage of 50 mV and 1 V respectively. The threshold voltage at low drain bias is 0.28 V which is obtained by linear extrapolation. DIBL is 85 mV/V and subthreshold swing is 100 mV/decade. 51

Figure 3.15: Schematic doping contours of SUPER-HALO profile

3.4 Laterally Nonuniform Doping

Process-induced channel length variation causes threshold voltage variation as a result of short channel effects. As CMOS scales down below 0.1 µm, SUPER-

HALO doping which consists of highly nonuniform profiles in both vertical and lateral directions, as shown schematically in Figure 3.15, is introduced. To generate

HALO profile, pockets of high doping regions are implanted after gate patterning so that they are self-aligned to the gate and to the source-drain. It helps shield the gate controlled depletion region from the penetration of source-drain fields.

The HALO doped regions are farther apart for long gates and closer together for shorter gates. The “effective doping” becomes higher toward shorter gates, thus counteracting short channel effect. In the 10-nm CMOS study, 20% channel ± length variation is assumed, therefore the channel length ranges from 8 nm to 12 nm. For the counterdoped MOSFET discussed previously, the threshold voltage 52

12 nm

Metal counterdoping Gate 19







ǫ ǫ 6 10 (n)







i =5 ox ×







t nm



























i =2





































10 nm









Drain









Source









14nm 20 . 20









1.5 10 4nm 4nm









1 5 10



















×









×(n)









(n)



















HALO 1 1020(p) × ~ ~ 6 1019 (p) ×

Figure 3.16: The illustration of HALO doping for channel length of 10 nm. HALO pockets of 4-nm are kept laterally on each side next to the source-drain region. The region between the HALO pockets has the same doping concentration as the substrate in this example. This concentration can be lowered for stronger HALO effect. variation is about 100 mV at drain voltage of 50 mV. This will be aggravated with increasing drain voltage due to the DIBL effect. This roll-off can be mitigated by applying HALO doping profile. In the counterdoped devices, only the highly doped region below the counterdoped region is adjusted to create HALO effect.

A simplified treatment is to have HALO pocket of 4 nm in lateral direction on each side next to the source-drain region. An example of a 10-nm MOSFET with

HALO profile is shown in Figure 3.16. The gate-to-source-drain overlap is kept at 1 nm/edge and other device parameters are kept the same as previous design.

The two HALO pockets are pulled apart as the channel length increases. Since 53 the region between HALO pockets has much lower doping compared to the HALO pockets, the “effective doping” concentration is lowered with increasing channel length. The region between the HALO pockets has lateral length varying from 0 to 4 nm as the channel length increases from 8 to 12 nm.

Figure 3.17: The electrostatic potential contour of a 10-nm n-MOSFET with HALO doping. The doping profiles are illustrated in Figure 3.16. The bias condi- tion is Vs = 0 and Vg = Vd = 1 V.

The 2-D finite mesh is applied to simulate the doping profiles of the MOSFET with HALO doping. Simulation with 1-D Schr¨odinger quantization is used. Under the condition of high gate voltage and high drain voltage (Vg = Vd = 1 V), the electrostatic potential contour of a 10-nm n-MOSFET with HALO effect is shown in Figure 3.17. The threshold voltage variation as a function of the channel length 54

0.36

W ithout HALO

0.34

W ith HALO

Stronger HALO

0.32

0.30

0.28

0.26

0.24

0.22 Threshold Voltage (V) Voltage Threshold

0.20

8 9 10 11 12 13 14

Channel Lengh (nm)

Figure 3.18: Threshold voltages are plotted as a function of the channel length for MOSFETs without HALO doping and with two other HALO doping profiles as shown in Figure 3.16. is plotted in Figure 3.18. The threshold voltage is measured at drain voltage of 50 mV using linear extrapolation. As channel length increases from 8 nm to 12 nm, the devices without HALO doping have Vt roll-off of about 100 mV (the line with square symbol). For the example shown in Figure 3.16, the doping concentration of the region between the HALO pockets is the same as the substrate doping —

6 1019 cm−3. The threshold voltage variation in this case is about 70 mV (the line × with circle symbol) for channel length varying from 8 nm to 12 nm. By lowering doping concentration in the center region, the HALO effect becomes stronger which leads to smaller Vt roll-off. For the center region with doping concentration of

2 1019 cm−3, V is almost flat as the channel length is varied from 8 nm to 14 nm × t as shown in Figure 3.18 (the triangle symbol). 55

3.5 Effect of Source-Drain Junction Depth on Short Chan-

nel Effect

Previous device design to control short channel effect has been focused on the channel region. As the device dimension scales down, the field penetration from the source/drain to the channel becomes stronger, therefore the source-drain junction depth becomes a more important role in the short channel effect control. The choice of the source-drain junction depth is important in the 10-nm MOSFET design.

According to the scale length theory, the threshold voltage roll-off ∆Vt is expo- nentially dependent on the L/λ ratio where λ is related to the depletion width and the gate insulator thickness. However, the effect of source-drain junction depth on short channel effect can not be derived from the exponential term. This effect is studied by Sleva S. et al. [43]. It has been demonstrated that the source-drain junction depth enters the pre-exponential term VSCE, as shown below:

∆V = V exp( πL/2λ) (3.20) t SCE −

For source-drain junction depth less than the depletion width, a decrease in short channel effect can be obtained through scaling these junction depths. How- ever, for source-drain junction depth greater than the MOSFET depletion layer width, negligible benefit is obtained from scaling the junction depth. Consider a

10-nm MOSFET, the depletion width is about 5 nm. Junction depth less than 5 56 nm is difficult to control during process. More importantly, high series resistance will be induced. Deep source-drain junction (xj = 14 nm) is the choice of the

10-nm MOSFET design. The variation of this depth has negligible effect on short channel effect.

3.6 Vt Lowering by Forward Body Bias

As we have shown in this thesis, the threshold voltage can not be reduced without limit due to the requirement in standby current and device design. This results in significant slowing down in performance gains because of the increasing

Vt/Vdd ratio. The control of threshold voltage for 10-nm CMOS has been explored from the aspect of gate work function and substrate doping profile in previous study. Substrate bias which is often called as body bias or well bias can provide another dimension of freedom for the threshold voltage control [44, 45]. Body bias control is a good candidate in minimizing the power for CMOS processors and has been studied extensively [46, 47, 48]. To forward bias the body to achieve better Vt/Vdd ratio or to reverse bias the body to achieve low standby leakage becomes appealing as CMOS dimensions continue to scale down. A body bias not only changes the threshold voltage, but also changes the tunneling current and depletion width which affects short channel effect. These effects will be examined in the 10-nm MOSFET design.

Previous threshold voltage equation was derived assuming zero substrate bias 57

(Vbs). A MOSFET is forward biased when Vbs is positive and reverse biased when

Vbs is negative. For uniformly doped long-channel MOSFETs, low drain threshold voltage can be derived with body bias taken into account [11]. The expression is shown here:

2ǫsiqNa(2ψB Vbs) Vt = Vfb +2ψB + − (3.21) p Cox

This equation shows that the effect of the reverse substrate bias (Vbs < 0) is to widen the bulk depletion region and raise the threshold voltage. The short channel effect degrades since the scale length increases with the depletion width. However, the subthreshold slope is expected to improve as a result of the smaller body effect.

Reverse body also enhances the band-to-band tunneling current. The forward body bias has the opposite effect. It lowers the threshold voltage and therefore increases the thermal leakage current [50], but the band-to-band tunneling current is relieved at the drain junction. The depletion width decreases which leads to better short channel control. The forward body bias is preferable in the aspects of extending bulk CMOS scaling. However, forward body bias also induces degraded subthreshold slope.

We have shown that counterdoping is required in order to lower the thresh- old voltage induced by high body doping. The counterdoping profile should be in mid 1019 cm−3 or higher and highly abrupt, otherwise the depletion width in- creases. Instead of applying counterdoping, forward body bias is applied to lower the threshold voltage for a 10-nm CMOS with retrograde doping profile. 58

2-D simulation with 1-D Schr¨odinger quantization is used to study the effect of body bias. The n-MOSFET with ground plane doping profile as shown in Fig- ure 3.7 is used. Threshold voltages are linearly extrapolated from the Ids vs. Vgs curves for forward body bias ranging from zero to 0.5 V. With a forward body bias of 0.5 V, the electrostatic potential contour is plotted at threshold voltage con- dition as shown in Figure 3.20. The electrostatic potential shift across the drain junction is reduced. The threshold voltage vs. forward body bias is plotted as the asterisk symbol in Figure 3.19. The effect of body bias on threshold voltage lies in two aspects. One is the electrostatic potential change which alters the depletion charge term in Equation 3.21. The other is the change of surface field which leads to the change in quantum-mechanical Vt shift. Both effects lead to the lowering of threshold voltage. To differentiate the two aspects, the threshold voltage (clas- sical Vt) is also extrapolated from simulation which does not include quantization model. Classical Vt is plotted as the open circle symbol in Figure 3.19. The in- crease of the threshold voltage due to quantum-mechanical effect is calculated from

classical QM Equation 3.19. The total threshold voltage (Vt + ∆Vt ) is shown as the open triangle symbol in Figure 3.19. Compared to the direct simulation result ( ), ∗ this threshold voltage (a) is very close, only 10-20 mV lower.

For a ground plane doping profile, the threshold voltage is still above 0.3 V even with a forward body bias of 0.5 V. To further increase the body bias may lead to two problems, one of which is the increase of the source-to-substrate leakage. To study the leakage current as a function of the forward bias, a diode is designed 59

0.6

Classical V

t

classical

V +QM V shif t

t t

0.5 V obtained f rom QM simulation

t

0.4

0.3

0.2 Threshold Voltage (V) Voltage Threshold

0.1

0.0 0.1 0.2 0.3 0.4 0.5

Vbs (V)

Figure 3.19: Threshold voltages versus body bias are plotted with different extrac- tion methods. using 2-D simulation tool. The n/p-region of the diode has about the same doping profile as the source and substrate of the 10-nm MOSFET designed in this study.

As shown in Figure 3.21, a forward body bias of 0.6 V leads to the leakage of 0.1

A/cm2, close to 3 nA/µm2 a value given by [49]. Compared to the source-to-drain thermal leakage current, this is small enough to ignore as long as the forward body bias is below 0.8 V according to Figure 3.21. Another concern induced by increased forward bias is the increase of the junction capacitance. As shown in Keshavarzi et. al. [50], forward body bias above 0.5 V leads to the degradation of performance as a result of high junction capacitance. It is a common practice not to use forward body bias above half a volt. 60

Figure 3.20: The electrostatic potential contour for 10-nm MOSFET with forward body bias of 0.5 V. The gate voltage is at 0.33 V which is the threshold voltage.

n(1.5E+20) p(6E19)

n(1.5E20) p(1E20)

10000

n(2E20) p(6E19)

) 100 -2

1 A/cm (

0.01

1E-4

1E-6 Current density

1E-8

1E-10

0.0 0.2 0.4 0.6 0.8 1.0

Forward bias (V)

Figure 3.21: The leakage current of a diode under forward bias condition. The diode under study has the doping concentration same as the source and substrate doping of a 10-nm n-MOSFET. 61

As have discussed previously, the ground plane doping profile can not be ob- tained in 10-nm MOSFET due to the limitation of electrically active doping con- centration. A more realistic design with extreme retrograde doping profile leads to a higher threshold voltage for the same depletion width. Therefore forward body bias is not enough to lower threshold voltage in the region of 0.2 to 0.3 V and counterdoping profile is required for high-performance CMOS application.

3.7 Effect of Thicker Gate Oxide

The requirement of 0.4 nm EOT is demonstrated for 10-nm CMOS according to the scale length theory. The physical thickness limit of SiO2 is predicted to be

0.8 nm — twice the thickness we previously studied. In this section, the gate oxide thickness is increased to 0.8-nm EOT without changing the design in the channel.

Several issues will be considered: what happens to the threshold voltage when the scale length is increased about 1.2 nm which is less than 20%? Another question is how much impact this increase has on the short channel effect, such as DIBL and subthreshold slope?

The substrate doping is 1020 cm−3 with counterdoping of 6 1019 cm−3 and x × s of 3 nm. The threshold voltage increases from 0.3 V to 0.42 V at low drain bias

(Vds = 50 mV). The DIBL increases from 80 mV/V to 220 mV/V. The threshold voltage roll-off (measured at high drain voltage of 1 V) along with DIBL as a function of the channel length is plotted in Figure 3.22. The increase of threshold 62

EOT=0.4 nm

0.50 350

EOT=0.8 nm

300 0.45 DIBL (mV/V) DIBL

250 0.40

200

0.35

150

0.30 ThresholdVoltage (V)

100

0.25

50

0.20

8 10 12 14 16

Channel Length (nm )

Figure 3.22: The threshold voltage and the drain-induced barrier lowering (DIBL) versus channel length for effective oxide thickness (EOT) of 0.4 nm and 0.8 nm. The threshold voltage is for the drain voltage at 1 V. For thicker oxide thickness, the threshold voltage is high and the DIBL is large compared to the thinner oxide thickness. voltage may be addressed by applying heavier surface counterdoping. The larger

DIBL due to the degraded short channel effect is not acceptable. Another effect of the thicker gate oxide is that the on-current drops about 50% due to the gate capacitance decrease. Scaling down below the gate oxide thickness of 0.8 nm is needed in order to have 10-nm CMOS short channel effects under control. This justifies the previous choice of the high-K gate dielectric which can help the scaling down of the gate insulator without large gate tunneling current. 4

Optimization of Gate Overlap and

Source/Drain Doping Lateral

Gradient

As the channel length is scaled down, the performance of CMOS is expected to increase as a result of the decrease in the intrinsic channel resistance. However, the extrinsic series resistance does not scale proportionately and is becoming a significant part of the total device resistance [51]. Performance degrades with more graded source/drain. The gate-to-source/drain overlap also plays an important role in the device performance. High series resistance can be induced when the channel is under-gated, i.e., part of the channel which is next to the source/drain region is not gated. On the other hand, too much gate overlap leads to high overlap capacitance which also degrade the performance. Therefore to optimize the gate-

63 64 to-source/drain overlap length and to find the requirement of the source/drain lateral gradient is needed for 10-nm MOSFET design.

Although traditionally, a minimum and positive gate overlap length is consid- ered necessary to maintain performance, underlapped devices have attracted a lot of attention recently. One motivation of the underlapped device is to avoid the adverse short channel effects by shrinking the gate length without reducing the source(S)-drain(D) distance. An example of a 16-nm underlapped device design where the channel length is in fact 40 nm is shown [52]. In [53], 2-D quantum mechanical simulation is performed. The gate length of 16 nm is fixed with the metallurgical channel length varying from 8 nm to 40 nm. The study shows that the optimum gate-to-source/drain nonoverlap length is 12 nm, corresponding to the longest channel length (40 nm) under study. This is a result of the effectively- increased channel length in the underlapped devices where the short channel effect gets relieved. The effect of the gate overlap/underlap is also studied previously by varying the gate length for a fixed metallurgical channel length in [54]. The metallurgical channel length is fixed at 16, 24 and 36 nm respectively. Minimum switching delay was obtained under non-overlapped conditions for channel length of 24 nm and 36 nm. However, a closer look at this research shows that the body doping is only 2 1018 cm−3 which corresponds to a depletion width of 25 nm. × According to the scale length theory (λ

The methodology of this work is to fix the channel length and vary the gate length to obtain the optimum performance. This is illustrated in Figure 4.1 show- ing the trade-off between the current drive and the miller capacitance. As shown in Figure 4.1 (a), the large gate can guarantee good gate electrostatic control and hence on-state current, but the excessive miller capacitance will degrade the switching performance. On the other hand, if the gate length is reduced too far as shown in Figure 4.1 (c), high series resistance induces low current drive. This trade-off leads to an optimum gate length as illustrated in Figure 4.1 (b). The short channel effect does not change while the gate length is varied, therefore the gate overlap is studied exclusively.

As for the channel length, it is well defined when the source-drain doping profile 66

Figure 4.1: The illustration of the optimum gate length as a result of the trade-off between current drive and miller capacitance. (a) shows that the gate is too long and large overlap capacitance degrades the performance. (c) shows that the gate is too short and the current drive is low. The trade-off leads to (b) the optimum gate overlap length.

is abrupt. The channel length is the distance defined by the doping edge of source- drain, or the metallurgical channel length. But when the source/drain doping is laterally graded, metallurgical channel length is not a relevant parameter [56] [51] since it has no direct effect on the current flow. The effective channel length is a measure of how much gate-controlled current a MOSFET delivers, therefore is defined as the distance where the current flow stays near the surface. It can be extracted from electrically measured terminal currents using channel-resistance method or shift-and-ratio method [51]. In order to fix the effective channel length while the source-drain lateral gradient is varied, a fixed off-current is used in this work for adjusting the distance between the graded source and drain regions. The effect of gate overlap is studied for each S/D gradient as the two effects are strongly coupled to each other [57] [58]. 67

Figure 4.2: The schematic of the 3-stage ring oscillator setup. At each node (n1, n2 and n3), a loading capacitance can be added to measure the loaded delay. The current source is added to provide a pulse signal to “kick” the circuit start.

4.1 CMOS Performance Metric — Inverter Delay

The performance of 10-nm CMOS’s is investigated by using the three-stage ring oscillator in the mixed-mode simulation as shown in Figure 4.2. At each node, a loading capacitor can be added to simulate the wiring capability of an inverter.

When the loading capacitance is zero, intrinsic delay is obtained. Loaded delay is measured for non-zero loading. The wave form of the voltage at each node is plotted in Figure 4.3. The sustained oscillation is a result of strong positive feedback due to the voltage gain of each inverter stage. The period of the oscillation is given by n(τn + τp)=2nτ, where n is the number of stages (three in this study) and

τn, τp are inverter delays per stage for rising and falling inputs, respectively. The width ratio of n-MOSFET and p-MOSFET is chosen to be 1:1.7 so that the current drive is balanced for n- and p-MOSFET and the pull-down delay equals the pull-up delay, i.e., τn = τp = τ. As shown in Figure 4.3, the period equals 6τ. 68

1.0

node1

node2

0.8 node3

0.6

6

0.4 Node Voltage (V) Voltage Node

0.2

0.0

-11 -11 -10

0.0 4.0x10 8.0x10 1.2x10

Time (sec)

Figure 4.3: The node voltages are plotted versus time for three-stage ring oscillator. The period of the oscillation is given by n(τn + τp)=2nτ where τ =(τn + τp)/2 is the the delay of an inverter.

The MOSFET under study is the 10-nm MOSFET with gate oxide EOT of 0.4 nm, metal gate and surface counterdoping. P-MOSFET shares the same design as the n-MOSFET except with the dopant type reversed and with a p+ Si gate work function. The off-current is the same while the on-current is lower due to the lower hole mobility. HALO doping is not applied in this study. The parasitic capacitance due to the gate fringing field is simulated by covering the gate with a

SiO2 cap layer. 69

4.2 Optimum Gate Overlap for an Abrupt Source - Drain

Profile

For an abrupt source/drain doping profile, the channel length is well-defined.

The source-drain separation is fixed at 10 nm and the gate overlap length Lov/edge is defined as (L 10nm)/2. V is 0.26 V and the off-state (V = 1V,V = 0) gate − t ds gs −7 current (Ioff ) is 10 A/µm. When the gate length and therefore the overlap length is varied, both the current drive and the overlap capacitance change accordingly.

The off-current is not sensitive to the overlap length.

Switching delay is measured by a 3-stage CMOS ring oscillator in a mixed-mode simulation. Without loading, the intrinsic delay vs. gate overlap length shown in

Figure 4.4 (open circles) indicates that the optimum performance is achieved at an Lov of 0 nm. When the overlap length is positive, excessive overlap capacitance degrades the switching performance. For the underlapped devices, high series resistance causes low current drive and longer delays.

One concern about the result of the optimum gate overlap length is the surface counterdoping. To examine whether counterdoping has effect on the optimum performance result, 10-nm n-MOSFET with retrograde doping profile is used. The gate work function is adjusted so that the threshold voltage is about the same as that in the n-MOSFET with counterdoping. The optimum gate overlap of zero is obtained. Therefore, the result of the optimum gate overlap is not sensitive to the channel counterdoping profile applied. 70

7.5 3

7 2.5

6.5 2

6 loaded delay (ps) intrinsic delay(ps) 1.5

5.5 −2 0 2 4 L /edge (nm) ov

Figure 4.4: Switching delay of a 3-stage ring oscillator vs. gate overlap for the abrupt S/D doping profile. Open circles are for the intrinsic delay. Asterisks are for the delay with a loading of 20 fF at each stage.

Loaded delay is studied by adding a 20 fF capacitance at each node of the

3-stage ring oscillator. 20 fF is about 4 to 5 times the intrinsic gate capacitance and therefore represents a case of heavy loading. The delay with loading is also plotted in Figure 4.4 (asterisks) where the minimum delay is located at an overlap length of 1 nm/edge. The minimum delay shifts to a positive gate overlap because higher drive current out-weights lower overlap capacitance for loaded circuits. The performance degrades sharply as Lov goes negative, so underlapped regions should be avoided.

The previous conclusion is based on the simulation environment where the device is covered by SiO2 to simulate the fringing field. Since the gate insulator 71

12 nm

Metal ǫi =5ǫox Gate ti =2nm















































































































































































































































14nm









Source10 nm









Drain









(n)









(n)

~ ~ Substrate (p)

Figure 4.5: The illustration of an n-MOSFET with extended gate insulator. Below the gate, all dimensions, contacts and doping profiles are the same as those in previous 10-nm MOSFET design. SiO2 is covered on top of the devices. should be high-K gate instead of Si dioxide, it is a possible structure to have the high-K material of 2-nm thickness cover the surface. The illustration of this device structure is shown in Figure 4.5. The gate insulator extension is the only thing that is changed and all other parameters including the contact locations are kept the same as before. The gate length in this case is the length of metal gate contact.

Simulation of three-stage ring oscillator is used to obtain the intrinsic switching delay as a function of the gate overlap/underlap length as shown in Figure 4.6. The intrinsic delay of the CMOS with SiO2 cover is also plotted as a comparison. The optimum gate overlap is at -2 nm/edge. The underlapped devices are preferred because of the stronger fringing field due to the extended high-K insulator in the 72 un-gated region, and therefore stronger current is induced in underlapped devices.

On the other hand, the delay is generally larger because the extrinsic capacitance increases as a result of higher dielectric constant. Even the underlapped devices provide the optimum performance compared to the non-underlapped devices with this new structure, the performance degrads compared to the traditional SiO2- covered devices. The following in-depth study of the source-drain gradient is only based on the original design without high-K gate extension.

1.8

1.6

1.4

1.2

intrinsic delay(ps) SiO cap layer 2 high−K cap layer 1 −2 0 2 L /edge (nm) ov

Figure 4.6: The intrinsic delay for CMOS with high-K gate insulator extension as shown in Figure 4.5, as a comparison, intrinsic delays for CMOS without high-K gate extension are also plotted. 73

4.3 The Effect of Source-Drain Doping Gradient on Per-

formance

To simulate the effect of S/D doping gradient, Gaussian profiles along the lateral direction are used with a varying straggle σ:

2 2 −(x−x0) /2σ Nd(x)= N0e

where x is in the lateral direction and x0 is the location where the S/D doping starts to fall off. It references to the edge of the earlier abrupt S/D profile (10 nm

S-D separation) where x0 = 0. As σ increases, if x0 is kept at 0, SCE is severe due to the penetration of the S/D doping tail into the channel. To keep the same off-current as the abrupt (σ = 0, x0 = 0) case, x0 must be backed off to allow a larger S/D separation. As shown in Figure 4.7, Ids vs. Vgs is plotted for σ = 3

1 nm with varying x0. As x0 moves to the left (negative) on the source side (x0 moves to the right on the drain side symmetrically), i.e., as the S-D separation increases, both Ion and Ioff are reduced. By adjusting x0, the off-current of the graded S/D can be made equal to the Ioff of the abrupt case. To compare devices with different S/D doping gradients, Ioff vs. Ion curve is a widely used metric.

In Figure 4.8, Ioff vs. Ion curves are generated by varying the S-D separation for each σ. For more graded S/D with a larger σ, the Ion-Ioff characteristics degrade, especially when σ > 3 nm.

When the off-currents are equalized for different σ, the corresponding doping

1When the S-D separation is varied, the gate length is fixed at a large value of 18 nm. 74

-2

0.007

10

0.006

-4

10 * 0.005

*

0.004

-6

10

-4.6 -6nm 0.003

(A/um) -3 x0=-2 ds I

Ioff of the abrupt* 10 nm case

0.002 -8

10

*

0.001

-10

0.000 10

-0.5 0.0 0.5 1.0 1.5

Vgs (V)

Figure 4.7: Drain current vs. gate voltage for σ = 3 nm. The location of S/D (x0) is labeled next to each curve. Increasing S-D separation (more negative x0) leads to reduced I and I . The solid line (x = 4.6 nm) represents the case where on off 0 − the off-current equals the Ioff of the abrupt 10 nm case. profiles of the source region are plotted in Figure 4.9 (the doping in the drain is symmetric to the source). More graded S/D profiles require a larger S-D separation because of the SCEs caused by the penetration of the S/D doping tail into the device. The S/D lateral gradient (LG) is defined as the slope at the point where the doping is 1/10 of the peak doping. For example, σ = 3 nm corresponds to a lateral gradient of 3.2 nm/decade.

Once the S-D separation of the graded S/D is determined from the condition of the same Ioff as the abrupt case, the effect of gate overlap can be studied by varying Lgate. Similar to the abrupt case, the off-current is insensitive to the gate overlap length for a fixed source-drain separation. The on-current can be 75

1E-4

=0

=3nm

1E-5

=5nm

1E-6

=8nm

1E-7

1E-8 Off-stateCurrent (A/um)

1E-9

1.0 1.5 2.0 2.5 3.0 3.5

On-state Current (A/um)

Figure 4.8: Ioff vs. Ion curves for different S/D lateral doping straggles. Each curve is generated by varying the S-D separation. plotted as a function of the gate overlap length (L /edge = (L 10nm)/2) ov gate − for different S/D lateral gradients ranging from zero to 5.4 nm/decade, as shown in Figure 4.10. The electrons in a 10-nm channel experience the combination of velocity saturation and ballistic transport. Although the accurate prediction of the drive current can not be obtained using drift-diffusion model, the relative value is what really matters in this study. It clearly shows that the drop of Ion due to the increased source/drain series resistance as Lov is decreased.

Following the same approach as the abrupt case, the intrinsic delays are plotted as a function of the gate overlap length for different source/drain lateral gradients in Figure 4.11. For each lateral gradient, there is an optimum gate overlap length where the delay is minimum. The optimum Lov for minimum intrinsic delays are 1, 76

20

) 1x10 -3

19

9x10

19

7x10

19

6x10

19

4x10

19

3x10

=0

19

=3nm (LG=3.2nm/dec) 1x10 Doping Concentration (cm

=5nm (LG=5.4nm/dec)

=8nm (LG=8.6nm/dec)

-20 -15 -10 -5 0

Lateral Dimention (nm)

Figure 4.9: Source doping profiles for different lateral straggles when the off-current is the same as the abrupt 10 nm case. The lateral gradient (LG) is defined as the slope at the point where the doping is 1/10 of the peak doping.

3

2.5 (mA/um) on I 2 LA=0 LA=3.2nm/dec LA=5.4nm/dec −1 0 1 2 3 4 L /edge (nm) ov

Figure 4.10: The on-currents (Vds = Vgs = 1V) are plotted vs. the overlap length for source/drain gradient of 0, 3.2, 5.4 nm/decade . 77

2 and 3.5 nm/edge for source/drain lateral gradients of 3.2, 5.4 and 8.6 nm/decade, respectively. An approximate doping level of 7 1019 cm−3 is obtained at the edge × of the optimum gate length for all lateral gradients (see Figure 4.9). In other words, any region with a S-D doping level less than 7 1019 cm−3 should not × be left un-gated, otherwise the series resistance will result in a longer delay. For

MOSFETs with a laterally graded source/drain doping profile, channel length is not well defined [9], therefore “overlap/underlap” has only relative meaning. But the 7 1019 cm−3 doping requirement holds true regardless of the specific choice × of the “zero overlap” position. Similarly, loaded delays are plotted in Figure 4.12.

Variation of the loaded delay is dominated by the on-current since the overlap capacitance is only a small fraction of the total capacitance. The minimum delay degrades rapidly as the S/D doping becomes more graded due to the loss of current drive, consistent with the results of Figure 4.8. From the results of both the intrinsic and the loaded delay analysis, a source/drain lateral gradient below 3 nm/decade is required to avoid significant performance degradation.

4.4 Band-to-Band Tunneling Current

The band-to-band tunneling in the heavily doped drain junction was discussed in Chapter 2. For an n-MOSFET in an inverter, the band-to-band tunneling leakage became problematic when the PN junction is reverse biased — the gate is grounded and the drain is pulled up to the supply voltage. This tunneling current 78

2.5

2

1.5 intrinsic delay(ps) LG=0 LG=3.2nm/dec LG=5.4nm/dec LG=8.6nm/dec 1 −1 0 1 2 3 4 5 L /edge (nm) ov

Figure 4.11: Intrinsic delay vs. gate overlap length for different S/D lateral gradi- ents (LG).

LG=0 LG=3.2nm/dec 9 LG=5.4nm/dec

8

7 loaded delay (ps)

6 −1 0 1 2 3 4 L /edge (nm) ov

Figure 4.12: Switching delay with a load capacitance of 20 fF/stage vs gate overlap length for different S/D lateral gradients (LG). 79 depends on the reverse bias as well as the minimum tunneling distance which is defined as the minimum distance between the conduction band and the valence band in the junction as shown in Figure 2.5. In this study, the source-drain lateral gradient of 3 nm/decade is a limit. Since it is hard to achieve a gradient below this limit in process, 3 nm/decade is used to study the effect of band-to-band tunneling.

First, a standby n-MOSFET in an inverter is considered. During standby, the bias condition is either (a): Vg = Vdd and Vs = Vd = 0 or (b): Vd = Vdd and

Vg = Vs=0. For (a), the leakage mainly comes from the gate tunneling current as discussed in Chapter 2. But another leakage source may occur in the short channel devices. At high gate voltage, the conduction band bends down toward the oxide/silicon interface. Since the depletion width is only 5 nm, tunneling from the substrate into the channel may happen as well. On the other hand, the potentials of the source and the drain are equal in case (a), the electrons tunneling from the substrate into the channel do not contribute to the leakage current. Under the bias condition of case (b), there are three leakage sources: thermal leakage current, source-to-drain direct tunneling and the band-to-band tunneling from the substrate to the drain region.

As discussed in Chapter 2, source-to-drain direct tunneling is not an issue for channel length of 10 nm, but band-to-band tunneling may dominate over the sub- threshold thermal leakage current. In Figure 4.13, the electric field contours of an n-MOSFET under standby status (Vg = Vs = 0 and Vd = Vdd) is shown. The 80

Figure 4.13: The electric field (absolute value) contour of a 10-nm n-MOSFET with Vg = Vs = 0 and Vd = Vdd.

high field region is located in the drain junction. By plotting the band diagram across the highest field region, the tunneling level can be estimated from the min- imum tunneling distance. Since the source-drain doping is graded, a slant cut is needed to show the steepest band bending in the junction. The cut is along the streamline which goes through the highest electric field point and is perpendicular to the electric field contour as shown in Figure 4.13. The band diagram of this cut is plotted in Figure 4.14 where a minimum tunneling distance of 3.5 nm is obtained. According to [25], the minimum tunneling distance in this case corre- sponds to about 103 A/cm2 at room temperature. Consider the high field region of the MOSFET, the tunneling current from each source is about 10−7 A/µm. This 81 is of the same magnitude as the thermal leakage current. Since the band-to-band tunneling current is a weak function of temperature, it is not a dominant factor when the device is operated in the worst case — high temperature.

1.5

e

Substrate (p) Drain (n)

1.0

0.5

0.0

W =3.5nm

tmin

-0.5

E

c

-1.0

-1.5

E BandDiagram (eV)

v -2.0

-2.5

-0.005 0.000 0.005 0.010 0.015

Streamline Coordinate (um)

Figure 4.14: The band diagram of the region where largest band bending appears in the drain junction. The device under study is shown in Figure 4.13. Electrons are tunneling from the substrate to the drain region. The band diagram is plotted along the streamline shown in Figure 4.13. A minimum tunneling distance of the drain junction is 3.5 nm.

The band-to-band tunneling current from substrate to channel under high gate voltage condition does not cause a concern in an inverter, but it may become a major leakage source under other bias conditions. For example, the top n-

MOSFET N1 in a two-way CMOS NAND gate as shown in Figure 4.15 where

Vin1 = Vdd, Vin2 = 0 and the output node is Vdd. The source node of N1 is brought 82

up to Vdd-Vt to keep N1 in off state since it is in series with N2 which is off because of the grounded gate. To estimate the tunneling leakage currents in N1, the 10-nm counterdoped device is used with the bias condition of Vg = Vd = 1 V and Vs =0.8

V. The electric field contour is shown in Figure 4.16.

Vdd

P1 P2

Vout=Vdd

Vin1 N1 =Vdd Vx=Vdd Vt Vin2 N2 = 0

Figure 4.15: Circuit diagram of a two-input CMOS NAND gate. The transistors are labeled N1, N2 and P1, P2. The bias condition is also labeled at the nodes.

High electric field region where abrupt band bending occurs is located in the surface channel region where the bands bend from the substrate toward the sur- face and the drain junction where the bands bend from the substrate toward the drain, as shown in Figure 4.16. In the channel region, a cut is made in the direc- tion perpendicular to the interface. While in the drain junction, a cut along the 83

Figure 4.16: The electric field contour of 10-nm MOSFET under bias condition of Vs = 0.8 V, Vg = 1 V, Vd = 1 V. The stream line shown is perpendicular to the electric field contour and passes through the highest field point of the drain junction.

streamline is made which is shown in Figure 4.16. The band diagrams along the two cuts are shown in Figure 4.17. Figure 4.17(a) shows the band diagram along the vertical direction in the center of the device. The zero of the x-axis denotes the gate/substrate interface. The band bends toward the interface with the minimum tunneling distance of 3.6 nm. The slope of the band near the interface decreases due to the surface counterdoping. Figure 4.17(b) shows the band diagram along the streamline which is shown in Figure 4.16. The zero of the x-axis is only a rela- tive location with no real physical meaning. A minimum tunneling distance of 3.5 nm is obtained. Since the minimum tunneling distances obtained here are of the 84 same magnitude as that in the n-MOSFET of an inverter studied previously, same conclusion is drawn — the band-to-band tunneling currents are not a dominant factor when the device is operated in the worst case — high temperature. It is therefore justified to consider the thermal leakage current only in the subthreshold operation mode.

The text of Chapter 4, in part, is a reprint of the material as it appears in “The

Effect of Gate Overlap and Source/Drain Doping Gradient on 10 nm CMOS Per- formance” by Minjian Liu, Ming Cai, Bo Yu and Yuan Taur, IEEE Transaction on

Electron Devices, Dec. 2006. The dissertation author was the primary researcher of this paper. 85

1.5

e

Channel Substrate

1.0

E

c

interface

0.5

0.0

W =3.6nm E

tmin -0.5

v

-1.0 BandDiagram (eV)

-1.5

-2.0

0.000 0.002 0.004 0.006 0.008 0.010 0.012

Perpendicular cut at center (um)

(a)

1.5

e

Substrate (p) Drain (n)

1.0

0.5

0.0

W =3.5nm

tmin

-0.5

E

c

-1.0

-1.5

E BandDiagram (eV)

v -2.0

-2.5

-0.005 0.000 0.005 0.010 0.015

Streamline Coordinate (um)

(b)

Figure 4.17: The band diagram of the region where large band bending appears. The device under study is shown in Figure 4.16. The electron tunneling direction is labeled in each case. In (a), a vertical cut is made along the center of the device and the band diagram is plotted. The minimum tunneling distance is 3.6 nm. In (b), the band diagram is plotted along the streamline shown in Figure 4.16. The minimum tunneling distance of drain junction is 3.5 nm. 5

The Scaling Limit of Power

Supply Voltage from Noise

Margin Considerations

The trade-off between power and performance is a dominating factor in CMOS design. The static power and performance trade-off has been the focus of the

MOSFET design in Chapter 3. As CMOS devices are scaled to 50 nm gate length and below, the growth of the active power leads to the requirement of power supply voltage (Vdd) scaling. But the non-scaling threshold voltage leads to high

Vt/Vdd ratio and therefore poor performance. Extensive research has been done on power supply scaling limit set by the off-current (Vt) vs. overdrive (Vt/Vdd) conflict [11] [59]. In this chapter, the scaling limit of power supply voltage is studied from noise margin considerations.

86 87

In the binary digital circuit, a finite noise margin is required to maintain logic self-consistency. A combinatorial logic gate circuit is self-consistent when any possible combinations of inputs taken from the logic state ranges always produce an output state that lies in the correct logic state range. The non-linearity of the active devices serves to compress the variety of input logic states into two output states. As supply voltage is scaled down, the nonlinearity degradation is shown in Figure 5.1 where the transfer curves of an inverter are plotted. Noise margin is the largest square that can fit inside the transfer curves. When Vdd is reduced from 1 V ( 40kT/q) to 0.2 V ( 8kT/q) while the threshold voltage is ∼ ∼ kept at 1/4 of Vdd, the VNM /Vdd ratio shrinks 38%. As Vdd is scaled down, the noise margin reaches zero before the supply voltage does. This is the nonlinearity degradation. A fundamental limit of the minimum power supply voltage is 3 4 − kT/q which is achieved in the subthreshold regime where the CMOS supply voltage is below the threshold voltage. In the subthreshold regime, dVout/dVin = gm/gds is about exp(qVds/kT )/m, derived from the subthreshold current equation [11]. The maximum exponential non-linearity is therefore achieved. CMOS’s exhibit non- linearity only when the supply voltage is much higher than the electron thermal energy.

For logic circuits with multiple fan-in, multiple transfer curves corresponding to different input combinations must be considered [18]. This aggravates the loss of noise margin as shown in Figure 5.2, where the noise margin square is obtained from the leftmost and the rightmost (flipped) transfer curves. Substantially higher 88

1

0.8 V NM )

in 0.6

(V V dd out 0.4 V V /V ratio NM dd 0.2 shrinks 38%

0 0 0.2 0.4 0.6 0.8 1 V (V ) in out

Figure 5.1: The transfer curves of an inverter with Vdd of 1 V and 0.2 V respectively. For each Vdd, Vt is kept at 1/4 of Vdd. The slope of the linear transition region is degraded as Vdd decreases. Noise margin is the largest square that can fit inside the transfer curves.

Vdd than that for the inverter (Figure 5.1) is needed to guarantee sufficient noise margin.

As CMOS’s are approaching the scaling limit, process-induced Vt variation be- comes increasingly prominent and can significantly increase the minimum supply voltage. When the Vt variation is included in the noise margin simulations, the worst case switching condition will be redefined based on both the input combi- nation and the choice of CMOS’s with different Vt. The minimum supply voltage condition is studied for high performance 10-nm CMOS logic gate in the worst case switching scenario. 89

1

0.8 )

in 0.6 b (V a c

out 0.4 V

0.2

0 0 0.2 0.4 0.6 0.8 1 V (V ) in out

(a)

1

0.8

) b’ in 0.6 (V a out 0.4 V

0.2

0 0 0.2 0.4 0.6 0.8 1 V (V ) in out

(b)

Figure 5.2: Noise margin for NAND logic circuits with multiple transfer curves de- pending on different combinations of inputs. In Figure (a), one-gate-switching curve a is the leftmost curve with the lowest transition voltage and all-gates- switching curve b is the rightmost curve with the highest transition voltage. In Figure (b), curve b’ is the flipped curve of b in Figure (a). Noise margin is the largest square that can fit into the “eye diagram”. 90

Table 5.1: Vt roll-off assumption in the 2-D device simulation.

Vds (V) 0.1 0.4 0.5 0.7 0.8

Vt (V) (L = 8 nm) 0.151 0.089 0.070 0.032 0.013

Vt (V) (L = 10 nm) 0.215 0.180 0.169 0.150 0.140

Vt (V) (L = 12 nm) 0.259 0.236 0.230 0.218 0.212

Vt roll-off(V) 0.108 0.147 0.160 0.186 0.199

5.1 Device Assumptions for Noise Margin Study

The simulation was carried out using the two-dimensional TCAD tool from

SYNOPSYS. 10 nm is chosen as the channel length with the nominal V . 20% t ± channel length variation is assumed with a total Vt roll-off of 0.1 V (Vds =0.1 V) as shown in Table 5.1. The Vt roll-off is defined as the Vt difference between 12-nm and 8-nm CMOS’s. Vt roll-off increases with drain voltage (supply voltage) due to the effect of drain induced barrier lowering.

5.2 Noise Margin for CMOS NAND Circuits

In the binary digital logic, two distinct logic states are identified within a relatively small range of voltages. Logic state 1 lies in the voltage range between

VHmin and VHmax. Logic state 0 lies in the voltage range between VLmin and VLmax.

In the logic circuit, inverters are added as buffers and they are adequate to 91

push the logic state 1 to Vdd or the logic state 0 to ground. Therefore VHmax and VLmin are set to Vdd and 0 respectively. The definition of VHmin and VLmax is shown in Figure 5.3 in terms of a 3-way NAND. Due to the Vt roll-off shown in

Table 5.1, a 12-nm MOSFET has the lowest current drive and is hence the weak

MOSFET. By the same token, an 8-nm MOSFET is the strong MOSFET. The generation of the maximum low signal VLmax requires strong pull-up MOSFETs (8- nm PMOS) and weak pull-down MOSFETs (12-nm NMOS) in the NAND circuit with all inputs tied at the minimum high signal VHmin. Based on the definition, the rightmost curve (Curve A) is generated by sweeping all inputs together from 0 to

Vdd. Conversely, the generation of VHmin requires strong NMOS (8-nm) and weak

PMOS (12-nm) with the logic inputs (1, 1, 0) as high as possible—(Vdd,Vdd,VLmax).

The leftmost curve (Curve B) is generated by sweeping only one input while keeping the other inputs at Vdd. VLmax and VHmin are defined by the curves as shown.

Figure 5.4 shows how the minimum supply voltage is determined from noise margin considerations. When the supply voltage is above the minimum limit in

Figure 5.4(a), curves A (flipped) and B have the intercepts and the noise margin is larger than zero. When the supply voltage is reduced too far, as shown in

Figure 5.4(b), the transfer curves do not intercept and no consistent (VLmax, VHmin) can be defined. In that case, the output will eventually end up in the wrong state.

When Curve B and the flipped Curve A have exactly one intersection, i.e., tangent to each other, the noise margin is zero, which corresponds to the minimum supply voltage condition. 92

V 1 n−MOS’s: 8nm (strong) Hmin n−MOS’s: 12nm (weak) p−MOS’s: 12nm (weak) 0.8 p−MOS’s: 8nm (strong)

VHmin dd VLmax

/V 0.6 VHmin Lmax dd Curve A V V out VHmin

V 0.4 Curve B the rightmost VLmax (B) the leftmost curve (A) V 0.2 curve Lmax V V 0 Lmax Hmin 0 0.2 0.4 0.6 0.8 1 V /V in dd

Figure 5.3: The definition and the generation of the maximum low VLmax and the minimum high VHmin signal

The leftmost transfer curve is generated by sweeping one input while keeping other inputs at Vdd, but which n-MOSFET is the switching device? Our simulation result shows that bottom switching is preferred for high supply voltage while top switching is needed when the supply voltage goes below 0.4 V. To understand this scenario, a two-way NAND gate is studied which is shown in Figure 4.15. Firstly, a supply voltage which is much higher than the threshold voltage is considered. In the bottom switching case, bottom transistor N2 is in saturation and N1 is in the linear region. The overdrive of N2 is Vin1. In the top switching case, the switching top transistor N1 is in saturation and the bottom transistor N2 is in linear region.

The node V is above ground. The overdrive of N1 is V V , smaller than that of x in1 − x N2 in the bottom switching case. Since the non-switching device in both cases are in linear region, the overdrive of the switching device determines that there is less 93

V 1 Hmin ) Curve A dd 0.8 /V in 0.6 flipped (V

dd Curve B

/V 0.4 out

V 0.2 V Lmax V V 0 Lmax Hmin 0 0.2 0.4 0.6 0.8 1 V /V (V /V ) in dd out dd

(a)

1

) Curve A dd 0.8 /V

in flipped 0.6 (V

dd Curve B

/V 0.4 out

V 0.2

0 0 0.2 0.4 0.6 0.8 1 V /V (V /V ) in dd out dd

(b)

Figure 5.4: “Eye diagram” for a 3-way NAND gate logic circuit. Vin and Vout are normalized to the supply voltage. Curve A is generated by switching all inputs together. Curve B is generated by switching one input while tying the other two inputs at Vdd. Noise margin exists in (a) where the supply voltage is above the minimum and Curve A is flipped to cross Curve B at (VLmax,VHmin), but not in (b) where the supply voltage is below the minimum and no results for VLmax and VHmin can be obtained. 94

0.4 Bottom Switching Top Switching 0.35 o V 0.3 out

0.25 V x (V) x 0.2 , V

out 0.15 V

0.1

0.05 V x 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 V (V) in

Figure 5.5: The output voltage and Vx are plotted versus input swing for Vdd of 0.4 V. The solid curve is for bottom switching and the dash-dot line is for top switching.

current in the top switching case and the leftmost curve is achieved by sweeping the bottom transistor [11]. Secondly, let’s consider the case where the supply voltage is only slightly higher than the threshold voltage, for example, Vdd =0.4 V. Both the bottom switching and the top switching cases are studied in Figure 5.5 where the output voltage and Vx are plotted versus input swing for Vdd of 0.4 V. For the bottom switching, Vx (about 0.3 V) is close to Vdd at low input voltage. This means that the threshold voltage of the top transistor N1 is increased by (m 1)V − x — above 0.2 V higher than the overdrive of N1 (V V 0.1 V). N1 is in the dd − x ≈ subthreshold region which leads to high series resistance and low current. The discharging current depends on two factors — overdrive voltage of the switching 95

0.5

0.4

)(V) 0.3 in

(V 0.2 out V

0.1 W /W =3 p n W /W =0.6 p n 0 0 0.1 0.2 0.3 0.4 0.5 V (V ) (V) in out

Figure 5.6: Voltage transfer characteristics for different width ratios with fixed Vt. Noise margin is zero for width ratio of 3 (dash-dot lines) but larger than zero for width ratio of 0.6 (solid lines) where the leftmost curve and the flipped rightmost curve achieve better symmetry across the diagonal. Minimum Vdd is 0.5 V for Wp/Wn = 3 but smaller than 0.5 V for Wp/Wn =0.6.

device and the series resistance of the non-switching device. For supply voltage of 0.4 V or lower, the series resistance plays the dominating role. Compared to the high supply voltage condition where N1 is working in the linear region when the bottom device (N2) is switched, higher input voltage is needed to bring the output voltage down. Therefore to obtain the leftmost curve, top n-MOSFET will be swept for low Vdd. For gate with multiple inputs, the non-switching devices can be considered as one device. Therefore the analysis of the two-way NAND can apply to multiple-input gate too. 96

Besides the dependence on Vt, minimum Vdd is also affected by the width ra- tio (Wp/Wn) of the NAND gate. As shown in Figure 5.6 where voltage transfer characteristics are plotted with the same Vt but different width ratios. Minimum

Vdd of 0.5 V is obtained at width ratio of 3 (dash-dot lines). As the width ra- tio decreases, the pull-down devices (NMOS) become stronger compared to the pull-up devices (PMOS), so the transfer curves shift left. Noise margin increases because the leftmost curve and the flipped rightmost curve achieve better symme- try across the diagonal as shown in Figure 5.6. When the width ratio reaches 0.6

(solid lines), the best symmetry is reached (width ratio smaller than 0.6 leads to the loss of symmetry) and the lowest minimum Vdd can be obtained. Therefore in the following noise margin study, Wp/Wn of 0.6 is used.

5.3 Minimum Power Supply Voltage from Noise Margin

Considerations

The non-linearity of noise margin degrades with increasing number of inputs.

A three-way NAND gate is used to study the minimum power supply voltage in the worst case switching condition, since gate with inputs more than three has low performance and is usually replaced by multiple gates with less inputs. As shown in

Table 5.1, threshold voltage is a function of the power supply voltage due to DIBL effect. Minimum power supply voltage can be obtained by lowering the supply voltage till noise margin reaches zero, then the corresponding threshold voltage is 97

0.4

0.3

0.2

Vout (Vin) (V) (Vin) Vout 0.1

V =0.17

t

V =0.155

t

0.0

0.0 0.1 0.2 0.3 0.4

Vin (Vout) (V)

Figure 5.7: For a fixed supply voltage, in this case — 0.4 V, work function is adjusted to reach the zero noise margin condition. Threshold voltage of 0.155 V is obtained. extrapolated from the IV characteristics with drain voltage equal to the minimum supply voltage. Since the threshold voltage is already obtained for supply voltage from 0.4 V to 0.8 V as shown in Table 5.1, an equivalent but more straightforward simulation setup is to fix the supply voltage and to adjust the gate work function to change the threshold voltage.

As shown in Figure 5.7, work function is adjusted to change the threshold voltage. Vt is varied by adjusting the gate work function so that the Vt roll-off is kept the same as that shown in Table 5.1. The transfer characteristics of a three- way NAND gate at supply voltage of 0.4 V are plotted. The condition of zero noise 98 margin gives a threshold voltage of 0.155 V. In this way, the threshold voltages correspond to other minimum supply voltages are obtained. The simulation results

◦ of minimum Vdd as a function of the nominal Vt are plotted in Figure 5.8 for 27 C.

0.8

0.7

Allowed V , V

dd t

0.6

No

Noise

0.5

Margin

V /V >1/3

t dd

0.4 Minimum Supply Voltage (V) Voltage Supply Minimum

0.08 0.10 0.12 0.14 0.16 0.18

Vt (V)

◦ Figure 5.8: Minimum supply voltage versus nominal Vt at room temperature (27 C) for 3-way NAND circuits. Vt/Vdd < 1/3 defines the high performance region. The minimum supply voltage is 0.43 V.

Higher Vt allows lower minimum Vdd because of the better non-linearity for higher Vt because of the exponential non-linearity in the subthreshold region. The fundamental physics behind this is as follows: The slope of the voltage transfer curve is V /V = g /g . Since I (V V )2 where V is a function of V out in m ds ds ∝ gs − t t ds due to DIBL, gm is less sensitive to Vt variation than gds. The slope increases with higher Vt, leading to better non-linearity and allowing lower Vdd. High Vt/Vdd ratio leads to low gate overdrive and poor performance. For high performance CMOS, 99

Vt/Vdd < 1/3 is usually required. When both conditions are plotted in Figure 5.8, they define a minimum supply voltage of 0.43 V.

The minimum supply voltage at 100◦C is also studied. High temperature de- grades the noise margin condition through two aspects — the increase of kT/q factor and the decrease of Vt. In Figure 5.9, by plotting the minimum Vdd vs.

◦ 100 C Vt, the latter effect is eliminated. The curve shows that the kT/q effect is increased for lower Vdd. Minimum supply voltage of 0.49 V is obtained for high performance CMOS at 100◦C. Therefore in the worst case scenario, the supply voltage can not be lowered below 0.5 V.

0.8

0

100 C

0.7

Allowed V , V

dd t 0

27 C

0.6

No

V /V >1/3

0.5 t dd

Noise

Margin

Low Performance

0.4 Minimum Supply Voltage (V) Voltage Supply Minimum

0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22

Vt (V)

◦ Figure 5.9: Minimum supply voltage versus nominal Vt at 100 C for 3-way NAND circuits. The result obtained at room temperature is also plotted as comparison. Vt/Vdd < 1/3 defines the high performance region. The minimum supply voltage is 0.49 V.

A more stringent assumption of Vt variation can decrease the minimum Vdd. 100

Simulation of CMOS’s with Vt roll-off of 100 mV at Vds of 0.5 V (instead of 0.1

V) shows that minimum Vdd can be as low as 0.37 V for high performance 10-nm

CMOS.

Finally, to conclude this chapter: minimum Vdd of 0.5 V is obtained for high performance 10-nm CMOS. The result can be applied to other channel length near scaling limit as long as the Vt roll-off is of the same level. For low power CMOS which allows Vt/Vdd > 1/3, a lower Vdd can be used with sufficient noise margin at the expense of switching performance.

The text of Chapter 5, in part, is the reprint of the material as it appears in

“Scaling Limit of Power Supply Voltage from Noise Margin Considerations”, by

Minjian Liu, Ming Cai and Yuan Taur, Proceedings of SISPAD, Sep. 2006. The dissertation author was the primary researcher of this paper. 6

Scaling to 10 nm — Bulk, SOI or

DG MOSFETs?

Having studied the bulk 10-nm CMOS design, the next question is: will the conventional bulk MOSFET be successfully scaled down to reach this ultimate limit or will alternatives, like SOI or double-gate (DG) MOSFETs lead the role?

To answer this question, both the fundamental limit and practical implementation difficulties will be taken into considerations.

The structures of bulk, SOI and DG-MOSFET are illustrated in Figure 6.1.

Partially depleted SOI (PDSOI) scales similarly to the bulk MOSFET except for the floating body effect. Therefore only fully-depleted SOI (FDSOI) is considered.

Both FDSOI and DG-MOSFET scaling requires the thinning down of the Si layer.

101 102

Figure 6.1: The structure of bulk, fully-depleted SOI and DG-MOSFET.

We have studied the 10-nm bulk CMOS design and a summary of the tech- nology requirement is shown in Figure 6.2. Abrupt placements of n- and p-type dopants at > 1019 cm−3 levels for both the channel and the source-drain regions are required. High-K dielectric gate is required to achieve the EOT of 0.4 to 0.5 nm. Metal electrode is needed to avoid poly-silicon depletion effect. To lower the threshold voltage due to high body doping, the work function of the metal elec- trode is chosen to be at conduction band edge for n-MOSFET and at valence band edge for p-MOSFET. The high body doping leads to the concern of band-to-band tunneling which is shown to be comparable to the thermal leakage current at room temperature. For SOI and DG-MOSFET, one advantage is the removal of the body doping and therefore the mitigation or elimination of the tunneling current.

Based on the most recent literature study, the technology requirements of 10-nm

SOI and DG-MOSFET will be reviewed and the question will be answered at the end of this chapter. 103

Figure 6.2: The summary of technology requirements of 10-nm bulk MOSFET.

6.1 SOI CMOS

FDSOI has been recognized as a potential candidate for developing high per- formance consumer electronics. The ultrathin silicon body of a SOI MOSFET is electrically isolated from the underlying substrate by a thick buried oxide (BOX).

The source/drain junction surface and therefore the associated capacitance are greatly reduced. The short-channel scaling of undoped FDSOI with standard thick BOX depends on silicon film thickness, gate dielectric thickness and the corresponding dielectric constants, but not the BOX thickness. The general scale length model [18] is inapplicable to the short-channel FDSOI scaling due to the source/drain-to-channel lateral-field coupling through the BOX as shown in Fig- ure 6.3. The depth of source/drain lateral field coupling in the BOX does not 104

increase with BOX thickness after tBOX becomes two times larger than the chan- nel length. The threshold roll-off is independent of the BOX thickness even though the scale length keeps increasing with thicker BOX.

To gain a clear guideline for short-channel FDSOI scaling, the constant Lmin contours for undoped FDSOI was developed in [60] by using 2-D numeric simulator.

Lmin is defined as the channel length with the Vt roll-off of 100 mV. A simple scaling rule is obtained by extrapolation:

ǫsi Lmin =4.5(tsi + ti) (6.1) ǫi

For gate dielectric with very high permittivity, the second term in equation 6.1 becomes negligible and L is limited to 5t . In order to achieve 10-nm FDSOI, min ∼ si high-K gate dielectric and metal gate are both required, like in bulk CMOS.

Figure 6.3: Field patten inside of a short channel SOI shows the strong source and drain coupling [60]. 105

The scaling limit of SOI MOSFETs also depends on the limit of gate insulator and silicon-film thickness. Based on the uncertainty principle, the momentum uncertainty of confined electrons increases with thinner silicon films. A higher ground state electron energy, and therefore a higher threshold voltage is induced.

The electron ground state energy is very sensitive to silicon-film thickness when t < 5nm [61]. A 5% variation in thickness at 2-nm thick Si film will result in 10% si ∼ fluctuation in threshold voltage. The Si film thickness can not be scaled below 2 nm in order to avoid excessive quantum threshold voltage shift, e.g., ∆V QM 0.2 V. t ∼ On the other hand, QM gate tunneling leakage limits the gate insulator thickness to 1 nm for oxide and 2 nm for high-K insulators with typically lower barrier ∼ ∼ heights

10-nm undoped SOI MOSFET design is achievable if both silicon-film thickness and gate dielectric thickness are scaled to their limits 2 nm but with a gate ∼ dielectric constant of 35.1 (EOT = 0.22 nm). It is a more stringent requirement than bulk MOSFET.

Although body doping can help relax the 5t limitation, high body doping ∼ si leads to high field which will trigger severe triangular quantum effect and add another 0.1-0.2V to the threshold voltage. In general, body doping does not help to extend the scaling limit [60]. 106

6.2 DG MOSFET

The DG-MOSFET was proposed in the early 1980. The concept has been gradually explored both experimentally and theoretically by many groups. The

DG-MOSFET is electrostatically much more robust than the standard single-gated

MOSFET since the gate shields the channel from both sides, suppressing penetra- tion of the field from the gate, reducing short channel effects.

The SCEs are controlled through the scaling of Si thickness instead of depletion width as in bulk MOSFET. The channel doping can be removed and the associated effects such as dopant discreteness and band-to-band tunneling can be relieved or eliminated. Source/drain junction capacitance is reduced. In symmetric DG-

MOSFET, subthreshold slope of 60 mV/decade can be achieved due to the field effect from both sides of the channel. Another potential advantage to bulk CMOS is more current drive (or gate capacitance) per device area.

The scale length of DG-MOSFET can be obtained from the three-region scale length equation [18]. For symmetric DG-MOSFET as shown in Figure 6.4, scale length can be expressed as:

tan(πti/λ)tan(πtsi/2λ)= ǫi/ǫsi (6.2)

According to equation 6.2, the normalized gate insulator thickness (ti/λ) vs. the normalized depletion width (Wd/λ) is plotted in Figure 6.5.

In the region of t t , λ is about W +2(ǫ /ǫ )t , For the 10-nm DG-MOSFET i ≪ si d si i i 107

Figure 6.4: The double gate MOSFET structure for 2-D field analysis.

with the same high-K dielectric assumption as the bulk MOSFET (EOT 4 ∼ − 5 A),˚ the silicon thickness is about 4 to 5 nm. This is more relaxed than the tsi requirement for 10-nm SOI. A proposed structure of 10-nm DG-MOSFET is shown in Figure 6.6. Aside from the requirement of uniform silicon thickness of 4 nm to control short channel effect, high-K gate dielectric with EOT of 0.5 nm is needed. DG-MOSFET also requires thick source/drain fan-out structure to reduce the series resistance and perfectly aligned top and bottom gates to each other and to source/drain doping. Metal gate with specific work function is also required in order to obtain desired threshold voltage. Although doping can be added to help adjust the threshold voltage, it is not preferred due to discrete dopant effect.

The implementation of DG-MOSFET poses great challenge. It can be (and has been) made in three basic configurations label type I, II and III in Figure 6.7. Type

I has the advantage that the channel layer is in the plane of the Si wafer surface 108

Figure 6.5: The normalized gate insulator thickness (ti/λ) vs. the normalized depletion width (Wd/λ).

so that the channel thickness is controlled by the thickness of the uniform planar layers rather than by lithography. Both Type II and type III pose great technol- ogy difficulties because such vertical devices require the lithographic technology at least four times more stringent than the minimum gate length in order to control the silicon channel thickness to its required dimension. Type III, which is also called FinFET, has the highest packing density for high-speed logic application since the channel width, the longest dimension for a logic FET, is perpendicular to the plane of the wafer [7]. A version of this has been implemented [62]. Re- cently FinFET with gate length being shrunk to 10 nm was fabricated [63]. The

DIBL is 71 mV/V for n-channel FinFET and 120 mV/V for p-channel FinFET.

Subthreshold slope is 125 mV/decade and 101 mV/decade for n- and p-channel 109

Figure 6.6: The ultimate DG-MOSFET design.

FinFET respectively. The on-current is 446 µA/µm and 356 µA/µm for n- and p-channel FinFET respectively. The short channel effect is not well under control because the Si thickness is in fact 17 to 26 nm [63]. In order to reach a channel length of 10 nm and to shrink the Si thickness to 4-5 nm, major breakthroughs in the fabrication techniques are needed for the implementation of manufacturable

DG-MOSFETs [64].

6.3 10 nm: Bulk MOSFET is the More Likely Candidate

In order to reach 10 nm, High-K gate dielectric and metal gate are required for all three types of MOSFETs — bulk, SOI and DG-MOSFETs. The effective oxide thickness of 0.4 to 0.5 nm is needed for both bulk and DG-MOSFET. FDSOI 110

Figure 6.7: Possible orientations of double-gate MOSFET on a silicon wafer. Type I is a planar structure, Type II and III are vertical structure. Type III is also called FinFET.

has the worst SCE control. Scaling to 10 nm requires both tsi and ti to scale to the 2 nm limit with a gate dielectric constant of 35. The choice of metal gate ∼ work function is based on the threshold voltage requirement from both the leakage control and performance (Vt/Vdd ratio) considerations. No known metal has gate work function located outside of the Si band gap, ideal work function for bulk and SOI MOSFET is at the conduction band edge for n-MOSFET and valence band edge for p-MOSFET. Specific work function around mid-gap is needed for

DG-MOSFET. 111

The depletion depth in the substrate is controlled by the doping profile in bulk

MOSFET. For channel length of 10 nm, bulk MOSFET requires the control of

19 −3 abrupt doping levels above 10 cm . FDSOI requires tsi to be the limit of 2 nm.

DG-MOSFET can relax Si thickness requirement to 4-5 nm, but the DG structure is rather challenging to make. Taking everything into consideration, it appears that bulk MOSFET is the most likely candidate for extending CMOS scaling to

10 nm.

The text of Chapter 6, in part, is the reprint of the material as it appears in

“Scaling to 10-nm, Bulk, SOI or DG MOSFET?”, by Minjian Liu, Wei-Yuan Lu,

Wei Wang and Yuan Taur, Proceedings of ICSICT, Oct. 2006. The dissertation author was the primary researcher of this paper. 7

Conclusion

A comprehensive design study on 10-nm bulk MOSFET is presented. 2-D

TCAD tool from SYNOPSYS, including the finite size structure editor (MDRAW) and the device simulator (DESSIS), are used in the study.

Based on the ITRS roadmap, 10-nm CMOS technology is expected to be in production in 2015. On the other hand, CMOS scaling to 10 nm channel length faces several fundamental limiting factors. They are short channel effect, gate oxide tunneling, and scaling of power supply voltage.

First, short channel design and threshold voltage control are presented. Based on the 2-D scale length theory, a gate insulator with 0.4 A˚ equivalent oxide thick- ness and a depletion width of 5 nm are required. High-K gate dielectric is needed because SiO2 can not be scaled to 4 A˚ due to high tunneling currents. A thicker

SiO2 would significantly degrade short channel effect. Metal gate not only elimi-

112 113 nates poly-depletion effect but also helps the incorporation of high-K dielectric by relieving thermal stability issues associated with high temperature anneals in the poly-silicon process. Metal gate work function at the edge of conduction band and valence band are used for n- and p-MOSFET respectively. High body doping above

1019 cm−3 is needed to control the depletion width but this leads to high threshold voltage, aggravated by quantum-mechanical effects. Even the extreme retrograde doping with a forward body bias can not achieve the required low threshold volt- ages. Therefore, counterdoping is required to further lower the threshold voltage.

Furthermore, laterally nonuniform HALO doping is shown to effectively mitigate short channel Vt roll-off.

The optimization of gate overlap and source/drain lateral doping gradient is studied based on the CMOS circuit performance. An optimum gate overlap length of about 1 nm/edge is obtained for abrupt source/drain doping profiles. For graded source/drain doping, the gate overlap should be such that the source/drain regions of doping < 7 1019 cm−3 are covered under the gate. In addition, a source/drain × lateral gradient of less than 3 nm/decade is required so the MOSFET current is not degraded by the series resistance.

In order to reduce active power, the scaling limit of supply voltage is stud- ied from noise margin considerations. Mixed-mode simulation is implemented to evaluate CMOS performance, taking both the Miller capacitance and the current drive into consideration. A three-way NAND gate is considered in the worst-case 114 switching scenario with threshold voltage roll-off at the scaling limit. As a result of the trade-off between the noise margin requirement and circuit performance, a minimum supply voltage of 0.5 V is concluded.

Finally, considering the daunting technology requirements of 10-nm FDSOI and

DG-MOSFET, bulk MOSFET is judged to be the most likely candidate to bring

CMOS scaling to 10 nm. Bibliography

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