ADE Module-1 Notes
Module-1 Syllabus: Electronic devices and applications -1 : Diodes, Clippers and Clamper, Transistor, Transistor Biasing, Transistor as a switch, BJT Vs FET, JFET, MOSFETs, FET 9 applications, CMOS Device, Ideal vs practical OP-AMP, Comparator, Active Filters, Relaxation Oscillator
Some basic information about transistor Transistor or BJT (Bipolar Junction Transistor) – • Invented in 1948 by Bardeen, Brattain and Shockley • Contains three adjoining, alternately doped semiconductor regions: Emitter (E), Base (B), and Collector (C) • The middle region, base, is very thin • Emitter is heavily doped compared to collector. So, emitter and collector are not interchangeable. • Two types- NPN and PNP • 3 types of Configuration- Common emitter, Common collector and Common Base • Most commonly used configuration – Common emitter as it provides good voltage and current gain in amplification circuits Some relationships • VBE = 0.7V • IE = IB IC • IE = (+ 1) IB IC • IC = IB Q-Point (Static Operation Point) • The intersection of the dc bias value of IB with the dc load line determines the Q-point. • It is desirable to have the Q-point centred on the load line. Why? • When a circuit is designed to have a centred Q-point, the amplifier is said to be midpoint biased. • Midpoint biasing allows optimum ac operation of the amplifier and good DC stability. • The values of the parameters IB, IC and VCE together are termed as ‘operating point’ or Q (Quiescent) point of the transistor.
VTU Questions
1. What is Biasing of a transistor and what is its requirement? (4 Marks, Dec 2008) 2. Give the four factors required for biasing circuit. (04 Marks, Dec 2010) Ans: Biasing - • The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system. • In fact, the amplifier increases the strength of a weak signal by transferring the energy from the applied DC source to the weak input ac signal • The analysis or design of any electronic amplifier therefore has two components: 1. The dc analysis and 2. The ac analysis
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ADE Module-1 Notes
• During the design stage, the choice of parameters for the required dc levels will affect the ac response. What is biasing circuit? • Once the desired dc current and voltage levels have been identified, a network must be constructed that will establish the desired values of IB, IC and VCE, Such a network is known as biasing circuit. • A biasing network has to preferably make use of one power supply to bias both the junctions of the transistor. Four factors required for biasing circuit 1. Emitter base (VBE) junction should be forward bias and Collector base junction should be reverse bias. VBE= 0.7V for Silicon(Si), VBE= 0.3V for Germanium(Ge) 2. Collector- Emitter voltage VCE > V CE(Sat) VCE (Sat)= 1V for Silicon(Si) and V CE(Sat)= 0.5V for Germanium(Ge) 3. Collector current IC when no input signal is applied = IC(Max) due to input signal 4. Maximum ratings of IC(Max) , VCE(Max) and PD(Max) should not be reached by the circuit.
3. Discuss with neat sketches, the relation of operating point of transistor for following: a) Near saturation region b) Near cut off region c) at the centre of active region (8M)(Dec 2011) Ans:
Three operating regions S.no Junction bias condition Mode Emitter-base Collector-base Usage 1. Active / Linear Forward Reverse Used for amplification
2. Saturation Forward Forward Used as switch turn ON
3. Cut-off Reverse Reverse Used as switch turn OFF
Output of transistor during three operating regions • Cut off: VCE = VCC, IC 0 • Active or linear: VCE VCC/2, IC IC max/2 • Saturation: VCE 0, IC IC max
From the output characteristics of CE amplifier
1. Point A, near cut off region: No proper bias to both junction => Transistor in Cut Off region => VBE= 0, IC=0 => no amplification. So point A cannot be Q point.
2. Point B, in active region: middle of Active region => both junction properly biased => linear amplification with good voltage and current swing. So, good Q-point.
3. Point C, near saturation region: since near saturation => non- linear amplification(IC not linear with change in Vce). So, not good as Q-point.
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ADE Module-1 Notes
4. Point D, near PD (Max): since near to Power Dissipation curve=> voltage swing is limited. So, not good as Q point.
Active region is bounded by: 1. Saturation region 2. I C (Max) 3. Cut off Region 4. P D (Max)
Types of Biasing circuits: 1. Fixed bias / base bias 2. Emitter bias / self-bias 3. Collector to base bias / feedback bias 4. Voltage divider bias / Universal bias
Some general equation will be required to solve numerical: 1. VE = IERE 2. VC = VCE + VE 3. VB = VBE + VE 4. VBC= VB – VC
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ADE Module-1 Notes
4. Explain transistor in its fixed bias mode with relevant expression. (6 M)(Dec 2012) 5. Explain with a neat diagram and dc equivalent circuit, the working of base bias amplifier. (08 marks, Dec 2009) Ans- Fixed bias: The simplest dc bias configuration. Also known base bias
DC Analysis
For dc analysis, open all the capacitance. So the dc circuit becomes as given
INPUT LOOP
Applying KVL to the input loop: VCC -IBRB – VBE = 0 • From the above equation, deriving for IB, we get, IB = [VCC – VBE] / RB
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ADE Module-1 Notes
So, Ic = β IB = β [VCC – VBE] / RB OUTPUT LOOP
Applying KVL for the output loop: VCC – ICRC – VCE = 0 Thus, VCE = VCC – ICRC
Load line analysis The input loop KVL equation is not used for the purpose of analysis. The output characteristics of the transistor used in the given circuit and output loop KVL equation is made use of.
• The method of load line analysis is as below: 1. Consider the equation VCE = VCC – ICRC ------(1) This relates VCE and IC for the given IB and RC
2. To find point A, put Ic = 0 in the equation (1) VCE = VCC This gives the coordinates (VCC, 0) on the x axis of the output characteristics.
3. To find point B, put Vce = 0 in the equation (1) 0 = VCC – ICRC IC = VCC / RC
Thus giving the coordinates of the point as (0, VCC / RC).
4. The two extreme points so obtained are joined to form the load line. 5. The point where load line intersects the given IB => Q – point or operating point
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ADE Module-1 Notes
Problem 1– Given the fixed bias circuit with VCC = 12V, RB = 240 K, RC = 2.2 KVBE = 0.7Vand = 75. Determine the values of operating point. Solution: Equation for the input loop is: VCC -IBRB – VBE = 0
IB = [VCC – VBE] / RB , Thus substituting the given values in the equation, we get IB = 47.08μA IC = IB = 3.53mA
Equation for the output loop is: VCC – ICRC – VCE = 0
VCE = VCC – ICRC = 4.23V Q-point = (Vce, Ic) = (4.23V, 3.53mA)
Problem 2– The fixed bias circuit has VCC = 12V, IB = 45μA, VCE = 6.5V, VBE = 0.7Vand = 50. Determine the values of resistors. Solution: IC = IB = 2.25 mA Equation for the input loop is: VCC -IBRB – VBE = 0 RB = [VCC – VBE] / IB = 251.11 K Equation for the output loop is: VCC – ICRC – VCE = 0 RC= (VCC – VCE) / IC = 2.44 K
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ADE Module-1 Notes
6. Explain the effects of collector resistor, base current and supply voltage on the operating point of a fixed bias circuit. Which is the ideal position for an operating point on the BJT fixed bias transistor circuit? Explain the above with neat diagrams. (10 M)(June 2012) Ans: Q point variation
1. Due to collector resistor Rc: • As RC is varied, the Q point shifts to left or right along the same IB line since the slope of the line varies. • As RC increases, slope reduces which results in shift of Q point to the left meaning no variation in IC and reduction in VCE.
2. Due to base current IB: • As IB is varied, the Q point shifts accordingly on the load line either up or down depending on IB increased or decreased respectively.
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ADE Module-1 Notes
3. Due to supply voltage Vcc:
• As VcC is varied, the Q point shifts to left or right along the same IB line since the slope of the line varies. • As Vcc increases, slope increases which results in shift of Q point to the right meaning
increasing IC and VCE. 7. Explain emitter bias circuit. (06 marks, Dec 2008)
Ans: Emitter Bias • The emitter bias is a biasing circuit very similar to fixed bias circuit with an emitter resistor added to it. • Including an emitter resistor in the fixed bias circuit improves the stability of Q point.
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ADE Module-1 Notes
DC Analysis For dc analysis, open all the capacitance. So the dc circuit becomes as given
Input loop
Writing KVL around the input loop we get, VCC - IBRB - VBE – IERE = 0 IE = (+1) IB VCC - IBRB - VBE - (+1) IBRE = 0 VCC – VBE = IB (RB + (+1) RE) Solving for IB: IB = (VCC – VBE) / [(RB + (+1) RE)]
So, Ic = β IB = β (VCC – VBE) / [(RB + (+1) RE)]
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ADE Module-1 Notes
Output loop: Collector – emitter loop
Applying KVL, VCC - ICRC - VCE – IERE = 0 IC = IE Thus, VCC - ICRC - VCE – ICRE = 0 VCC - IC (RC + RE) - VCE = 0
VCE = VCC - IC (RC + RE)
Load line analysis
• The method of load line analysis is as below: 1. Consider the equation VCE = VCC - IC (RC + RE)------(1)
2. To find point A, put Ic = 0 in the equation (1) VCE = VCC This gives the coordinates (VCC, 0) on the x axis of the output characteristics.
3. To find point B, put Vce = 0 in the equation (1) 0 = VCC – IC (RC + RE) IC = VCC / (RC + RE)
Thus giving the coordinates of the point as (0, VCC / (RC + RE)).
4. The two extreme points so obtained are joined to form the load line. 5. The point where load line intersects the given IB => Q – point or operating point
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Problem 3: Analyse the following circuit: Given = 75, VCC = 16V, RB = 430k, RC = 2kVBEVand RE = 1k Find Q point, VC, VE, VB and VBC Solution: Input KVL, VCC - IBRB - VBE – IERE = 0 IE = (+1) IB VCC – VBE = IB (RB + (+1) RE) IB = (VCC – VBE) / [(RB + (+1) RE)] = (16 – 0.7) / [430k + (76) 1k] = 30.24A
So, Ic = β IB = (75) (30.24A) = 2.27mA Output KVL, VCC - ICRC - VCE – IERE = 0 IC = IE Thus, VCE = VCC - IC (RC + RE) = 9.19V Q-point= (VCE, IC) = (9.19V, 2.27mA)
VE = IE RE=2.27V VC = VCE + VE = 11.46V VB = VBE + VE = 2.97V VBC = VB – VC = 2.97 – 11.46 = - 8.49V
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ADE Module-1 Notes
Problem 4: Analyse the following circuit: Given = 80, VCC = 12V, IC = 2mA, VC = 7.6VVBEVand VE = 2.4 VFind Q point VCE, RE, RB and RC Solution: VCE = VC – VE = 5.2V RE = VE / IE = VE / IC = 1.2 K Output KVL, VCC - ICRC - VCE – IERE = 0 IC = IE Thus, VCE = VCC - IC (RC + RE)
RC + RE = (VCC – VCE) / IC = 3.4 K RC = 2.2 K IB = Ic / β = 25 A Input KVL, VCC - IBRB - VBE – IERE = 0 IE = (+1) IB VCC – VBE = IB (RB + (+1) RE) RB + (+1) RE = (VCC – VBE) / IB RB = 452 K - (+1) RE RB = 354.8 K
8. A Ge transistor with β=60 is used in self-biasing circuit with VCC=16V, RC= 1.5 KΩ, VE=2V. If the quiescent point is to be VCE= 8V and IC=4 mA, find the values of R1, R2 and Re. (8Marks, June 2010)
9. For the circuit shown calculate IB, IC, VCE, VC, VE, VB. Assume β =100. (8M) (Dec 2012) 10. Find the values of resistors RB, RC, RE and the transistor gain β, for the self-bias circuit.
Given that IB= 40 A, IC= 4 mA, VE= 2 V, VCE = 12V and supply voltage VCC = 15V. Assume that the transistor used in the circuit is a silicon transistor. (5M) (July 2013)
11. Explain with a neat circuit diagram, voltage divider bias amplifier and also mention the importance of bypass capacitor. (06 marks, JUNE 2010)
Ans: Voltage divider bias Two methods of analysing a voltage divider bias circuit are: • Accurate method – can be applied to any voltage divider circuit • Approximate method – direct method, saves time and energy, can be applied in most of the circuits under some assumptions and approximation
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ADE Module-1 Notes
Accurate method • In this method, the Thevenin’s equivalent network for input side of the base terminal to be found. Input Loop
To find Rth ( Thevenin’s resistance):
From the above circuit, Rth = R1 parallel to R2 = R1 R2 / (R1 + R2)
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ADE Module-1 Notes
To find Vth( Thevenin’s Voltage):
From the above circuit, Vth = VR2 = (R2VCC) / (R1 + R2)
Thevenin’s equivalent circuit:
Input loop Applying KVL Vth – IB Rth – VBE - IERE = 0 IE= ( + 1) IB So, (Vth – VBE) = IB [ Rth +( + 1) RE ] IB = (Vth – VBE) / [ Rth +( + 1) RE ]
So, Ic = β IB = β ( Vth – VBE) / [ Rth +( + 1) RE ]
Output loop KVL to the output loop: VCC - ICRC - VCE – IERE = 0 IE IC Thus, VCE = VCC – IC (RC + RE)
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ADE Module-1 Notes
Problem 5 For the circuit given below, find IC and VCE. Given the values of R1= 39 KΩ, R2=3.9KΩ, RC= 4KΩ, RE =1.5KΩ, = 140 and VCC = 18V.Also draw the DC load Line.
Solution Considering accurate analysis: 1. Let us find Rth = R1R2 = R1 R2 / (R1 + R2) = 3.55KΩ 2. Then find Vth = VR2 = R2 VCC / (R1 + R2) = 1.64V 3. Then find IB IB = (Vth – VBE) / [Rth +( + 1) RE ] = 4.37A 4. Then find IC = IB = 0.612mA 5. Then find VCE = VCC – IC (RC + RE) = 12.63V 6. Draw DC load line and indicate Q point values on it.
Approximate analysis: Input Network
• The emitter resistance RE is seen as (+1) RE at the input loop Input resistance, Ri = (+1) RE • If Ri >> R2, then the IB << I2 through R2. • This means, Ri >> R2 or (+1)RE 10R2 or RE 10R2 • This makes IB 0 • Thus I1 = I2, so R1 and R2 can be considered as in series. Voltage divider can be applied to find the voltage across R2 (VB) VB = VCCR2 / (R1 + R2) VE is calculated as, VE = VB – VBE IE is calculated as, IE = VE / RE IE IC
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ADE Module-1 Notes
Output Loop: KVL to the output loop: VCC - ICRC - VCE – IERE = 0 IE IC Thus, VCE = VCC – IC (RC + RE) Problem 7 Given: VCC = 18V, R1 = 39kΩ, R2 = 3.9kΩ, RC = 4kΩ, RE =1.5kΩ and = 140. Analyse the circuit using approximate technique. Solution In order to check whether approximate technique can be used, we need to verify the condition, RE 10R2 Here, RE = 210 k and 10R2 = 39 k Thus the condition RE 10R2 satisfied Note: if RE 10R2 not satisfied, then accurate method has to be used. Another condition which can be given in the question for approximate method is IB << I2.
Thus approximate technique can be applied. 1. Find VB = VCCR2 / (R1 + R2) = 1.64V 2. Find VE = VB – 0.7 = 0.94V 3. Find IE = VE / RE = 0.63mA = IC 4. Find VCE = VCC – IC (RC + RE) = 12.55V
Load line analysis • Same as emitter bias
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ADE Module-1 Notes
12. Using the condition for voltage divider bias for the BJT amplifier circuit shown in the fig below, determine the terminal currents IB, IC and IE, the terminal voltage VCE. Draw the DC load line and mark the Q point on the IC versus VCE characteristics plot. (10M JULY 2011)
13. Explain Collector to base bias with emitter resistor with proper diagrams. (10 marks, Dec 2010) Ans: Collector to base bias or Feedback bias
Input Loop
Applying KVL to input loop: VCC – (ICRC - IBRB -VBE –IERE = 0 ICIB and IE = (+1) IB
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Solving for IB, IB = (VCC – VBE) / [RB + ( ( RC + RE)]
So, Ic = β IB = β (VCC – VBE) / [RB + ( ( RC + RE)] Output loop
KVL to the output loop: VCC – (IC+ IB) RC - VCE – IERE = 0 IE IC and IB 0 Thus, VCE = VCC – IC (RC + RE)
Load line analysis • Same as emitter bias
Problem : Given VCC = 10V, RC = 4.7k, RB = 250and RE = 1.2k. = 90.Analyze the circuit to find Q point. Also find Q-point if = 135. Solution:
Applying KVL to input loop: VCC – (ICRC - IBRB -VBE –IERE = 0 ICIB and IE = (+1) IB Solving for IB, IB = (VCC – VBE) / [ RB + ( ( RC + RE)] = ? IC = (IB ) = ? KVL to the output loop: VCC - ICRC - VCE – IERE = 0 IE IC VCE = VCC – IC (RC + RE) = ?
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With the same procedure: • IB = 8.89A • IC = 1.2mA • VCE = 2.92V
11. Explain Collector to base bias without emitter resistor with proper diagrams. (10 marks, JULY 2009) Ans: Collector to base bias or Feedback bias
Input loop Applying KVL to input loop: VCC – (ICRC - IBRB -VBE = 0 ICIB Solving for IB, IB = (VCC – VBE) / [RB + ( RC]
So, Ic = β IB = β (VCC – VBE) / [RB + ( RC] Output loop
KVL to the output loop: VCC – (IC+ IB) RC - VCE = 0 IB 0 Thus, VCE = VCC – IC RC Load line analysis • Same as fixed bias
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ADE Module-1 Notes
Problem: Determine the DC level of IB, VCE, VC, VB, VBC for the feedback bias network having RB=680 kRC =4.7K, VCC = 20 V, VBE= 0.7 V Solution:
Applying KVL to input loop: VCC – (ICRC - IBRB -VBE = 0 ICIB Solving for IB, IB = (VCC – VBE) / [RB + ( RC] = (20 – 0.7) / [680k + (120+1)(4.7k)] = ?
So, Ic = β IB =?
KVL to the output loop: VCC – (IC+ IB) RC - VCE = 0 IB 0 Thus, VCE = VCC – IC RC =?
VC = VCC – ICRC =? VB = VBE - VE= VBE = 0.7V VBC = VB – VC = 0.7V – 11.26V = - 10.56V Advantages
Fixed bias: 1. The operating point can be selected anywhere in the active region of the characteristics by simply changing the value of RB. Thus, it provides maximum flexibility in the design. 2. Simplest circuit since very small number of components are required
Emitter bias 1. The circuit has the tendency to stabilize operating point against changes in temperature and β-value. 2. As increases, IB reduces, maintaining almost same IC and VCE thus stabilizing the Q point against variations.
Feedback bias 1. As IC increases, voltage across RC increases, thus reducing IB and causing IC to reduce. 2. RB is used as feedback as well as for providing IB
Voltage divider bias 1. If the condition RE >>10R2, the voltage VB will remain fairly constant for changing levels of IC. VBE =VB – VE, as IC increases, VE increases, since VB is constant, VBE drops making IB to fall, which will try to offset the increases level of IC. 2. Most stable biasing circuit against variation in temperature or β 3. Most widely used
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ADE Module-1 Notes
Disadvantages: Fixed bias: 1. Thermal stability is not provided in the circuit. Thus Q-point is not maintained. 2. Since IB is already fixed, Ic depends on β which changes unit to unit and shifts the Q- point. Thus the stability is very poor. 3. Rarely used
Emitter bias In this circuit, to keep IC independent of β the following condition must be met:
this is approximately the case if
( β + 1 )RE >> RB. As β-value is fixed for a given transistor, this relation can be satisfied either by keeping RE very large or making RB very low. RE causes AC feedback (negative feedback) which reduces the voltage gain of the amplifier. If RE is of large value, voltage gain will reduce. If RB is low, a separate low voltage supply should be used in the base circuit. Using two supplies of different voltages is impractical.
Feedback bias 1. Collector to base resistance RB causes AC feedback (negative feedback) which reduces the voltage gain of the amplifier. This can be solved by adding a capacitor between base resistor and ground as shown:
Voltage divider bias 1. RE causes AC feedback (negative feedback) which reduces the voltage gain of the amplifier. This can be solved by adding a capacitor across RE, Known as Bypass capacitor CE.
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ADE Module-1 Notes
12. With a neat sketch, explain transistor as s switch. (6M) (Dec 2012) Ans: The application of transistors is not limited solely to the amplification of signals. Through proper design it can be used as a switch for computer and control applications. Can be employed as an inverter in computer logic circuitry.
Proper design for the inversion process requires that the operating point switch from cut-off to saturation along active region. 1. Initially we will assume that IC= 0 mA when IB = 0uA and VCE = VCEsat =0V. 2. When Vi = 5 V, the transistor will be “on” and the design must ensure that the network is heavily saturated by a level of IB resulting in the saturation level for the collector current for the circuit. The transistor resistance to Ic in saturation is nearly zero or very small, resulting in a short circuit across Vcc and ground. And hence all the current flows to ground leaving 0V across Vc. 3. For Vi = 0 V, IB = 0 μA, and since we are assuming that IC = ICEO = 0 mA. The transistor resistance is nearly infinity, acting like open circuit across Vcc and transistor ground. And all the current flows towards the output, leaving Vc= 5V.
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ADE Module-1 Notes
Maximum base current required to keep transistor in saturation is Ib(max) should 1.5 times greater than Ib High input voltage to keep the transistor in saturation VIH = IBRB+VBE
Transistor Switching Delays 1. td = delay time: Time required by transistor to increase the IC from the time input is applied to 10% of final value of IC. Reason: When base-emitter voltage is VBE is applied, the base current rises. The collector current however remains zero till VBE =0.7V. 2. tr = rise time: Time required by transistor to increase the IC from 10% to 90% of final value of IC. Reason: IC has to rise from cut off region to saturations region through active region. 3. ton = turn on time: ton = td + tr
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4. tS = storage time: Time required by transistor to fall from final value of IC to to 90% of final value of IC when input in removed(high to low) Reason: When the input is removed VBE = 0, the collector current doesn’t change since transistor is in saturation. Across its collector base junction electron flow is huge which cannot be removed instantly. Ic starts decreasing when the electron flow starts decreasing. This time delay is dominating and large as compared to other time delay. 5. tf = fall time: Time required by transistor to fall from 90% to 10 % of final value of IC when input in removed. Reason: Ic has to decrease from saturation region to cut off region through active region. 6. toff = turn off time: toff = ts + tf .
GENERAL INFO ABT FET
VTU Questions
Q1. What are the differences between BJT’s and FET’s? (5M) (July 2013)
BJT (Bipolar Junction Transistor) FET (Field Effect Transistor) 1. Current controlled device => input current Voltage controlled device => input IB controls output current IC voltage VGS controls output current ID
2. Bipolar device => Current due to both Unipolar device => Current due to electrons and holes carriers majority (either electrons and holes) carriers 3. Output IC changes linearly with change in Output ID changes non- linearly with input IB change in input VGS 4. Input resistance less than FET Input resistance more than BJT In range of KΩ In range of MΩ
5. Construction size more than FET Construction size smaller than BJT
6. Poor thermal stability Better thermal stability
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7. Highly sensitive to changes in the input Less sensitive to changes in the input signal signal 8. Effected by radiation Not Effected by radiation
9. Noisy due to carriers crossing two junctions Less noisy since no junction
10. Better gain than FET Less gain
11. Only Two types=> PNP and NPN Many types => MOSFET, CMOS, FET etc Q2. Explain the VI characteristics of N-channel JFET and define various conditions. (8M)(Dec 2012)
Ans: JFET – Junction Field Effect Transistor
Construction: The N-channel JFET has an N-type silicon bar, referred to as the channel has two P-type silicon material diffused on the opposite sides forming P-N junctions The two P material are connected internally to form a common terminal called the gate terminal The two ends of the N- channel gives one terminal called the source S and the other drain D. Source. The terminal through which the majority carriers enter the channel, is called the source terminal S Drain. The terminal, through which the majority carriers leave the channel, is called the drain terminal D and the conventional current leaving the channel at D is
designated as ID.
The drain-to-source voltage is called VDS, and is positive if D is more positive than source S Gate. There are two internally connected heavily doped impurity regions to create
two P-N junctions. These impurity regions are called the gate G. A voltage VGS is applied between the gate and source in the direction to reverse-bias the P-N junction.. Channel. The region between the source and drain, sandwiched between the two gates is called the channel and the majority carriers move from source to drain through this channel.
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Note: Arrow going inside towards the gate
N- channel JFET construction N-channel JFET Symbol
Operation of N- channel JFET
1. When VGS = 0 Volts and VDS = +ve V:
This creates small depletion region between p-gate and n-channel since VGS =0 The electrons (which are the majority carriers in N-channel) flow from Source S to
Drain D whereas conventional drain current ID flows through the channel from D to S.
since ID increases linearly with increase in VDS, this is known as Ohmic region of FET
As VDS made more positive, the depletion region increases which decreases the size of the n-channel. Depletion layers width is more near Drain than Source.
Flow of electrons slows down and become constant, so ID becomes constant This is known as Pinch Off condition
The VDS value at this condition is known as VP = pinch off voltage For the case V =0, the drain current at pinch-off is called the drain-source saturation GS current, I . DSS When ID becomes constant it is known as saturation region or active region.
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a. ID increases for small values of VDS b. Pinch off condition
2. When VGS = -ve V and VDS = +ve V: the depletion region widths are increased since VGS = negative voltage. The increase in the depletion regions reduces the channel thickness, which decreases
its resistance. The net result is that drain current ID is reduced. So, the JFET will pinch-off at a lower voltage (Vp).
3. When VGS < - Vp
For VGS < -Vp, no conductive path between drain and source, ID =0 This is known as cut off region.
This VGS is known as VGS(OFF) = -VP
Also, at high levels of VDS the JFET reaches a breakdown situation. ID will increases uncontrollably if VDS > VDS max.
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Transfer Characteristics Output Characteristics
The transfer Characteristics is also known as a transconductance curve.
NOTE:
1. In a JFET, the relationship (Shockley’s Equation) between VGS (input voltage) and ID (output current) is used to define the transfer characteristics
2 VGS ID = I DSS 1 - VP
As a result, FET’s are often referred as square law devices
Q3. Explain the VI characteristics of P-channel JFET and define various conditions. Ans:
Construction: explanation similar to N-Channel FET except In P-channel FET: channel is of P type and gate of N type material
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Note: Arrow going outside from the gate
P- channel JFET construction P-channel JFET Symbol
Operation:
P-Channel JFET operates in a similar manner as the N-channel JFET except the voltage polarities and current directions are reversed
When VGS = 0 and VDS = -ve V : ID due to holes of P channel and flows from source to drain, pinch off condition similar to N-channel
When VGS = +ve V and VDS = -ve V : ID decreases
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Q4. With the help of neat figures, explain the construction and characteristics of N- Channel depletion MOSFET. (10M) (July 2013)
Ans: N-Channel Depletion MOSFET (DE- MOSFET)
Construction: It consists of a highly doped P-type substrate Two blocks of heavily doped N+ material forming the source and drain. An N-channel between the source(S) and drain (D).
A thin layer of SiO2 dielectric is grown over the entire surface Metal contact are provided for drain and source On the surface area between drain and source, a metal contact for gate (G) is provided.
Si02 layer results in an extremely high input impedance. The P-substrate may have an additional terminal connection called SS
Symbol
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ADE Module-1 Notes
Operation: DE-MOSFET operates in two modes: 1. Depletion mode 2. Enhancement mode
1. When VGS =0 and VDS= +ve: Zero Bias Electrons of N channel moves towards Drain (+ve) causing current ID to flow between drain to source.
As VDS increases the channel width at drain reduces due to depletion of electrons which
cause ID to become constant. This is known as pinch off condition
The voltage known as VP = pinch off voltage and the constant current known as IDSS
2. When VGS = -ve and VDS= +ve: Depletion mode the gate repels some of the negative charge carriers out of the N-channel to recombine with holes of P-substrate
Due to recombination the ID current value reduces.
As VDS increases the channel width at drain reduces due to depletion of electrons which
cause ID to become constant. With increase in negative voltage at the gate, the drain current decreases.
Since the ID is decreasing, this mode of operation is referred as depletion-mode
3. When VGS = +ve and VDS= +ve: Enhancement mode Gate (+ve) attracts the negative charge (minority) carriers from the P-substrate to the N- channel, increasing the carriers in N-channel. Thus it reduces the channel resistance and increases the drain-current.
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ADE Module-1 Notes
The more positive the gate is made, the more drain current flows.
Since ID is increasing, this mode of operation is referred as enhancement-mode
Characteristics :
In Depletion MOSFET operation:
When VGS = 0V, ID = IDSS
When VGS < 0V, ID < IDSS => depletion mode
When VGS > 0V, ID > IDSS=> enhancement mode
The formula used to plot the Transfer Curve, is:
2 VGS ID = I DSS 1 - VP
Transfer characteristics Output characteristics
Q5. With the help of neat figures, explain the construction and characteristics of P-Channel depletion MOSFET.
Ans:
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ADE Module-1 Notes
Construction: Same terminals as N- Channel DE-MOSFET. A P-channel DE-MOSFET is constructed like an N-channel DE-MOSFET, starting with an N-type substrate and diffusing P+ drain and source and connecting them internally by a P-doped channel region.
Operation: In P-channel DE-MOSFET operation:
When VGS = 0V, ID = IDSS
When VGS = +ve, ID < IDSS => depletion mode
When VGS = -ve, ID > IDSS=> enhancement mode
Q6. Explain the working of N-channel E-MOSFET with neat diagram. Explain with the output characteristics of the same. (10M)(Jun 2012)
Ans: N-channel Enhancement-MOSFET Construction: It consists of a highly doped P-type substrate
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ADE Module-1 Notes
Two blocks of heavily doped N+ material forming the source and drain. No channel between the source(S) and drain (D).
A thin layer of SiO2 dielectric is grown over the entire surface Metal contact are provided for drain and source On the surface area between drain and source, a metal contact for gate (G) is provided.
Si02 layer results in an extremely high input impedance. The P-substrate may have an additional terminal connection called SS
Operation: E-MOSFET works only in enhancement mode
1. When VGS =0 and VDS= +ve:
Since no channel between drain and source, ID = 0
2. When VGS =-ve and VDS= +ve: Since no channel between drain and source, ID = 0
3. When VGS =+ve and VDS= +ve: The negative (i.e. minority) charge carriers within the substrate are attracted to the
positive gate since gate is positive and accumulate close to the SiO2 layer. As the gate voltage is increased, more and more electrons accumulate under the gate. Since these electrons cannot flow across the insulated layer of silicon dioxide to the gate, so they accumulate at the surface of the substrate just below the gate. These accumulated minority charge carriers N -type channel stretching from drain to source. When this occurs, a channel is induced by forming N-type channel.
The drain current ID starts flowing. The strength of the drain current depends upon the channel resistance i.e. depends upon the number of charge carriers attracted to the positive gate.
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ADE Module-1 Notes
Thus drain current is controlled by the gate potential. Since the conductivity of the channel is enhanced by the positive bias on the gate so this device is also called the enhancement MOSFET or E- MOSFET.
The minimum value of gate-to-source voltage VGS that is required to form the channel is
termed the gate-to-source threshold voltage VT.
VGS < VT, ID = 0 => E-MOSFET is OFF
VGS >VT, ID flows => E-MOSFET is ON
Parameters: The ID of E- MOSFET is given as: 2 ID = k (V GS - V T ) where VT = threshold voltage or voltage at which the MOSFET turns on.
ID(on)
k= 2 (VGS(ON) - V T ) Characteristics:
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ADE Module-1 Notes
Q6. Explain the working of P-channel E-MOSFET with neat diagram. Ans:
Construction: Same terminals as N- Channel E-MOSFET. A P-channel E-MOSFET is constructed like an N-channel E-MOSFET, starting with an N-type substrate and diffusing P+ drain and source without any channel.
Operation: The working of P-channel Enhancement mode MOSFET is similar to the n-channel except that the voltage polarities and current directions are reversed. When VGS = 0V, ID = 0
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ADE Module-1 Notes
When VGS = +ve, ID =0
When VGS = -ve, ID increases => enhancement mode
VGS > VT, ID = 0 => E-MOSFET is OFF
VGS
Q7. What are the differences between JFET’s and MOSFET’s? (5M) (July 2013)
FET (Field Effect Transistor) MOSFET(Metal Oxide Semiconductor FET) 1. No Insulation layer SiO2 layer present
2. Operates only in depletion mode Operates in depletion and / or enhancement mode 3. Fabrication process is complex Fabrication process is simple and easy
4. Input resistance is less than MOSFET Input resistance is more than FET Range- 1GΩ to 10 GΩ Range- 1013Ω to 1015Ω 5. Drain resistance more than MOSFET Drain resistance less than FET Range- 100 KΩ to 1 MΩ Range- 1KΩ to 50 KΩ
6. Leakage current IG more in range 10 ηA to Leakage current IG less in range 10 pA to 100 ηA 100 pA 7. Not widely used Widely used
8. Fabricated using semiconductor bar which Fabricated on a semiconductor substrate. acts as a channel.
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ADE Module-1 Notes
Q10. Discuss CMOS inverter with a neat circuit diagram along with the transfer characteristics. (06 marks, Dec 2010, June 2010) Ans: CMOS- Complementary MOSFET
It has complementary pair of P-channel and N-channel E-MOSFET Advantages: high input impedance, low power consumption, requires very less space compared to transistor Used in designing Logic circuits
Construction: N-channel induced on the right MOSFET: has P-well with N+ drain and N+ source and P+ substrate P-channel induced on the left MOSFET: has N-well with P+ drain and P+ source and N+ substrate
CMOS as Inverter: 1. When Vin = 0, logic LOW
P-channel VGS = -ve => Q2 ON
N-channel VGS = 0 => Q1 OFF
Q2 offers low impedance path for VDD and Q1 offers high impedance.
So, Vout = VDD => Logic High 2. When Vin = high voltage, logic HIGH
P-channel VGS = +ve => Q2 OFF
N-channel VGS = -ve => Q1 ON Q1 offers low impedance path and Q2 offers high impedance.
So, Vout = 0 => Logic Low
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ADE Module-1 Notes
Q11. Mention the applications of FET. (Study VVR and any other three applications)
ANS: FETs has many applications. 6 of them are:
1. FET as amplifiers:
FET are less noisy than BJT Signal level at the TV and radio receiver input is usually very low due to which it should have low noise amplifier. So they are used as front end of radio and TV receivers FET in Common Drain configuration has very high impedance and low output impedance So they are used as buffer amplifier for matching high impedance source to low impedance load Used in RF amplifiers at very high frequencies.
2. FET as Analog switch:
Dept. of CSE, NHCE Page 39
ADE Module-1 Notes
1. When switch is open
VGS (OFF) is not part of the circuit. The gate is shorted to the source.
The voltage across gate and source VGS = 0, the FET goes to saturation
In saturation region, FET provides constant ID which provides Vout So, FET works as closed switch 2. When switch is closed
VGS (OFF) is part of the circuit.
The voltage across gate and source VGS = VGS(OFF) , the FET goes to cut off region
In cut off region, ID =0 which makes Vout =0 So, FET works as open switch
3. FET as Multiplexer:
An analog multiplexer, a circuit that steers one of the input signals to the output line Each FET acts as a single-pole single-throw switch. V1, V2, V3 are control or selection signals connected to gate of the FETs.
When control signal= VGS (OFF) => FET is OFF
When control signal= 0 => FET is ON
All input signals are blocked by making all control signals = VGS (OFF) By making any control voltage equal to zero, one of the inputs can be transmitted to the output.
For instance, when V2 is zero, the signal obtained at the output will be sawtooth.
Similarly when V3is zero, the output signal will be square-wave one. Normally, only one of the control signals is zero.
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ADE Module-1 Notes
4. FET as Current Limiter:
In normal condition, FET is working in ohmic region. All the supply voltage appears across the load. When the load current tries to increase to an excessive level (may be due to short-circuit or any other reason), the excessive load current forces the JFET into saturation region. The JFET now acts as a current source and prevents excessive load current.
5. FET as VVR: Another wide application of a FET is that it can be used as a voltage variable resistor (VVR). When the FET is operated in ohmic region, the channel between drain and source of a FET acts as a simple resistor.
In this region drain-to-source resistance RDS can be controlled by varying the bias
voltage VGS. As VGS increases, resistance increases , so ID decreases When the FET is biased to be used in this region of operation, the resistance of the device can be controlled with the gate voltage and hence the name voltage variable resistor or voltage dependent resistor (VDR). The drain curves as shown in figure extend on both sides of the origin. So the resistance of the device can be controlled with the gate voltage in positive and negative cycle. This means that a FET can be employed as a voltage-variable resistor for small ac signals. This finds a very good application in most of the electronic and communication circuits.
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ADE Module-1 Notes
FET as voltage variable resistor (VVR) is used in automatic gain control of an amplifier in a communication receiver or in any electronic circuit that requires a constant output voltage.
6. FET as oscillator:
JFET can incorporate the amplifying action as well as feedback action. It, therefore, acts well as a phase shift oscillator. The high input impedance of FET is especially very valuable in phase-shift oscillators in order to minimize the loading effect.
RC phase shift oscillator Pierce oscillator
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ADE Module-1 Notes
1. What is an Op-Amp? Draw its equivalent diagram. Ans: Operational Amplifiers • Usually Called Op Amps • An amplifier is a device that accepts a varying input signal and produces a similar output signal with larger amplitude. • Usually connected so part of the output is fed back to the input. (Feedback Loop) • Most Op Amps behave like voltage amplifiers. • They are the basic components used to build analog circuits. • The name “operational amplifier” comes from the fact that they were originally used to perform mathematical operations such as integration and differentiation. • Integrated circuit fabrication techniques have made high-performance operational amplifiers very inexpensive in comparison to older discrete devices. • Vo = A ( non-inverting input – inverting input)
Thevenin’s equivalent circuit: Op-amp has different stages internally This stages can be represented as Thevenin’s equivalent model of Op-amp.
Represented by: Ad= open loop differential voltage gain + - vd = (v -v ) = differential input signal voltage Ri= amplifier input resistance Ro= amplifier output resistance
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ADE Module-1 Notes
Table 1.2. Operational Amplifier Parameters—(Ideal and Typical Values)
S. No. Parameter Symbol Ideal Value Typical Value Units
1. Input offset voltage Vio 0 100 μV
2. Input offset current Iio 0 100 nA
3. Input bias current Io 0 500 nA
4. Input resistance Ri ∞ 2 MΩ
5. Output resistance Ro 0 100 Ω
6. Common Mode Rejection Ratio CMRR ∞ 90 dB
7. Power Supply Rejection Ratio PSRR 0 150 μV/V
8. Slew Rate SR 0 0.01 V/μ sec 9. Voltage Gain Av ∞ 104 to 106 No unit
. Explain with a neat diagram comparator with non-zero reference voltage for positive and negative references. (10 Marks) (July 2009)
ANS:
Comparator with positive (+Vcc) reference Vref = Vcc R2 R1 + R2 When Vi>Vref , V0 = +Vsat When Vi< Vref , V0 = - Vsat
Comparator with negative (-Vcc) reference Vref = - Vcc R2 R1 + R2 When Vi>Vref , V0 = +Vsat When Vi Dept. of CSE, NHCE Page 44 ADE Module-1 Notes 10. With relevant formulas, neat diagram and waveform explain Op-Amp Schmitt trigger. (10M) (DEC 2012) 11. For the inverting mode Schmitt trigger shown in figure. Calculate upper and lower trigger point. ANS: Schmitt trigger / Comparator with hysteresis When V0 = +Vsat, Vx = Vsat R1 R1 + R2 Vin >Vx, Vo = - Vsat When Vo = - Vsat, Vx = - Vsat R1 R1 + R2 Vin Upper Trip Point: (Upper Trigger Point / Upper Threshold point) VUTP = 2 Vsat R1 R2 Lower Trip Point: ( Lower Trigger Point / Lower Threshold point) VLTP = - 2 Vsat R1 R2 Dept. of CSE, NHCE Page 45 ADE Module-1 Notes Non inverting type: 12. Explain the working of window comparator with diagram. Ans: Has 2 reference voltages : Lower trip point(LTP) & Upper trip point(UTP) When Vi < LTP, output at A1 => +Vsat output at A1 => -Vsat Diode D1 = Forward biased & D2 = Reverse biased Vo = +Vsat Dept. of CSE, NHCE Page 46 ADE Module-1 Notes When Vi > UTP, output at A1 => -Vsat output at A1 => +Vsat Diode D1 = Reverse biased & D2 = Forward biased Vo = +Vsat When LTP < Vi < UTP, output at A1 => -Vsat output at A1 => -Vsat Diode D1 = D2 = Reverse biased Vo = Zero 13. What are active filters? ANS: Filters: circuits which passes only a specified range of signal frequencies and cut-off or attenuate frequencies outside this range. Two types: passive filters and active filters. Passive filters: uses only passive elements such as resistors, capacitors and inductors. Active filters: uses active elements such as transistors, Op-Amp with resistors, capacitors and inductors. Active filters can be of different order depending upon number of capacitors used: First Order Filters - 1 capacitor used Second Order filters – 2 capacitors used 14. Explain first order active filter with diagrams. ANS: 1. Low Pass filter: Since Xc = 1 2π f C At low frequencies, Xc> R Vo = Vi At high frequencies, Xc< R Vo = Zero Dept. of CSE, NHCE Page 47 ADE Module-1 Notes 2. High Pass filter: Since Xc = 1 2π f C At low frequencies, Xc> R Vo = Zero At high frequencies, Xc< R Vo = Vi fc = 1 2π RC 15. Explain second order active filters with diagram. ANS: 1. Butterworth filter: Also called maximally flat filter. When Z1 = Z2 = R and Z3 = Z4 = C =>second order low pass filter When Z1 = Z2 = C and Z3 = Z4 = R =>second order high pass filter Dept. of CSE, NHCE Page 48 ADE Module-1 Notes fc = 1 Av = 1 + R2 2π RC R1 21. With neat figure and relevant waveforms explain the working of relaxation oscillator circuit using Op-Amp. (8M)(July 2013) 22. Explain the principle of relaxation oscillator to generate rectangular output. Draw a neat circuit diagram and waveform. (08 Marks) (July 2009) ANS: Relaxation Oscillator: (Same as LAB experiment) . Used to generate non-sinusoidal output . Output time period depends upon charging of C (RC value) Working: . Let initially output is at +Vsat . V1 = Vsat R1 R1 + R2 . V1 > V2, Vo = +Vsat . C starts charging towards +Vsat . As C starts charging, V2 starts increasing . When V2 > V1, V0 = -Vsat . V1 = - Vsat R1 R1 + R2 . C starts discharging . As C is discharging, V2 decreasing . When V1> V2, Vo = +Vsat . Cycle repeats Time period of output waveform, T= 2 RC ln 1+β 1- β β = R1 / (R1 + R2) Dept. of CSE, NHCE Page 49 ADE Module-1 Notes NOTE: Relaxation oscillator can be made to generate triangular waveform if cascaded in series with an Integrator circuit. Dept. of CSE, NHCE Page 50