ADE Module-1 Notes Module-1 Syllabus: Electronic devices and applications -1 : Diodes, Clippers and Clamper, Transistor, Transistor Biasing, Transistor as a switch, BJT Vs FET, JFET, MOSFETs, FET 9 applications, CMOS Device, Ideal vs practical OP-AMP, Comparator, Active Filters, Relaxation Oscillator Some basic information about transistor Transistor or BJT (Bipolar Junction Transistor) – • Invented in 1948 by Bardeen, Brattain and Shockley • Contains three adjoining, alternately doped semiconductor regions: Emitter (E), Base (B), and Collector (C) • The middle region, base, is very thin • Emitter is heavily doped compared to collector. So, emitter and collector are not interchangeable. • Two types- NPN and PNP • 3 types of Configuration- Common emitter, Common collector and Common Base • Most commonly used configuration – Common emitter as it provides good voltage and current gain in amplification circuits Some relationships • VBE = 0.7V • IE = IB IC • IE = (+ 1) IB IC • IC = IB Q-Point (Static Operation Point) • The intersection of the dc bias value of IB with the dc load line determines the Q-point. • It is desirable to have the Q-point centred on the load line. Why? • When a circuit is designed to have a centred Q-point, the amplifier is said to be midpoint biased. • Midpoint biasing allows optimum ac operation of the amplifier and good DC stability. • The values of the parameters IB, IC and VCE together are termed as ‘operating point’ or Q (Quiescent) point of the transistor. VTU Questions 1. What is Biasing of a transistor and what is its requirement? (4 Marks, Dec 2008) 2. Give the four factors required for biasing circuit. (04 Marks, Dec 2010) Ans: Biasing - • The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system. • In fact, the amplifier increases the strength of a weak signal by transferring the energy from the applied DC source to the weak input ac signal • The analysis or design of any electronic amplifier therefore has two components: 1. The dc analysis and 2. The ac analysis Dept. of CSE, NHCE Page 1 ADE Module-1 Notes • During the design stage, the choice of parameters for the required dc levels will affect the ac response. What is biasing circuit? • Once the desired dc current and voltage levels have been identified, a network must be constructed that will establish the desired values of IB, IC and VCE, Such a network is known as biasing circuit. • A biasing network has to preferably make use of one power supply to bias both the junctions of the transistor. Four factors required for biasing circuit 1. Emitter base (VBE) junction should be forward bias and Collector base junction should be reverse bias. VBE= 0.7V for Silicon(Si), VBE= 0.3V for Germanium(Ge) 2. Collector- Emitter voltage VCE > V CE(Sat) VCE (Sat)= 1V for Silicon(Si) and V CE(Sat)= 0.5V for Germanium(Ge) 3. Collector current IC when no input signal is applied = IC(Max) due to input signal 4. Maximum ratings of IC(Max) , VCE(Max) and PD(Max) should not be reached by the circuit. 3. Discuss with neat sketches, the relation of operating point of transistor for following: a) Near saturation region b) Near cut off region c) at the centre of active region (8M)(Dec 2011) Ans: Three operating regions S.no Junction bias condition Mode Emitter-base Collector-base Usage 1. Active / Linear Forward Reverse Used for amplification 2. Saturation Forward Forward Used as switch turn ON 3. Cut-off Reverse Reverse Used as switch turn OFF Output of transistor during three operating regions • Cut off: VCE = VCC, IC 0 • Active or linear: VCE VCC/2, IC IC max/2 • Saturation: VCE 0, IC IC max From the output characteristics of CE amplifier 1. Point A, near cut off region: No proper bias to both junction => Transistor in Cut Off region => VBE= 0, IC=0 => no amplification. So point A cannot be Q point. 2. Point B, in active region: middle of Active region => both junction properly biased => linear amplification with good voltage and current swing. So, good Q-point. 3. Point C, near saturation region: since near saturation => non- linear amplification(IC not linear with change in Vce). So, not good as Q-point. Dept. of CSE, NHCE Page 2 ADE Module-1 Notes 4. Point D, near PD (Max): since near to Power Dissipation curve=> voltage swing is limited. So, not good as Q point. Active region is bounded by: 1. Saturation region 2. I C (Max) 3. Cut off Region 4. P D (Max) Types of Biasing circuits: 1. Fixed bias / base bias 2. Emitter bias / self-bias 3. Collector to base bias / feedback bias 4. Voltage divider bias / Universal bias Some general equation will be required to solve numerical: 1. VE = IERE 2. VC = VCE + VE 3. VB = VBE + VE 4. VBC= VB – VC Dept. of CSE, NHCE Page 3 ADE Module-1 Notes 4. Explain transistor in its fixed bias mode with relevant expression. (6 M)(Dec 2012) 5. Explain with a neat diagram and dc equivalent circuit, the working of base bias amplifier. (08 marks, Dec 2009) Ans- Fixed bias: The simplest dc bias configuration. Also known base bias DC Analysis For dc analysis, open all the capacitance. So the dc circuit becomes as given INPUT LOOP Applying KVL to the input loop: VCC -IBRB – VBE = 0 • From the above equation, deriving for IB, we get, IB = [VCC – VBE] / RB Dept. of CSE, NHCE Page 4 ADE Module-1 Notes So, Ic = β IB = β [VCC – VBE] / RB OUTPUT LOOP Applying KVL for the output loop: VCC – ICRC – VCE = 0 Thus, VCE = VCC – ICRC Load line analysis The input loop KVL equation is not used for the purpose of analysis. The output characteristics of the transistor used in the given circuit and output loop KVL equation is made use of. • The method of load line analysis is as below: 1. Consider the equation VCE = VCC – ICRC ------------------------------(1) This relates VCE and IC for the given IB and RC 2. To find point A, put Ic = 0 in the equation (1) VCE = VCC This gives the coordinates (VCC, 0) on the x axis of the output characteristics. 3. To find point B, put Vce = 0 in the equation (1) 0 = VCC – ICRC IC = VCC / RC Thus giving the coordinates of the point as (0, VCC / RC). 4. The two extreme points so obtained are joined to form the load line. 5. The point where load line intersects the given IB => Q – point or operating point Dept. of CSE, NHCE Page 5 ADE Module-1 Notes Problem 1– Given the fixed bias circuit with VCC = 12V, RB = 240 K, RC = 2.2 KVBE = 0.7Vand = 75. Determine the values of operating point. Solution: Equation for the input loop is: VCC -IBRB – VBE = 0 IB = [VCC – VBE] / RB , Thus substituting the given values in the equation, we get IB = 47.08μA IC = IB = 3.53mA Equation for the output loop is: VCC – ICRC – VCE = 0 VCE = VCC – ICRC = 4.23V Q-point = (Vce, Ic) = (4.23V, 3.53mA) Problem 2– The fixed bias circuit has VCC = 12V, IB = 45μA, VCE = 6.5V, VBE = 0.7Vand = 50. Determine the values of resistors. Solution: IC = IB = 2.25 mA Equation for the input loop is: VCC -IBRB – VBE = 0 RB = [VCC – VBE] / IB = 251.11 K Equation for the output loop is: VCC – ICRC – VCE = 0 RC= (VCC – VCE) / IC = 2.44 K Dept. of CSE, NHCE Page 6 ADE Module-1 Notes 6. Explain the effects of collector resistor, base current and supply voltage on the operating point of a fixed bias circuit. Which is the ideal position for an operating point on the BJT fixed bias transistor circuit? Explain the above with neat diagrams. (10 M)(June 2012) Ans: Q point variation 1. Due to collector resistor Rc: • As RC is varied, the Q point shifts to left or right along the same IB line since the slope of the line varies. • As RC increases, slope reduces which results in shift of Q point to the left meaning no variation in IC and reduction in VCE. 2. Due to base current IB: • As IB is varied, the Q point shifts accordingly on the load line either up or down depending on IB increased or decreased respectively. Dept. of CSE, NHCE Page 7 ADE Module-1 Notes 3. Due to supply voltage Vcc: • As VcC is varied, the Q point shifts to left or right along the same IB line since the slope of the line varies. • As Vcc increases, slope increases which results in shift of Q point to the right meaning increasing IC and VCE. 7. Explain emitter bias circuit. (06 marks, Dec 2008) Ans: Emitter Bias • The emitter bias is a biasing circuit very similar to fixed bias circuit with an emitter resistor added to it. • Including an emitter resistor in the fixed bias circuit improves the stability of Q point. Dept. of CSE, NHCE Page 8 ADE Module-1 Notes DC Analysis For dc analysis, open all the capacitance. So the dc circuit becomes as given Input loop Writing KVL around the input loop we get, VCC - IBRB - VBE – IERE = 0 IE = (+1) IB VCC - IBRB - VBE - (+1) IBRE = 0 VCC – VBE = IB (RB + (+1) RE) Solving for IB: IB = (VCC – VBE) / [(RB + (+1) RE)] So, Ic = β IB = β (VCC – VBE) / [(RB + (+1) RE)] Dept. of CSE, NHCE Page 9 ADE Module-1 Notes Output loop: Collector – emitter loop Applying KVL, VCC - ICRC - VCE – IERE = 0 IC = IE Thus, VCC - ICRC - VCE – ICRE = 0 VCC - IC (RC + RE) - VCE = 0 VCE = VCC - IC (RC + RE) Load line analysis • The method of load line analysis is as below: 1.