United States Patent (19) 11 Patent Number: 5,046,038 Briggs Et Al
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United States Patent (19) 11 Patent Number: 5,046,038 Briggs et al. 45 Date of Patent: Sep. 3, 1991 54 METHOD AND APPARATUS FOR described which first comprises approximating the PERFORMING DIVISION USINGA short reciprocal of the divisor. A reciprocal bias adjust RECTANGULARASPECTRATO ment factor is added to the approximation and the cor MULTIPLER rectly biased short reciprocal is multiplied by a prede 75 Inventors: Willard B. Briggs, Carrollton; David termined number of the most significant bits of the divi W. Matula, Dallas, both of Tex. dend and the product is truncated to generate a first quotient digit value. The multiplication takes place in a 73) Assignee: Cyrix Corporation, Dallas, Tex. multiplier array having a rectangular aspect ratio with 21 Appl. No.: 389,051 the long side having a number of bits at least as large as the number of bits required for the divisor. The short 22 Filed: Aug. 2, 1989 side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits Related U.S. Application Data required for a single quotient digit value, which is also 63 Continuation-in-part of Ser. No. 376,753, Jul. 7, 1989, determined to be the number of bits in the short recipro abandoned. cal. The quotient digit value is multiplied by the full 51 Int. C.’................................................ G06F 7/52 divisor and the exact product is subtracted from the 52 U.S. Cl. .................................................... 364/765 dividend to yield an exact partial remainder. The de (58) Field of Search ........................ 364/765, 766, 767 scribed steps are repeated to serially generate quotient digit values with exact partial remainders with the pre (56) References Cited ceding partial remainder taking the place of the divi U.S. PATENT DOCUMENTS dend. The quotient digit values are accumulated to 3,591,787 7/1971 Freiman et al...................... 364/767 yield a complete quotient. The complete quotient is 3,828,175 8/1974 Amdahl et al. ....... ... 364/765 decremented and the remainder recalculated if the final 4,466,077 8/1984 Iannucci et al. .................... 364/766 partial remainder is negative, yielding the full precision Primary Examiner-David H. Malzahn unique quotient and non-negative remainder pair. Attorney, Agent, or Firm-Baker & Botts 57) ABSTRACT A method and apparatus for performing division is 26 Claims, 2 Drawing Sheets UPER ARRAY U.S. Patent Sep. 3, 1991 Sheet 1 of 2 5,046,038 INALIZE PARTAL REMANDER Z get X DETERMINE SHORT RECIPROCAL LOOK-UP y' Ray TO N+k BITS ACCURACY COMPUTE: y' = y' (2-yy) NEXT QUOTENT DG VALUE q CE Z R COMPUTE: y" y" (2-yy") ACCUMULATE QUOTIEN Q (= Q+2N COMPUTE: R y" 6. CAL CULATE PARTAL TRUNCATED TO N+k REMANDER BITS ACCURACY z e (z - q; y)2 FIG. 2 CORRECT QUOTENT BASED ON REMANDER FIG. 1 SHORT RECIPROCAL = 1.28 FIG. 4 46 61 8 79 12 REM x SHORT RECIPROCAL = 78 47 31 36 57 48 37 50 = 46 81 57 92 -36 09 76 26 47 72 1 50 = 61 08 30 72 -47 86 85 91 -4 74 41 00 = - 18 87 24 48 -(-14 12 51 58) -61 89 42 00 = -79 22 45 76 -(-61 99 37 49) O9 95 49 00 = 12 74. 22 72 09 41 67 72 53 81 28 U.S. Patent Sep. 3, 1991 Sheet 2 of 2 5,046,038 87 ADDER 8 7 SHIFTER 5,046,038 1. 2 rior to the SRT division, but still contains a major disad METHOD AND APPARATUS FOR PERFORMING vantage. The Newton-Raphson division requires two DVISION USINGA RECTANGULAR ASPECT full precision multiplies which are time consuming. The RATIO MULTIPLIER Convergence Division Method, which is effectively a variation of the Newton-Raphson division process, re RELATED APPLICATIONS quires similar steps to remove the indeterminacy in the This application is a continuation-in-part of Appli error to effect IEEE standard roundings. cants' co-pending U.S. patent application Ser. No. Therefore, a need has arisen for a system which uses 07/376,753, filed July 7, 1989 entitled "Method and a division process which results in an exact result which Apparatus for Performing Division Using a Rectangu 10 can be used for appropriate IEEE standard rounding lar Aspect Ratio Multiplier' now abandoned. procedures, but which is less time consuming than and TECHNICAL FIELD OF THE INVENTION more efficient than previously developed systems. SUMMARY OF THE INVENTION . This invention relates in general to the field of per 15 forming mathematical functions using electronic de In accordance with the present invention, a division vices. More specifically, the present invention relates to method and system are provided which substantially a method and apparatus for performing the division eliminate or reduce disadvantages and problems associ function in a system using a rectangular aspect ratio ated with prior arithmetic techniques used to perform multiplier circuit. the division function. BACKGROUND OF THE INVENTION The division system of the present invention first The arithmetic unit is one of the most important com determines an approximation of the reciprocal of the ponents of any integrated electronic data processing divisor, hereinafter referred to as the short reciprocal, system. Arithmetic units perform a wide variety of accurate to a number of bits needed to substantially fill mathematical functions upon operands which are trans 25 the smaller side of a rectangular aspect ratio multiplier mitted from other portions of an integrated system. The (hereinafter sometimes also referred to as "rectangular basic addition, subtraction and multiplication functions multiplier') circuit. The division system then develops are quickly and efficiently performed in arithmetic units quotient digit values corresponding to a large radix. today. However, presently available techniques for This large radix is substantially equal to the number of performing division functions have not been completely bits of the smaller side of the rectangular multiplier. The satisfactory with respect to efficiency and speed. precision required for the short reciprocal is limited to A common method of performing division in arith one digit in this large radix plus appropriate guard bits. metic systems presently available is through the use of commonly known SRT procedures. In SRT division, Importantly, the error in the short reciprocal can be left the digits of the quotient are developed serially a certain 35 indeterminate as only a bound on the error of the recip number of bits at a time using table look-ups or pro rocal value is needed for the process, thus eliminating a grammable logic arrays (PLA) to logically determine time consuming feature of the Newtow-Raphson with each quotient digit as a function of the leading bits of IEEE standard rounding process. Each quotient digit the partial remainder and divisor. An exact new partial value is determined by multiplying the short reciprocal remainder is calculated after each digit so that the pro 40 of the divisor by the partial remainder in the rectangular cess may continue indefinitely. A key disadvantage of multiplier and appropriately truncating the result. The SRT division is that because of the limitations of the quotient digit values are determined serially with exact look-up table size, no more than three or four bits per partial remainders. Each quotient digit value deter quotient digit can be calculated in any one step. Thus, mined by the technique is one of at most two possible the division operation using the SRT system takes many 45 values in the large radix system where the new partial steps or iterations. In effect the time required for SRT remainder corresponds to less than a unit of value in the division grows linearly with the number of bits of preci quotient digit determined. Such partial remainders are sion, and becomes relatively slower in comparison to then sufficient for simplified implementation of all certain approximation techniques for higher precision IEEE standard roundings. Through the use of a rectan division operations. 50 gular multiplier, no full precision multiplication steps A more recently developed system employs a divi are required. sion system using a Newton-Raphson approximation An important technical advantage of the present technique. In this system, an approximation of the recip invention inheres in the fact that it uses a rectangular rocal of the divisor is calculated using an iterative pro aspect ratio multiplier circuit. The use of the rectangu cess to achieve a value for the reciprocal in a full preci 55 sion format. The full precision reciprocal approxima lar multiplier saves time in several places in the division tion is then multiplied by the full precision dividend to process. Each of the multiplication steps used to form achieve an estimate of the full precision quotient. Only the quotient digit values are much simpler functions a bound on the indeterminate error of the estimated than full precision multiplication. Further time savings quotient is known and this information is inadequate for 60 result from the fact that the initial estimation of the implementation of precise rounding. To achieve precise reciprocal of the divisor need only be estimated to the rounding the indeterminacy in the error is removed by precision of the shorter side of the rectangular multi a second full precision multiplication. In the second full plier. This saves the multiplication steps necessary in precision multiplication step, the divisor is multiplied by the Newton-Raphson iterations to expand the accuracy the estimated quotient and a corresponding remainder is 65 of the estimation to a full precision width, as well as computed. This information is then sufficient to allow saving the subsequent full precision multiplications em for the appropriate IEEE standard rounding proce ployed to remove the indeterminacy in the Newton dures.