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Produced by the NASA Center for Aerospace Information (CASI) FIFTH QUARTERLY R-'ORT

BONDING LARGE AREA SILICON WAFERS

CONTRACT NO. 952022

PREPARED FOR

JET PROPULSION LABORATORY

4800 Oak Grove Drive Pasadena, California 91103

I ^> 1960? ^u iQ 71

PREPARED BY a r mW MOTOROLA INC.

W SEMICONDUCTOR PRODUCTS DIVISION a C. 5005 East McDowell Road v; Phoenix, Arizona 85008 C °

Z09 WMOA A11117V^ 0

FIFTH QUARTERLY REPORT

BONDING LARGE AREA SILICON WAFERS

CONTRACT NO. 952022

PREPARED FOR

JET PROPULSION LABORATORY 4800 Oak Grove Drive Pasadena, California 91103

PREPARED BY

MOTOROLA INC. SEMICONDUCTOR PRODUCTS DIVISION 5005 East McDowell Road Phoenix, Arizona 85008

"This work was performed for the Jet Propulsion Laboratory, California Institute of Technology, as sponsored by the National Aeronautics and Space Administration under Contract NAS7-100." This report contains information prepared by Motorola Inc., Semiconductor Products Division under JPL sub-contract. Its content is not necessarily endorsed by the Jet Propulsion Laboratory, California Institute of Technology, or the National Aeronautics and Space Administration.

ii 4

ABSTRACT

Progress in both solid-solid and solid-liquid diffusion bonding is described. The problem of voiding which beset the project in the last period is discussed and solutions, where they have been obtained, are presented. A void-free solid-solid bonding scheme for inter-wafer bonds has been achieved and the results are shown. Elimination of gas filled voids in the solid-liquid case can be achieved by eliminating the electrodeposition of low melting point materials. Bonds of 1-inch wafers to appropriate heat sinks are shown as prototypes to the large area bond of an actual circuit.

The progress in the measurement of thermophysical properties is reported. Expansion coefficients of several common solders are given as well as the elastic modulii for the Ag-In system.

The results of the computer stress analysis for a 1•-inch diameter trilayer system are presented. Curves for radial, hoop, "Z 1 ° and sheer stress as a function of radius and depth in the silicon wafer are shown and implication on device performance are discussed.

iii

^. A. -0

TABLE OF CONTENTS y Section Title Page 1.0 INTRODUCTION 1 V 2.0 TECHNICAL DISCUSSION 3 2.1 Diffusion Bonding 3 2.1.1 Solid State Diffusion Bonds 3 2.1.2 Liquid State Diffusion Bonds 8 2.2 Amalgam Bonding with Low Ten.perature Solders 19 2.3 Thermophysical Properties 21 2.3.1 Elastic Modulus 22 2.3.2 Tensile Strength 25 2.3.3 Coefficient of Thermal Expansion 25 2.3.4 Thermal Conductivity 31 2.4 Stress Analysis 31 3.0 NEW TECHNOLOGY 41 4.0 CONCLUSION 43

iv LIST OF ILLUSTRAT IONS Figure Title Page 1 Cross Section Through a Au-Ag-Au Solid-Solid Diffusion Bond 6 2 Cross Section Through a Au-Cu-Au Solid-Solid Diffusion Bond 7 3 Cross Section Through a Au-In-Au Solid-Liquid Diffusion Bond 10 4 Cross Section Through Au-In-Au Solid-Liquid Diffusion Bend Showing Alloying and Intermetallic Formation 11 5 1-inch Wafer to Molybdenum Heat Sink with Indium Diffusion Bond 13 6 1-inch Wafer to Molybdenum Heat Sink with Tin Diffusion Bond 14 7 1-inch Wafer to Molybdenum Heat Sink with Pb-Sn-In-Cd Diffusion Bond 15 8 1-inch Wafer to Molybdenum Heat Sink with Pb-Sn-In Diffusion Bond 16 9 Cross Section of Pb-Sn-In-Cd Diffusion Bond 17 10 Cross Section of Pb-Sn-In-Cd Diffusion Bond 18 11 Cross Section of Ga-In-Sn + Ag Amalgam Bond 20 12 Elastic Modulus for Ag-In Solid Solutions 23 13 Results of an Attempt to Swage 50-50 Ag-In Showing the Brittle Nature of the Material 24 14 Dilation Curve for Au-Ge 26 15 Dilation Curve for Au-Si 27 16 Dilation Curve for Au-Sn 28 17 Dilation Curve for Al-Si 29 18 Dilation Curve for Pb-Sn 30 19 Radial Stress vs Radius in Silicon 32 20 Hoop Stress vs Radius in Silicon 33 21 Z-stress vs Radius in Silicon 34

v LIST OF ILLUSTRATIONS (C ont ' d . ) Figure Title Page I 22 Shear Stress vs Radius in Silicon 35 23 Radial Stress vs "2" in Silicon 37 24 Radial Stress Surface for Silicon 38 25 Radial Stress as a Function of Solder Expansivity 40 26 Bridgeman Furnace Profile 42

I vi 9

1.0 INTRODUCTION

This report describes work performed during the fifth 3-month period of an 18-month program to develop techniques for reliably bonding large area wafers to suitable heat sinks. The purpose is to enable the bonding of silicon single crystals of greater than 20 mils and up to 2 inches in diameter in a manner which does not damage the wafer or affect the performance of devices contained therein. The provision of a path of low thermal resistance between the heat sources and the heat sink is an essential character. The materials of the system should not degrade under continuous operation or show deleterious effects when subjected to thermal shock or other high stress testing.

The approach to the problem has been in fax phases. The first is the appraisal of potential bonding materials and the actual development of large area bonding methods. The selection of a suitable metal for bonding has been completed, emphasis being concentrated on indium, tin and multicomponent systems based on 01,e'm. Development of methods for actually making bonds is nearing a final. stage.

The use of "diffusion bonding" has emerged as the principal solution to the problem. In one of several ways this method can achieve a high temperature solder with a moderately low temperature anneal. Two modes of diffusion bonds can be used: all solid state bonding (2.1.1) in which a diffusion couple is used as a bonding tool or solid-liquid bonding (2.1.2) where a "wet and flow" operation is basic. A similar method called "amalgam bonding" due to its similarity to the dental filling procedure is finding application (2.2).

Measurements of several thermophysical properties of bonding alloys are nearing completion. Values for expansion coefficient and elastic modulus for some bonding systems are given (2.3.).

1 The results of a computer stress analysis for a trilayer system of 1-inch diameter are presented (2.4). Stress curves for all the pertinent stresses and a stress "surface" for the wafer layer are discussed along with implications about the solder materials. The effect of varying the solder expansivity when a solder has an elastic limit of 20,000 psi is given.

If 2 2.0 TECHNICAL DISCUSSION

2.1 DIFFUSION BONDING

Due to the disparity in expansion coefficients between silicon and the common heat sinking materials, new bonding techniques requiring small thermal excursions must be employed. Con- sideration of performance levels, however, indicates that a high temperature refractory-like solder, resistant to hardening effects is also desirable. In this program, the develo pment of diffusion bonding and several "off-shoot" techniques has presented a feasible solution to this problem. This approach allows a relatively high temperature bond to be achieved using a low temperature anneal, avoiding any large thermal excursions and hence keeping stresses low.

2.1.1 Solid State Diffusion Bonds

The use of the binary diffusion couple as a bond^,ng tool has been applied to 1- and 2-inch wafers of silicon. Two metal "mating" surfaces--one the back of a wafer, the other the heat sink-- are placed in contact and held at temperatures well below the melting points (and/or any other phase change temperature). Interdiffusion of the species eliminates the original tnr;°erface and if sufficient time is a".lowed,a bond is achieved. By properly choosing the metals as those which form ideal solid-solutions (e.g., Au-Ag Au--Cu), one can eliminate the deleterious bonding characteristics of high thermal and electrical resistance attributable to intermetallic compounds. Although these bonds require relatively long anneal times and slightly higher temperatures than some other methods, the advantages gained in conductivity appear to make pursuance of this method more than worthwhile.

3 2.1.1.1 Voids in Solid State Diffusion Bonds Al

As was pointed out in the last report of this project, the x prune problem with this solid state bonding scheme was with voids. Two characteristics of the plated surface were thought to contribute to these voids:

(1) Surface roughness--Due to the "matte" finish of the electroplated goad, pockets may exist when two surfaces are enmeshed. For small area (die) bonds, deformation of the surfaces into one another is easily achieved with moderate forces and voids are eliminated. In the case of the large area bond, however, enormous forces would be required for total deformation and hence "holes" can be expected to remain.

(2) Concavity--Due to electric field configurat4ons during electroplating the edges of the wafer receive more deposited material than the center. This results in a concave surface. When placed in contact with a planar or similarly concave surface,"edge bonding" 4 results, the center region remaining completely open.

A more detailed disucssion of these points including illustrations has been given in the previous report.

The first attempt at a solution to this problem has been most successful. To simultaneously eliminate both the roughness and concavity,the wafer and heat sink were repolished after the gold electroplating process with a fine alumina "slurry." This leaves both surfaces flat and smooth providing the optimum atomic contact necessary for a good diffusion couple.

A thin layer of silver (or copper) is then evaporated on one of the polished gold surfaces (usually the heat sink) just before clamping the system together. if

4 I&

Actual bonding takes place at 300°C for about 16 hours in an N2 and H2 ambient. The system was mechanically clamped as discussed in earlier reports.

Results are shown in Figures 1 and 2 for the Au-Ag-Au and Au-Cu-Au systems, respectively. It is easily seen that the bonds are thin (,0.25 mil) , well alloyed and free of any voids. Since both these binary metallic systems are ideal solid solutions, it is expected that the thermal and electrical resistances are both quite low.

Although the solid state bonding system has yielded excellent bond quality, there exist two drawbacks in the method:

(1) The anneal time may be too long for high volume production.

(2) The extra polishing step is time consuming and expensive.

Experiments to minimize anneal time and yet achieve complete elimination of the interface must be done. This will establish some boundary condition on the process. The use of thinner metal layers will also help cut down this time.

One way to cut out the polish after electroplating is to eliminate the electroplating step altogether. This may be achieved by using one of the recently developed multilayer metallizations put down by evaporation on prepolished substrates and heat sinks. The first layer of the multilayer structure is necessary to provide adherence to the silicon and the second layer is the outer sandwich of the bond. One such system which appears feasible is the Cr-Au metallization now finding wide application in integrated circuits. It seems possible to use a three-stage evaporation Cr followed by Au then Ag on the wafer and a polished gold layer on the heat sink.

5 1000X

Figure 1. Cross Section Through a Au-Ag-Au Solid-Solid Diffusion Bond

6 7618-10-8 1000X

Figure 2. Cross Section Through s Au-Cu-Au Solid-Solid Diffusion Bond

7619-10-8 7 Preliminary wafer-wafer bonds using this system show promise and work on this system using heat sinks is continuing. a 2.1.2 Liquid State Diffusion Bonds

The use of the trilayer electrodeposited systems Au-In-Au. Au-Sn-Au in making large area bonds has been the cause of much concern. Although the solid state bonds are of excellent quality, there is, from a production viewpoint, a need for a more rapid, less expensive system of making large area bonds. Hence, in spite of several major problems work has continued on the liquid state diffusion bond and some degree of success has been achieved.

2.1.2.1 Voids in Liquid State Diffusion Bonds

Prime among the problem areas has been that of voids. We have discussed in detail the probable causes of holes in bonds and will simply outline them here for clarity: r

(1) Trapped gas--surface roughness of the electroplated layers can cause trapping much the same as in solid state bonds.

(2) Outgassing--electroplated layers contain quantities of "junk" (brighteners and other organics) which are trapped in the liquid layer during the bonding process.

(3) Pillaring--this effect due to nonuniform cooling and expansion disparity creates large voided regions in the bond.

(4) Chemical reaction--reduction of metal oxides leaves a gaseous residue within the "wet" layer.

8 ,4

(5) Dewetting--incompatibility of surfaces causes lack of adherence.

(6) Diffusion effects--Kirkendahl and other related effects can also account for voids.

As a first attempt at finalizing a process without the deleterious void problem, the use of the electroplated "wet" layer was eliminated. This removed any trapped organics and gases from the center layer. As a replacement "thin" preforms of pure indium and pure tin were used. These were rolled flat, varied in thickness from 2 to 4 mils, and were sandwiched between the wafer and heat sink. The use of 99.999 + percent pure metals also guaranteed freedom from impurity oxides along with eliminating the troublesome organics. Anneal temperatures were 250° for both the Sn and In systems for less than 1 hour.

Figures 3 and 4 show a cross section through a 1.5-inch wafer-wafer bond using Au-In-Au. The entire bond segment is shown to be void free and the formation of high melting point intermetallics is evident. It is clear, however, that alloying is incomplete; the center of the bond is probably pure indium, and the need for still thinner preforms (the origin-ril preform here was about 4 mil) is evident. Measurements show that complete alloying occurs to just over 1 mil at the time-temperature used and this seems to be the upper limit on the preform thickness. Efforts are bing made to obtain rolled indium and tin foils of just less than 1 mil for future use.

In spite of this, however, the absence of the previously seen gas —pocket voids is gratifying. The use of the "junk-free" preforms has apparently provided a solution to problems 1 and 2.

Pillaring (problem 3) has been eliminated by allowing complete hardening of the bond layer before unclamping. It was

9 250X

Figure 3. Cross Section Through a Au-In-Au Solid-Liquid Diffusion Bond

7620-10-8 10 1000X

Figure 4. Cross Section Through Au-In-Au Solid-Liquid Diffusion Bond Showing Alloying and Intermetallic Formation

11 7621-10-8 decided that when a bond is unclamped while the solder in the center is still soft, buckling of the wafer may occur due to unequal expansion between heat sink and wafer. It is this buckling which causes pillaring. At any rate, allowing a bond to completely cool has eliminated this problem.

2.1.2.2 Multicomponent Solders in Diffusion Bonding

It is a well-known fact that the addition of impurities to a normally pure liquid metal decreases the surface free energy of the melt making the wet and flow process proceed in an easier fashion. In addition, diffusion in an alloy may proceed faster than in either of the parent materials (although this is not always true). With this idea in mind, we have developed alloy solder preforms for the "wet" layer which manifest superior "wet and flow" characteristics. In most applications where preforms are used, flow of the solder is not desirable although good wetting of the surface to be bonded is essential. At present, bonds employing electroplated Au, and either the ternary system Pb-In-Sn or the quaternary system Pb-In-Sn-Cd are being made. If one refers to Figures 5, 6, 7, and 8,it is easily seen that the wettability of the gold layer by the ternary system is far better than of the others. These figures are of bonds made with identical preforms of several different solder materials. Upon sectioning one of these multicomponent bonds, one finds excellent alloying characteristics as well (Figures 9 and 10).

It is noteworthy that Figures 5, 6, 7, and 8 show "prototypes" of future LSI systems. A molybdenum heat sink 1.25 inches in diameter which has previously been brazed to a copper stud, will act as the "pad" upon which the 1-inch "die" will be bonded. These partic- ular circuits are Motorola process control patterns, and the bonds were made to test wetting, alloying, and mechanical stability under thermal cycling of the bonds. a

12 P

Figure 5. 1-inch Wafer to Molybdenum Heat Sink with Indium Diffusion Bond

7621-10-8 13 Figure 6. 1-inch Wafer to Molybdenum Heat Sink with Tin Diffusion Bond

14 7622-10-8 Figure 7. 1-inch Wafer to Molybdenum Heat Sink with Pb-Sn-In-Cd Diffusion Bond

15 7623-10-8

-14W. CT Figure 8. 1-inch Wafer co Molybdenum Heat Sink with Pb-Sn-In Diffusion Bond

7624-10 -8 16 6v

250X

Figure 9. Cross Section of Pb-Sn-In-Cd Diffusion Bond

17 7625-10-8 1000X

Figure 10. Cross Section of Pb-Sn-In-Cd Diffusion Bond

18 7626-10-8 In summary then, the future of liquid state diffusion bonding again looks bright. Although these bonds may not manifest the superior electrical and thermal characteristics of an all solid-state bond, they :nay find application where speed and cost are a problem.

2.2 AMALGAM BONDING 4ITH LOW TEMPERATURE SOLDERS

In diffusion bonding alloying takes place along an interface between a liquid and solid layer unt:.l, at the anneal temperature, the entire bond volume is solid. An alternate method by which one can obtain a high temperature material is to disperse particles of high melting point materials in a background of liquid metal just before bonding. (This is the principle used to make a dental filling.) By annealing at moderate temperatures, then, the solid is dissolved in the liquid until, as in diffusion bonding, the solidus line of the solution is crossed and the amalgam becomes solid.

Several wafer-wafer bonds have been made using an alloy of Ga ., In, Sn, which is liquid at room temperature, as the solder and silver powder as the dispersant. One such bond is shown in Figure 11. The bond is void f ree, but in this case insufficient alloying has left some silver undissolved.

It is apparent that this method shows promise although much is to be 'learned about the technique of making such bonds. The large surface to volume ratio of the dispersed powder appears to decrease the anneal time from what it would be if the system was layered. However, it must be remembered that since these solders are liquid at room temperature or slightly above, more high temperature material and longer anneal times are required for alloying to an solder operat- ing at the temperatures dictated by electronic systems.

Current work schedules call for some investigation into the techniques of the amalgam bond in the near future. 19 Figure 11. Cross Section of Ga-In-Sn + Ag Amalgam Bond

20 7627-10-8 2.3 THERMOPHYSICAL PROPERTIESr

The determination of various thermal and mechanical. properties of typical solder systems were undertaken to provide insight into the characteristics of solder materials with the idea of furthering design and fabrication in the future. Five common solders of the microelectronics industry, as well as a binary metallic system typical of diffusion bonding, were to be examined. The solders are:

Au-Sn (80-20) Au-Ge (88-12) Au-Si (97-3) Al-Si (89-11) Pb-Sn (37-63)

The binary system chosen was Ag-In; the reasons for the coice being twofold:

(1) It was presumed that the properties of Ag-In were typical of solders formed from the I-III and II-IV groups of the periodic table.

(2) Materials for fabrication are readily available, easy to work with and have well-known properties in the pure stare.

The measurements undertaken were coefficient of thermal expansion, thermal conductivity, elastic modulus, and tensile strength.

It was felt that from these four, other pertinent quantities such as electrical conductivity, hardness, and others, could be in- ferred from well known physical laws (e.g., Wiederman-Franz Law).

21 2.3.1 Elastic Modulus

Measurements of the elastic modulus of several common b eutectic solders have been attempted (both here and by other workers); however, good data is not forthcoming. The solders are extremely brittle and cannot even be machined without excessive chipping and cracking. Metal working of the thermal conductivity samples into tensile specimens is an impossibility. Hence, no further work is planned in the tensile properties of these eutectic solders.

The elastic modulus measurements for the Ag-In system have proceeded as planned (at least in the solid solution ranges of less than 20 percent solute).

Samples were "swaged" from cast 0.5-inch diamter slugs into 1/8-inch diameter rods, suitable for pulling in an Instron tester. Before each test,specimens were annealed at well over 75 percent of their melting point to assure removal of any residual stress from the metal working.

Data for Young's Modulus as a function of composition is shown in Figure 12. As would be expected from the pure metal parameters increasing indium content tends to "soften" (i.e., lower the elastic modulus) the harder metal whereas on the opposite side of the diagram the reverse is true. The implications of this are that the addition of indium to any "hard" solder ought to provide a more malleable bonding material which will absorb the stresses of thermal mismatch. These data seem to confirm the choice of indium-based systems for diffusion bonding.

It is noteworthy that data does not exist for the fi intermetallic regions. This is due in a large part to cur inability to have compounds with near 50-50 composition machined. Figure 13

22 .

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cm Q 0 0, O Q !D v v N 0 Q ( 9 01 x ISd)3 23 Figure 13. Results of an Attempt to Swage 50-50 Ag-In Showing the Brittle Nature of the Material

24 7628-10-8 shows the results of an attempt to swage 50-50 Ag-In. At the first pass, the end of the sample is shattered into bits making further machining impossible. This is the typicala behavior of intermetallic compoundsc and ....rMICCn^ ; "^ out further why ^^^^ materials are to be avoided. (This, again ;, indicates the superiority of the Au-Ag solid state bond where no such compounds are formed.) Annealing schedules and "shim" thicknesses, which avoid excessive intermetallic compound formation, must be developed for a high reliability, stable large area bond.

2.3.2 Tensile Strength

The swaged samples used to measure the elastic moduli are being annealed in preparation for a "pull-to-break" test which will yield the maximum tensile strength of the solder. Data should be obtained in the next few weeks.

2.3.3 Coefficient of Thermal Expansion

Measurements have been completed of the expansivity of the five eutectic solders using a quartz dilatometer as previously described. Figures 14, 15, 16, 17, and 18 are the expansion curves for each of the samples. The slope of the Al vs T line is the expansioa coefficient a. The values for each sample are given on each curve and summarized in Table I.

TA BLE I

Solder a(ppm/,C)

Au-Ge 14.1

Au-Si 14.2

Au-Sn 17.1

Al-Si 23.1

Pb-Sn 22.1

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( £ _01 x S3HONO HION31 30 It is to be noticed that these values are high compared to either silicon or molybdenum and as such do not appear ideally suited to large scale bonding where matching expansion is important especially in the case where the solder is very brittle. One also sees that the Au-Si and Au-Ge solders manifest the same expansion as pure gold. This is expected since the Au in either case forms a continuous phase (i.e,, silicon particles in a gold background) and as such dominates the properties of the alloy material. The same is true for Al-Si.

Sample preparation has further delayed measurements of expansivity 'in the case of the Ag-In system.

2.3.4 Thermal Conductivity

This parameter has been reported for the eutectic solders. The presence of voids in the cast Ag-In slugs has demanded the con- struction of appropriate machinery fortheir removal (cf New Technology). A furnace for this purpose has been constructed and calibrated. Samples and final measurements should be forthcoming.

2.4 STRESS ANALYSIS

The first complete solution for "stresses-in-joined-bodies" using the superposition method and the computer program has been done. Calculations were performed for a 1-inch sil 4&:.con wafer bonded .with gold solder to a molybdenum heat sink. The respective thicknesses were 20, 2 and 125 mils while the expansion coefficients are 3.3, 14.3 and 5.5 in units of ppm/°C. Figures 19, 20, 21, and 22 show the radial dependences of the pertinent stresses in the silicon wafer. Here, the left ordinate gives the reduced stress (a/E) while the right ordinate shows the actual stress in psi. A positive a represents a tension force whereas a negative one means the body is under compression.

31 10

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7630-10-8 0 0 0.1 0.2 0.3 0.4 0.5 0.6 r (INCHES) 32 10

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7631-10-5

0 0 0.1 0.2 0.3 0.4 0.5 0.6 r (INCHES) 33 !760

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7632-10-8

—9 0 0.1 0.2 0.3 0.4 0.5 0.6 r(INCHES) 34 s

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7634-10-8

0 0.1 0.2 0.3 0.4 0.5 v.6 r ( INCHES) 35 These results clearly show that a bonded silicon wafer a is under considerable compressive force in the radial and "hoop" directions (x,20,000 psi) and the buckling experienced in the earlier stages of this program seems to be explained. Figure 21 shows a "Z" stress peak near the extreme of the wafer and one might anticipate a peeling effect to ensue as wafer size increases.

The results shown in Figure 22 demonstrate that the shear forces are considerably less than the tensile ones. This is perhaps due to the fact that the surface shea r .interaction actually present in the physical system is replaced in the computer calculation by an ""effective tensile force" and some of the true shear shows up in the rather large tensile forces.

The "Z"" dependence of the radial stress is shown in Figure 23 parcmeterized by the radius and demonstrates the expected decrease in the forces as one moves away from the bonding interface and toward the wafer ige. It is noteworthy, however, that the top surface of the wa.for is not stress-free as one might hope. Part of this may be due to the method of calculation of these boundary forces; however, it is felt that the presence of some nonzero stress on the surface is real and that stress sensitive devices in this region would be affected.

The preceding figures may be condensed into a "radial- stress surface" sketched in Figure 24. Any point in the surface represents the magnitude of the stress at a given (r,z) coordinate in the silicon wafer. Similar data has been obtained for the solder layer and the substrate and plots will be `,i cluded in futlare reports on this project.

An interesting calculation has been performed to study the effects of us-Ing different solder materials. Sample calculations

36 0

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Figure 24. Radial Stress Surface for Silicon a

38 7640-10-8 have been done to determine the radial stress as a function of the expansivity of the solder. These data are summarized in Figure 25.

One should note that the stress levels in bath the water and substrate are only weakly dependent on the solder expansivity. This is probably due in part to the fact that the calculations main- tained the same elastic modulus for the solder (namely pure Au) while varying the expansion coefficient and also partly due to the thinness of the solder. The very thin layer would be transparent to a good part of the applied stress of the heat sink. The flat region of the solder curve is due to the test that a plastic approximation was employed and stresses beyond 20,000 psi exceed the elastic limit of the solder and are therefore intolerable.

It is felt that extension of the present work to include 2-inch wafers to heat sinks and an examination of the effects of varying solder parameters for that system are within the scope of this work and will be dealt with during the next report period. Similar results are anticipated.

39 2(

A N a x M O

X a

—2

7641-10-8

5 10 15 40 a SOLDER ( PPM/9C) ^.0 NEW TECHNOLOGY

Due to the fact that the cast thermal conductivity samples were full of voids, a method of eliminating them was developed. In the "art y' of crystal growing, one common method of removing both voids and impurities is "gradient cooling." This is a modification of zone refining in which the entire sample is made molten and as Qool.ng proceeds from one end a liquid-solder interface progresses across the sample leveling the solute content and sweeping gas pockets and voids to one end of the sample. The apparatus commonly used for the process is a Bridgeman Furnace. This is simply a wire- wound furnace with a step gradient in it. The profile for the furnace which we have constructed is shown in Figure 26. The solidus temperature is to be located at the region of steepest slope (+). One simply lowers a given material -.n molten form from the hot zone until solidi- fication occurs at one end; the liquid-solid interface proceeds across the sample leveling impurities and sweeping out voids.

The temperature controller, which we have also designed and constructed to operate the furnace, is a modified S.C.R. control unit. 00

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`'f L 4.0 CONCLUSION

It was remarked in the conclusion of the last report that the future of diffusion bonding--both for solid and liquid states-- rested in the ability to identify and eliminate voids. In the case of solid state bonding voids have been completely eliminated and excellent wafer-wafer bonds have been made. The process is now being applied to water-heat sink bonds and a feasible system for excellent conductance is expected to result. It is felt that the quality of the solid state bonding scheme in terms of both electrical and thermal conductivity more than outweighs the cost and time in- volved in making the bonds.

Most voids have also been eliminated in the liquid state bonds by making use of thin solder "shims" instead of the usual electroplated layers. Present techniques leave some unalloyed solder but the use of thinner shims is expected to eliminate the incomplete alloying.

10 The continuity of the large area bonds and their mechanical strength under thermal cycling is to be evaluated during the next report period. Military specifications will be employed for testing and liquid crystal systems are being developed to in- vestigate the void problem nondestructively. These tests will be used on existing prototypes of large area bonds and on the new bonds to be made in this period.

Finalization of the properties measurements and computer stress analysis is expected to be completed in this period heading toward final report.