DOCSLIB.ORG

Cell/BE Processor-Based Systems and Software Offerings IBM Bladecenter

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Cell/BE Processor-Based Systems and Software Offerings IBM Bladecenter IBM Systems and Technology Group Cell/B.E. processor-based systems and software offerings IBM BladeCenter® QS22 and SDK 3.0 IBM CONFIDENTIAL © 2008 IBM Corporation IBM Systems and Technology Group The challenge today For many years, organizations have relied on performance gains from increasing clock speeds of “traditional” microprocessor architectures This approach has been challenged by the physical limitations of semiconductors and by traditional processor architecture implementations High performance computing (HPC) applications need a fundamentally new technology and approach to the system-level architecture to achieve the desired level of performance. 2 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group Cell Broadband Engine™ (Cell/B.E.) Technology For a higher of absolute performance and efficiency IBM, Sony, Toshiba Alliance formed in 2000 March, 2001 – STI Design Center opened in Austin, TX April, 2004 - Single Cell BE operational July, 2004 - 2-way SMP operational February, 2005 - first technical disclosures at ISSCC May, 2005 - first public demonstration of Cell/B.E. processor-based system at E3 August, 2005 - published technical details of Cell/B.E. architecture November, 2005 - published open source SDK & Cell/B.E. simulator August, 2006 - introduced the very first Cell/B.E. processor-based server to the market 3 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group IBM commitment to innovation IBM BladeCenter QS22 Extraordinary double precision floating point performance. Large memory capability. Ready for the most demanding production applications PowerXCell™ 8i processor •BladeCenter QS21 •IBM SDK for Multicore Acceleration 3.0 BladeCenter QS20 Produce systems Produce robust Create initial for early adoption production ready platforms for and solution systems for targeted experimentation enablement industry applications 2007 2008 2006 4 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group Cell Broadband Engine Architecture™ (CBEA) Technology Roadmap CompatibleCompatible codecode andand securitysecurity basebase acrossacross entireentire linlinee IBM PowerXCell 32ii 45nm SOI Performance Enhancements/ IBM Scaling PowerXCell™ 8i (1+8eDP SPE) 65nm SOI Cost Cell/B.E. Cell/B.E. Cell/B.E. (1+8) (1+8) Reduction (1+8) 90nm SOI 65nm SOI 45nm SOI Committed Concept 2006 2007 2008 2009 2010 All future dates and specifications are estimations only; Subject to change without notice. Dashed outlines indicate concept designs. 5 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group IBM PowerXCell™ 8i processor benefits The new PowerXCell 8i processor builds on the Cell Broadband Engine Architecture and combines a general-purpose Power Architecture™ core of modest performance with eight enhanced synergistic processing elements optimized for extreme double precision and single precision computational performance Sets a new performance standard – Accelerates computationally intense workloads such as analytics, multimedia and vector processing. – Efficient computation per watt Designed for flexibility – Wide variety of application domains – Cell can cover a wide range of application space with its capabilities in – floating point operations, integer operations PowerXCellPowerXCell 8i 8i processorprocessor – data streaming / throughput support 6565 nmnm 99 cores,cores, 1010 threadsthreads – real-time support 230.4230.4 GFlopsGFlops peak peak (SP)(SP) atat 3.2GHz3.2GHz – Exploits C/C++, Fortran programming models 108.8108.8 GFlopsGFlops peak peak (DP)(DP) atat 3.2GHz3.2GHz UpUp toto 2525 GB/sGB/s memorymemory bandwidthbandwidth Enhanced security capability UpUp toto 7575 GB/sGB/s I/OI/O bandwidthbandwidth – Virtual trusted computing environment for security 9292 WattsWatts @@ 3.2GHz3.2GHz TopTop frequencyfrequency >4GHz>4GHz (observed(observed inin lab)lab) 6 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group PowerXCell 8i uses ½ the space & power and delivers more than 2.3x the GFlops of traditional architecture Example Server Example Desktop PowerXCell 8i Dual Core Quad Core 2 Nine Core 349mm , 3.4 GHz @ 150W 214 mm², 3 GHz @ 130W 109 mm 2 3.2 GHz@ 75W 2 Cores, ~27.2 SP GFlops 4 Cores, ~96 SP GFlops 1.3b Transistors @ 65nm 820m Transistors @ 45nm 9 cores, ~ 230 SP GFlops, 250m Transistors @ 65nm On any traditional processor, shown ratio of Intel’s x86 Quad Core processors are Dual cores to cache, prediction, & related items illustrated here remains at ~50% of area the Chip Modules (DCMs), 2 of these processor chip area stacked vertically & packaged together 7 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group BladeCenter® QS22 – PowerXCell 8i Core Electronics D D D D D D D D – Two 3.2GHz PowerXCell 8i Processors D D D D D D D D R R R R R R R R – SP: 460 GFlops peak per blade 2 2 2 2 2 2 2 2 – DP: 217 GFlops peak per blade DDR2 – Up to 32GB DDR2 800MHz – Standard blade form factor PowerXCell 8i PowerXCell 8i – Support BladeCenter H chassis Rambus® FlexIO ™ Flash, RTC Integrated features D D & NVRAM – Dual 1Gb Ethernet (BCM5704) D IBM D IBM R South R South 2 UART, SPI – Serial/Console port, 4x USB on PCI 2 Bridge 2 Bridge Con Legacy SPI PCI-X PCI Optional PCI-E x16 PCI-E x8 – Pair 1GB DDR2 VLP DIMMs as I/O buffer 4x HSC *1 2x USB HSDC 1GbE (2GB total) (46C0501) 2.0 2x PCI-E x16 Optional IB – 4x SDR InfiniBand adapter (32R1760) 2 port – SAS expansion card (39Y9190) Flash IB x4 HCA Drive – 8GB Flash Drive (43W3934) USB to IB-4x to GbE to BC mid plane BC-H high speed BC mid plane fabric/mid plane *The HSC interface is not enabled on the standard products. This interface can be enabled on “custom” system implementations for clients by working with the Cell services organization in IBM Industry Systems. 8 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group Performance highlights Performance is an order of magnitude better than general purpose processors (GPP) for media and certain applications that can take advantage of its Single Instruction Multiple Data (SIMD) capability – Performance of its simple Power Processor Element (PPE) is comparable to a traditional GPP performance – Each Synergetic Processor Element (SPE) is able to perform mostly the same as a GPP running at the same frequency – Key performance advantage comes from its eight de-coupled SPE engines with dedicated resources including large register files and DMA channels Accelerates targeted applications with extraordinary processing capabilities – Floating-point operations – Integer operations – Data streaming / throughput support – Real-time support Open architecture allows for optimization at compiler and application level – Performance gains from tuning compilers and applications can be significant – Tools/simulators are provided to assist in performance optimization efforts 9 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group IBM BladeCenter QS22 Premier blade for HPC workloads QS22 is the RIGHT choice for intensive streaming and/or single and double precision floating point workloads QS22 is OPEN – based on Power Architecture and running Linux® OS QS22 is EASY to deploy and to integrate into the existing IT infrastructure and/or workloads: – Co-exist and complement all other Blade servers offerings (Intel®, AMD®, POWER®) – Ready to scale out and deploy in production environments QS22 is GREEN – more than 1.7 SP (or 0.8 DP) GFLOPS per watt. 10 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group IBM SDK for Multicore Acceleration and related tools The IBM SDK is a complete tools package that simplifies programming for the Cell Broadband Engine Architecture Eclipse-based IDE Simulator IBM XL C/C++ compiler* Optimized compiler for use in creating Cell/B.E. optimized applications. Offers: * improved performance * automatic overlay support * SPE code generation XLC compiler is Performance a Tools complementary GNU tool chain product to SDK Libraries and frameworks Data Accelerated Communication Basic Linear Standardized Library and Algebra SIMD math Framework (ALF) Synchronization Subroutines (BLAS) libraries (DaCS) Denotes software components included in the SDK for Multicore Acceleration 11 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group IBM SDK for Multicore Acceleration value Designed to be highly reliable, simple to acquire and easy to use – Complete, integrated kit – Production-ready tools from IBM – IBM warranty and support Based on industry standards to ease the transition to the Cell/B.E. – Eclipse-based Integrated Development Environment – Standard, base libraries – Third-party libraries can be plugged in Designed to make it easy to port and optimize applications for the QS21 and QS22 – Enhancements to enable new features in QS22 – Performance tuning tools to help optimize algorithms without re-writing the entire application – Tools designed to help you partition an application across a hybrid Cell/B.E. and x86 platform 12 Sales Conference © 2008 IBM Corporation IBM Systems and Technology Group Decreasing programmer attention to architectural details Cell ProgrammingInc rApproacheseasing Progra aremm efullyr Co ncustomizable!trol over Cell/B.E. resources 2. Assisted 3. Case Tools / 1. “Native” Programming Complete Programming Hardware Libraries, Abstraction Compilers, Frameworks User tool-driven Intrinsics, © 2008 IBM Corporation DMA, etc. Sales Conference 13 IBM Systems and Technology Group Workloads ideal for PowerXCell
Load more

Recommended publications
  • Cell Processorprocessor Andand Cellcell Processorprocessor Basedbased Devicesdevices
    CellCell ProcessorProcessor andand CellCell ProcessorProcessor BasedBased DevicesDevices May 31, 2005 SPXXL Barry Bolding, WW Deep Computing Thanks to Ashwini Nanda IBM TJ Watson Research Center New York Pathway to the Digital Media Revolution Incremental Technology Innovations Provide Stepping Stones of Progress to the Future Virtual Communities Immersive WEB Portals Virtual Travel & eCommerce 20xx "Matrix" HD Content Virtual Tokyo Creation & Delivery Real-time Creation and Modification of Content Immersive Environment Needs enormous Real-Time Engineering computing Design Collaboration power 2004 Incremental Technology Innovations on the Horizon: On-Demand Computing & Communication Infrastructures Online Games Application Optimized Processor and System Architectures Leading Edge Communication Bandwidth/Storage Capacities Immersion HW and SW Technologies Rich Media Applications, Middleware and OS CellCell ProcessorProcessor OverviewOverview CellCell HistoryHistory • IBM, SCEI/Sony, Toshiba Alliance formed in 2000 • Design Center opened in March 2001 • Based in Austin, Texas • February 7, 2005: First technical disclosures CellCell HighlightsHighlights • Multi-core microprocessor (9 cores) • The possibilities… – Supercomputer on a chip – Digital home to distributed computing and supercomputing – >10x performance potential for many kernels/algorithms • Current prototypes running <3 GHz clock frequency • Demonstrated Beehive at Electronic Entertainment Expo Meeting – TRE (Terrain Rendering Engine application) IntroducingIntroducing CellCell
    [Show full text]
  • The GPU Computing Revolution
    The GPU Computing Revolution From Multi-Core CPUs to Many-Core Graphics Processors A Knowledge Transfer Report from the London Mathematical Society and Knowledge Transfer Network for Industrial Mathematics By Simon McIntosh-Smith Copyright © 2011 by Simon McIntosh-Smith Front cover image credits: Top left: Umberto Shtanzman / Shutterstock.com Top right: godrick / Shutterstock.com Bottom left: Double Negative Visual Effects Bottom right: University of Bristol Background: Serg64 / Shutterstock.com THE GPU COMPUTING REVOLUTION From Multi-Core CPUs To Many-Core Graphics Processors By Simon McIntosh-Smith Contents Page Executive Summary 3 From Multi-Core to Many-Core: Background and Development 4 Success Stories 7 GPUs in Depth 11 Current Challenges 18 Next Steps 19 Appendix 1: Active Researchers and Practitioner Groups 21 Appendix 2: Software Applications Available on GPUs 23 References 24 September 2011 A Knowledge Transfer Report from the London Mathematical Society and the Knowledge Transfer Network for Industrial Mathematics Edited by Robert Leese and Tom Melham London Mathematical Society, De Morgan House, 57–58 Russell Square, London WC1B 4HS KTN for Industrial Mathematics, Surrey Technology Centre, Surrey Research Park, Guildford GU2 7YG 2 THE GPU COMPUTING REVOLUTION From Multi-Core CPUs To Many-Core Graphics Processors AUTHOR Simon McIntosh-Smith is head of the Microelectronics Research Group at the Univer- sity of Bristol and chair of the Many-Core and Reconfigurable Supercomputing Conference (MRSC), Europe’s largest conference dedicated to the use of massively parallel computer architectures. Prior to joining the university he spent fifteen years in industry where he designed massively parallel hardware and software at companies such as Inmos, STMicro- electronics and Pixelfusion, before co-founding ClearSpeed as Vice-President of Architec- ture and Applications.
    [Show full text]
  • OLCF AR 2016-17 FINAL 9-7-17.Pdf
    Oak Ridge Leadership Computing Facility Annual Report 2016–2017 1 Outreach manager – Katie Bethea Writers – Eric Gedenk, Jonathan Hines, Katie Jones, and Rachel Harken Designer – Jason Smith Editor – Wendy Hames Photography – Jason Richards and Carlos Jones Stock images – iStockphoto™ Oak Ridge Leadership Computing Facility Oak Ridge National Laboratory P.O. Box 2008, Oak Ridge, TN 37831-6161 Phone: 865-241-6536 Email: [email protected] Website: https://www.olcf.ornl.gov Facebook: https://www.facebook.com/oakridgeleadershipcomputingfacility Twitter: @OLCFGOV The research detailed in this publication made use of the Oak Ridge Leadership Computing Facility, a US Department of Energy Office of Science User Facility located at DOE’s Oak Ridge National Laboratory. The Office of Science is the single largest supporter of basic research in the physical sciences in the United States and is working to address some of the most pressing challenges of our time. For more information, please visit science.energy.gov. 2 Contents LETTER In a Record 25th Year, We Celebrate the Past and Look to the Future 4 SCIENCE Streamlining Accelerated Computing for Industry 6 A Seismic Mapping Milestone 8 The Shape of Melting in Two Dimensions 10 A Supercomputing First for Predicting Magnetism in Real Nanoparticles 12 Researchers Flip Script for Lithium-Ion Electrolytes to Simulate Better Batteries 14 A Real CAM-Do Attitude 16 FEATURES Big Data Emphasis and New Partnerships Highlight the Path to Summit 18 OLCF Celebrates 25 Years of HPC Leadership 24 PEOPLE & PROGRAMS Groups within the OLCF 28 OLCF User Group and Executive Board 30 INCITE, ALCC, DD 31 SYSTEMS & SUPPORT Resource Overview 32 User Experience 34 Education, Outreach, and Training 35 ‘TitanWeek’ Recognizes Contributions of Nation’s Premier Supercomputer 36 Selected Publications 38 Acronyms 41 3 In a Record 25th Year, We Celebrate the Past and Look to the Future installed at the turn of the new millennium—to the founding of the Center for Computational Sciences at the US Department of Energy’s Oak Ridge National Laboratory.
    [Show full text]
  • Financial Computing on Gpus Lecture 1: Cpus and Gpus Mike Giles
    ' $ Financial Computing on GPUs Lecture 1: CPUs and GPUs Mike Giles [email protected] Oxford-Man Institute for Quantitative Finance Oxford University Mathematical Institute &Lecture 1 1 % ' $ Economics Money drives computing, as much as technology. If there’s a big enough market, someone will develop the product. Need economies of scale to make chips cheaply, so very few companies and competing products. To anticipate computing trends, look at market drivers, key applications. &Lecture 1 2 % ' $ CPUs • chip size/speed continues to doubles every 18-24 months (Moore’s Law) • similar growth in other hardware aspects, but memory bandwidth struggles to keep up • safe to assume that this will continue for at least the next 10 years, driven by: – multimedia applications (e.g. streaming video, HD) – image processing – “intelligent” software &Lecture 1 3 % ' $ Multilevel Parallelism • instruction parallelism (e.g. addition) • pipeline parallelism, overlapping different instructions • multiple pipelines, each with own capabilities • multiple cores (CPUs) within a single chip • multiple chips within a single shared-memory computer • multiple computers within a distributed-memory system • multiple systems within an organisation &Lecture 1 4 % ' $ Ideal Von Neumann Processor • each cycle, CPU takes data from registers, does an operation, and puts the result back • load/store operations (memory ←→ registers) also take one cycle • CPU can do different operations each cycle • output of one operation can be input to next - - - op1 - time - - op2
    [Show full text]
  • E-Business on Demand- Messaging Guidebook
    IBM Systems & Technology Group IBM Deep Computing Rebecca Austen Director, Deep Computing Marketing © 2005 IBM Corporation 1 IBM Systems & Technology Group Deep Computing Innovation Addressing Challenges Beyond Computation System Design Data – Scalability – Data management – Packaging & density – Archival & compliance – Network infrastructure – Performance & reliability – Power consumption & cooling – Simulation & modeling – Data warehousing & mining Software – Capacity management & virtualization – System management – Security – Software integration Economics – Programming models & – Hybrid financial & delivery productivity models – Software licensing 2 © 2005 IBM Corporation IBM Systems & Technology Group Deep Computing Collaboration Innovation Through Client and Industry Partnerships System, Application & User Requirements, Best Practices – SPXXL, ScicomP – BG Consortium Infrastructure – DEISA, TeraGrid, MareNostrum Software & Open Standards – GPFS evolution – Linux, Grid Research & Development – Technology/systems – Blue Gene, Cell – Collaborative projects – Genographic, WCG 3 © 2005 IBM Corporation IBM Systems & Technology Group Deep Computing Embraces a Broad Spectrum of Markets Life Sciences Research, drug discovery, diagnostics, information-based medicine Digital Media Business Digital content creation, Intelligence management and Data warehousing and distribution data mining Petroleum Oil and gas exploration and production Financial Services Optimizing IT infrastructure, risk management and Industrial/Product compliance,
    [Show full text]
  • モバイル性能を向上させたAVノートPC Qosmiotm V65
    一般論文 FEATURE ARTICLES モバイル性能を向上させたAVノートPC QosmioTM V65 QosmioTM V65/F60 High-Mobility AV Notebook PC 界 陽夫 板倉 広明 佐藤 重信 ■ SAKAI Akio ■ ITAKURA Hiroaki ■ SATO Shigenobu これまで東芝は，デジタル AV 機器と高性能ノートPC（パソコン）の機能を併せ持った AVノート PCとして， Qosmioシリーズ の開発を進めてきた。近年，モバイル性能を向上させた AVノートPC へのユーザーニーズが高まっており，今回，モバイル性能 を向上させたモバイルAVノートPC Qosmio V65（海外向けモデルはF60）を開発した。 第6世代となるQosmio V65/F60では，HD（High Definition）の映像データを高速処理できる映像処理専用エンジン SpursEngineTMとデジタルテレビ（TV）チューナを搭載しながら，当社のモバイルノートPCで培った高密度実装技術により 薄型化を実現した。更に，IMF（In Mold Forming）による新加飾技術で，深みのある色を表現しながら耐久性も向上させた。 一方， SpursEngineとブルーレイ（注1）ディスクドライブの組合せによる新たなアプリケーションを開発することで，AVノート PCとしての機能も向上させた。 Toshiba has developed the Qosmio series of audiovisual (AV) notebook PCs, which successfully balance the functionality of a notebook PC and that of digital AV equipment. In recent years, demand has been growing for AV notebook PCs that are sufficiently thin and light to be easily carried. To meet the demand for enhanced mobility, we have released the Qosmio V65/F60, the sixth-generation AV notebook PC, incorporating the SpursEngineTM high-performance stream processor, a Blu-ray Disc drive, and a digital terrestrial TV tuner for high-speed processing of high-definition (HD) contents, with a reduction in thickness achieved by the use of high-density mounting technology cultivated in the development of our mobile notebook PCs. Moreover, the Qosmio V65/F60 offers improved durability and increased depth of color by a new decoration technique using in-mold forming (IMF). 1 まえがき Qosmioシリーズは，デジタルAV機器の機能を備えるAV ノートPC として商品化を進めてきた。従来から，高性能
    [Show full text]
  • Legendsincomputing.Pdf
    Anita Jones z 2007 IEEE Founders Medal z Director of Defense Research and Engineering at the U.S. Department of Defense from 1993 to 1997 z Fellow of the z Association for Computing Machinery (ACM) z American Association for the Advancement of Science z IEEE z Author of two books and more than 40 papers z U.S. Air Force Meritorious Civilian Service Award z Distinguished Public Service Award z Congressional Record tribute z Augusta Ada Lovelace Award from the Association for Women in Computing z Lawrence R. Quarles Professor in the Computer Science Department at the University of Virginia’s School of Engineering and Applied Science Legends in Computing Amy Pearl Designer and implementer of the Sun Link Service, an open protocol for creating hypertext links between elements of desktop applications Legends in Computing Programming the Eniac z Programs were not stored z Every new problem required new connections Legends in Computing Stephanie Rosenthal z Computing Research Association Outstanding Female Undergraduate Award, 2007 z research at CMU on social robotics led to two publications. z research on collaborative learning, potential interfaces for use with interactive whiteboards and experiments about issues in collaboration, resulted in a first-authored publication. Legends in Computing 1950s Assembler Programming Class This would be so much easier with a computer… Legends in Computing Elaine Kant z Founder and president of SciComp z Fellow of the American Association for Artificial Intelligence z Fellow of the American Association for the Advancement of Science z Outstanding Achievement Award in Science/Technology, from University YWCA z U.S. Patent No.
    [Show full text]
  • Scheduling Tasks Over Multicore Machines Enhanced with Acelerators: a Runtime System's Perspective
    Scheduling Tasks over Multicore machines enhanced with acelerators: a Runtime System’s Perspective Cédric Augonnet To cite this version: Cédric Augonnet. Scheduling Tasks over Multicore machines enhanced with acelerators: a Runtime System’s Perspective. Distributed, Parallel, and Cluster Computing [cs.DC]. Université Bordeaux 1, 2011. English. tel-00777154 HAL Id: tel-00777154 https://tel.archives-ouvertes.fr/tel-00777154 Submitted on 17 Jan 2013 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. N◦ d’ordre: 4460 UNIVERSITE´ DE BORDEAUX 1 ECOLE´ DOCTORALE DE MATHEMATIQUES´ ET INFORMATIQUE THESE` present´ ee´ pour obtenir le grade de DOCTEUR Sp´ecialit´e: Informatique Scheduling Tasks over Multicore machines enhanced with Accelerators: a Runtime System’s Perspective par C´edricAUGONNET soutenue le 9 Decembre´ 2011 Apres` avis de : M. Albert COHEN Directeur de recherche INRIA Rapporteur M. Jean-Franc¸ois MEHAUT Professeur des Universites´ Rapporteur Devant la commission d’examen composee´ de : M. Henri BAL Professeur des Universites´ Examinateur M. Albert COHEN Directeur de recherche INRIA Rapporteur M. David GOUDIN Ingenieur´ Chercheur au CEA Examinateur M. Jean-Franc¸ois MEHAUT Professeur des Universites´ Rapporteur M. Raymond NAMYST Professeur des Universites´ Directeur de These` M.
    [Show full text]
  • IBM Power Systems Compiler Roadmap
    Software Group Compilation Technology IBM Power Systems Compiler Roadmap Roch Archambault IBM Toronto Laboratory [email protected] SCICOMP Barcelona | May 21, 2009 @ 2009 IBM Corporation Software Group Compilation Technology IBM Rational Disclaimer © Copyright IBM Corporation 2008. All rights reserved. The information contained in these materials is provided for informational purposes only, and is provided AS IS without warranty of any kind, express or implied. IBM shall not be responsible for any damages arising out of the use of, or otherwise related to, these materials. Nothing contained in these materials is intended to, nor shall have the effect of, creating any warranties or representations from IBM or its suppliers or licensors, or altering the terms and conditions of the applicable license agreement governing the use of IBM software. References in these materials to IBM products, programs, or services do not imply that they will be available in all countries in which IBM operates. Product release dates and/or capabilities referenced in these materials may change at any time at IBM’s sole discretion based on market opportunities or other factors, and are not intended to be a commitment to future product or feature availability in any way. IBM, the IBM logo, Rational, the Rational logo, Telelogic, the Telelogic logo, and other IBM products and services are trademarks of the International Business Machines Corporation, in the United States, other countries or both. Other company, product, or service names may be trademarks or service marks of others. 2 SCICOMP Barcelona | IBM Power Systems Compiler Roadmap © 2009 IBM Corporation Software Group Compilation Technology Agenda .
    [Show full text]
  • Toshiba Group's Environmental Vision 2050
    Toshiba Group’s Environmental Vision 2050 Meeting Environmental challenges – The first stage Ｅｎｖｉｒｏｎｍｅｎｔａｌ Ｖｉｓｉｏｎ ２０１０ Toshiba Group Slogan Committed to People, Committed to the Future. TOSHIBA Contribute to sustainable development of the Earth throughout our business processes and products Double overall eco-efficiency FY2000 FY2010 Product Business process eco-efficiency eco-efficiency Factor T - Products Factor T- Process 2.2 1.2 Value of a product/ Sales/Environmental impact of Environmental impact of a the entire business process product throughout its lifecycle 2 Copyright © Toshiba. 2007. All rights reserved. Meeting environmental challenges – The first stage Double Overall Eco-Efficiency FY2000 FY2010 Overall eco-efficiency 2.00 FY2006 2.00 FY2010 1.75 1.59 1.86 Result: 1.59 times 1.49 1.74 Target: 2 times 1.50 1.63 1.32 1.52 1.68 time (product) 2.2 times (product) 1.25 1.42 1.22 times (business process) 1.00 1.2 times (business process) 1.00 Compared with FY2000 Result Plan Compared with FY2000 0 2000 2004 2005 2006 2007 2008 2009 2010 (FY) ＰｒｏｄｕｃｔＰｒｏｄｕｃｔ ＥｃｏＥｃｏ--ｅｆｆｉｃｉｅｎｃｙｅｆｆｉｃｉｅｎｃｙ ＢｕｓｉｎｅｓｓＢｕｓｉｎｅｓｓ ＰｒｏｃｅｓｓＰｒｏｃｅｓｓ ＥｃｏＥｃｏ--ｅｆｆｉｃｉｅｎｃｙｅｆｆｉｃｉｅｎｃｙ Value of products (performance improvement) Ｓａｌｅｓ Environmental impacts throughout Environmental impacts of products Composition of environmental impacts business processes 2.2 times during product life cycles 1.2 times (Average of all products of Toshiba Group) FY2006 result 1.22 times FY2006 result 1.30 2.25 Environmental 1.68 times Environmental 2.20 impacts of 1.22 2.00 impacts of 1.20 2.03 products 1.68 business 1.20 1.17 1.75 1.88 (from procurement 1.56 1.19 1.19 1.20 1.20 1.20 1.74 of raw materials to processes 1.18 1.50 1.36 FY2010 target of raw materials to 1.60 final disposal) (manufacturing) 1.10 1.48 ２.２ times final disposal) 1.25 FY2010 target 1.0 1.00 Result Plan １.２ times 1.00 0 80% 20% 1.00 Result Plan 0 0 20002004200520062007 200820092010(FY) 20002004200520062007200820092010(FY) 3 Copyright © Toshiba.
    [Show full text]
  • IBM ACTC: Helping to Make Supercomputing Easier
    IBM ACTC: Helping to Make Supercomputing Easier Luiz DeRose Advanced Computing Technology Center IBM Research HPC Symposium University of Oklahoma [email protected] Thomas J. Watson Research Center PO Box 218 Sept 12, 2002 © 2002 Yorktown Heights, NY 10598 Outline Who we are ¾ Mission statement ¾ Functional overview and organization ¾ History What we do ¾ Industry solutions and activities Education and training STC community building Application consulting Performance tools research Sept 12, 2002 ACTC - © 2002 - Luiz DeRose [email protected] 2 1 ACTC Mission ¾ To close the gap between HPC users and IBM ¾ Conduct research on applications for IBM servers within the scientific and technical community Technical directions Emerging technologies ACTC - Research ¾ Software tools and libraries ¾ HPC applications ¾ Research collaborations ¾ Education and training Focus ¾ AIX and Linux platforms Sept 12, 2002 ACTC - © 2002 - Luiz DeRose [email protected] 3 ACTC Functional Overview Outside Technology: • Linux • Computational Grids ACTC • DPCL, OpenMP, MPI IBM Technology: • Power 4, RS/6000 SP • GPFS Solutions: • PSSP, LAPI • Tools • Libraries Customer Needs: • App Consulting • Reduce Cost of Ownership • Collaboration • Optimized Applications • Education + User Training • Education • User Groups Sept 12, 2002 ACTC - © 2002 - Luiz DeRose [email protected] 4 2 ACTC History Created in September, 1998 ¾ Emphasis on helping new customers to port and optimize on IBM system ¾ Required establishing relationships with scientists on research level Expanded operations via alignment with Web/Server Division: ¾ EMEA extended in April, 1999 ¾ AP extended (TRL) in September, 2000 ¾ Partnership with IBM Centers of Competency (Server Group) Sept 12, 2002 ACTC - © 2002 - Luiz DeRose [email protected] 5 ACTC Education 1st Power4 Workshop ¾ Jan.
    [Show full text]
  • Fast Elliptic-Curve Cryptography on the Cell Broadband Engine
    Fast elliptic-curve cryptography on the Cell Broadband Engine Neil Costigan1 and Peter Schwabe2 ⋆ 1 School of Computing Dublin City University, Glasnevin, Dublin 9, Ireland [email protected] 2 Department of Mathematics and Computer Science Technische Universiteit Eindhoven, P.O. Box 513, 5600 MB Eindhoven, Netherlands [email protected] Abstract. This paper is the first to investigate the power of the Cell Broadband Engine for state-of-the-art public-key cryptography. We pre- sent a high-speed implementation of elliptic-curve Diffie-Hellman (ECDH) key exchange for this processor, which needs 777000 cycles on one Syn- ergistic Processor Unit for a scalar multiplication on a 255-bit elliptic curve, including the costs for key verification and key compression. This cycle count is independent of inputs therefore protecting against timing attacks. This speed relies on a new representation of elements of the underlying finite field suited for the unconventional instruction set of this architec- ture. Furthermore we demonstrate that an implementation based on the multi- precision integer arithmetic functions provided by IBM’s multi-precision math (MPM) library would take at least 9660640 cycles. Comparison with implementations of the same function for other archi- tectures shows that the Cell Broadband Engine is competitive in terms of cost-performance ratio to other recent processors such as the Core 2 for public-key cryptography. Specifically, the state-of-the-art Galbraith-Lin-Scott ECDH software per- forms 27370 scalar multiplications per second using all four cores of a 2.5GHz Intel Core 2 Quad Q9300 inside a $400 computer, while the new software reported in this paper performs 24528 scalar multiplications per second on a Playstation 3 that costs just $279.
    [Show full text]