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Oversampling Data Converters Oversampling Data Converters 2B1611 Spring 2005 Ana Rusu Outline Introduction Oversampling Oversampling with Noise-Shaping Sigma-delta ADCs System Architecture Sigma-delta modulator architectures Decimation Filters Sigma-delta DACs System Architecture Interpolating Filters Summary 2B1611 Spring 2005 Ana Rusu Introduction Oversampling Noise-Shaping Data Converters Exchange resolution in time for resolution in amplitude using oversampling, feedback and digital filtering. An oversampling converter uses a noise-shaping modulator to reduce the in-band quantization noise (to achieve high resolution). The oversampling ratio (OSR) can vary usual from 8 to 256. The resolution of oversampling converter is proportional to the OSR. The bandwidth of the signal to be converted is inversely proportional to the OSR(=fs/2fB). Benefits of oversampling with noise shaping: +Relaxed transition band requirements for analog antialiasing and reconstruction filters Drawbacks of oversampling +Reduced matching tolerances with noise shaping: : +Reduced baseband quantization noise -Difficult to model and simulate power (high resolution) -Limited in bandwidth by the OSR +Very compatible with VLSI technology Solutions for drawbacks because most of the converter is digital Multi-bit quantizer +Provide an excellent means of trading Alternative architectures precision for speed +Single-bit noise-shaping uses one-bit DACs which are inherently linear 2B1611 Spring 2005 Ana Rusu Conventional Nyquist-rate A/D Converter Oversampled A/D Converter 2B1611 Spring 2005 Ana Rusu Oversampling (without noise-shaping) Sampling- Nyquist frequency Conventional ADC with fB ≈ 0.5fN ,fB=analog signal bandwidth, fN=Nyquist frequency (=2 fB), Oversampling Oversampled ADC with fB ≈ 0.5fN << 0.5fS, fS=sampling frequency, M(=OSR)= fS/2 fB 2B1611 Spring 2005 Ana Rusu Oversampling Quantization Noise Assume that the quantization noise e(k) is white and is independent of fS. Baseband noise For a discrete-time quantizer (which is not in overload) with a step size, ∆ and sampling frequency, fS the quantization noise power is distributed uniformly across the Nyquist bandwidth. 2B1611 Spring 2005 Ana Rusu Oversampling Power spectral density of the quantization error (e) is 2 2 ∆ 1 Ne(f ) = e / fs = ( )⋅ 12 fs The total quantization error power within the baseband f / 2 2 If fB=fS/2 , the baseband quantization noise power is s 2 ∆ S = ∫ N (f )df = e = B0 e 12 −fs / 2 2 If fB<fS/2, the baseband quantization noise power is fB ∆ 1 SB = ∫ Ne(f )df = ⋅ ⋅ 2fB = where M is the oversampling ratio (OSR): −fB 12 fs fS ⎛ 2f ⎞ S M = = S ⋅⎜ B ⎟ = B0 B0 ⎜ ⎟ M 2fB ⎝ fS ⎠ 2B1611 Spring 2005 Ana Rusu Oversampling ⎛ V ⎞ ⎜ ref ⎟ SignalPower _ at _ fin ⎛ Vin,rms⎞ N SNR = = 20log⎜ ⎟ = 20log⎜ 2 2 ⎟ = 20log⎜⎛2 3 M ⎟⎞ BasebandNoisePower ⎝ erms ⎠ ⎜ ∆ 1 ⎟ ⎝ 2 ⎠ ⎜ ⋅ ⎟ ⎝ 12 M ⎠ SNRmax[dB] = 6.02N +1.76dB +10log(M) It is seen that a doubling of M, only gives a decrease of the inband noise of 1/√2 which corresponds to a 3dB (which corresponds to 0.5 bits of resolution) improvement in SNR (DR). A much greater improvement in resolution with increasing M can be obtained by embedding the quantizer in a feedback loop: ∆ modulation or ∆Σ modulation(noise- shaping). 2B1611 Spring 2005 Ana Rusu Oversampling & Noise-Shaping Delta Modulator (Predictive Modulator) Delta-Sigma Modulator (Noise-Shaping Modulator) 2B1611 Spring 2005 Ana Rusu Delta Modulator (Predictive Modulator) The predictive modulator reduces the quantization noise by only detecting the change of the signal rather than the absolute signal value using a delta modulator. The drawback of a predictive modulator is the exhibition of slope overload for rapidly changing input signals. Noise-Shaping (Sigma-Delta) modulator is derived from delta modulator: is a delta modulator with an additional integrator in front of quantizer. Noise-Shaping modulator also performs only a coarse quantization of the input signal, but it employs filtering and negative feedback to shift a large amount of the quantization noise to higher frequencies out of the signal band. Thereby the inband quantization noise is reduced and high resolutions can be achieved. Out-of- band noise, including quantization noise, is suppressed by a subsequent digital LPF (decimation filter). The output of the digital filter can be resampled at a lower sampling rate if the filter provides adequate antialiasing, as well as noise suppression. 2B1611 Spring 2005 Ana Rusu Noise-Shaping: Delta-Sigma (Sigma-Delta) Modulator Integrator accumulates the difference between the input signal and quantization signal. Feedback keeps the integrator output near zero, thus minimizing the low- frequency difference between input and quantization signals. The summator takes the difference (Delta) ∆Σ modulator with 1-bit quantization: between the input signal and the feedback a summator, one-bit ADC (1-bit signal. The integrator accumulates or sums quantizer) is just a comparator, 2 (Sigma) this difference and feeds the result levels DAC can be an analog switch to back, via the ADC (quantizer) and DAC, to ± Vref. the summer. This force the output of the 1-bit DAC is inherently linear. modulator to track the average of the input. The average signal feedback should ideally be the same as the input signal. http://www.analog.com/Analog_Root/static/techSupport/designTools/interactiveTools/sdtutorial/sdtutorial.html 2B1611 Spring 2005 Ana Rusu Oversampling Σ∆ A/D Converters System Architecture Components of an oversampling ADC: Σ∆ Modulator (or noise-shaper), which shapes the quantization noise and push the majority of the inband noise to higher frequencies. It modulates the analog input signal to a simple digital code, normally an one- bit serial-stream using a sampling rate Σ∆ ADCs can be implemented with: much higher than the Nyquist rate. • Low-Pass Σ∆ Modulators Digital Filter with two components: • Band-Pass Σ∆ Modulators Low-pass filter – used to remove the In high frequency quantization noise and • Single-loop architecture to preserve the input signal. • Cascaded architecture Decimator (or down-sampler) – it With down samples the high frequency • Single-bit quantizer modulator output into a low frequency • Multibit quantizer output and does some pre-filtering on the quantization noise. 2B1611 Spring 2005 Ana Rusu Σ∆ Modulator Architectures • Low-pass Σ∆ Modulators First-order Σ∆ Modulator High-order Single-Loop Σ∆ Modulators High-order Cascaded Σ∆ Modulators Multibit Σ∆ Modulators • Band-pass Σ∆ Modulators 2B1611 Spring 2005 Ana Rusu Σ∆ Modulator Architectures First-order Σ∆ Modulator (First-order Noise-Shaping) Principle The block diagram of a 1st order single-bit Σ∆ modulator (interpolator structure) Vin,max=0.4V, and the quantizer levels are at ±0.5V. When the input approaches 0.4, the modulator output is dominated by positive pulses; when the input is around –0.4, the output Time-domain response has few positive pulses; for input around zero, the output oscillates between two levels. The input range must be kept in between the 2 quantizer levels. The local average of the output is efficiently computed by a decimator. 2B1611 Spring 2005 Ana Rusu First-order Σ∆ Modulator (First-order Noise-Shaping) Time-domain: the output of the integrator u[k] at the th k sampling period, kTS u[]k = x[k −1]− q[k −1]+ u[k −1] The 1-bit quantizer delivers a signal y[k] which is either Principle -∆/2 or +∆/2 depending on the sign of its input u[k]: ∆ The block diagram of a 1st order Σ∆ modulator y[]k = sgn(u[]k ) ⋅ 2 (interpolator structure) where ∆ is the quantizer step size. The quantization error e[k] can be defined as e[k] = y[k]− u[k] The quantization error is modeled as an additive error sequence, e(k), with the z-transform E(z). If the DAC is ideal: q[k] = y[k] the output is y[]k = x[k −1]+ (e[k]− e[k −1]) Converting this expression to the z-domain Y(z) = z −1 ⋅ X(z) + (1− z −1 )E(z) -1 Signal Transfer Function STF(z)=HX(z)=Y(z)/X(z)=z -1 Noise Transfer Function NTF(z)=HE(z)=E(z)/X(z)=1-z 2B1611 Spring 2005 Ana Rusu First-order Σ∆ Modulator (First-order Noise-Shaping) jωT 2πfj/ f z-domain: z = e = e S The transfer function for the delaying discrete- Principle time integrator ( has a pole at dc) is The linear discrete-time model −1 of the modulator H(z) = z 1− z−1 Y(z) = H(z)⋅[X(z) − Y(z)]+ E(z) Y(z) = z−1 ⋅ X(z) + (1− z−1)E(z) where STF(z)=Hs(z)= z-1 is a simply delay and NTF(z)=HE(z) is a first-order HP filter −1 H E (z) = NTF(z) =1− z thus, in the output Y(z), the signal is only delayed, while the quantization error is filtered by the first-order high-pass filter. 2B1611 Spring 2005 Ana Rusu Frequency domain: to estimate the SNR and DR, we substitute z = e jωT = e2πfj/ fS for physical frequencies. where T=1/fS. Thus If Ne(f) is the power spectral density of the quantization error e(k), the spectral power density of the quantization noise in the modulator output is If it is assumed that the spectrum of the quantization error is white and if the quantization error power, SQ is then 2B1611 Spring 2005 Ana Rusu Frequency domain (cont): To determine the baseband quantization noise power at the modulator output, we assume that the quantization noise is white with a uniform spectral density SQ/fS, and the oversampling ratio is M= fS /(2 fB ). Then: 2B1611 Spring 2005 Ana Rusu First-order Σ∆ Modulator (First-order Noise-Shaping) Frequency domain (cont): The maximum signal-to-noise ratio (SNR) for a full-scale sinusoidal input signal (with an amplitude of at most ∆/2) is SNRmax[dB] = 6.02N +1.76 − 5.17 + 30log(M) Conclusion: Each doubling of M results in a 9 dB increase in SNR (DR), which corresponds to 1.5 bits of resolution.
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