Oversampling Data Converters
2B1611 Spring 2005 Ana Rusu Outline
Introduction Oversampling Oversampling with Noise-Shaping Sigma-delta ADCs System Architecture Sigma-delta modulator architectures Decimation Filters Sigma-delta DACs System Architecture Interpolating Filters Summary
2B1611 Spring 2005 Ana Rusu Introduction Oversampling Noise-Shaping Data Converters
Exchange resolution in time for resolution in amplitude using oversampling, feedback and digital filtering. An oversampling converter uses a noise-shaping modulator to reduce the in-band quantization noise (to achieve high resolution). The oversampling ratio (OSR) can vary usual from 8 to 256. The resolution of oversampling converter is proportional to the OSR. The bandwidth of the signal to be converted is inversely proportional to the OSR(=fs/2fB). Benefits of oversampling with noise shaping: +Relaxed transition band requirements for analog antialiasing and reconstruction filters Drawbacks of oversampling +Reduced matching tolerances with noise shaping: : +Reduced baseband quantization noise -Difficult to model and simulate power (high resolution) -Limited in bandwidth by the OSR +Very compatible with VLSI technology Solutions for drawbacks because most of the converter is digital Multi-bit quantizer +Provide an excellent means of trading Alternative architectures precision for speed +Single-bit noise-shaping uses one-bit DACs which are inherently linear 2B1611 Spring 2005 Ana Rusu Conventional Nyquist-rate A/D Converter
Oversampled A/D Converter
2B1611 Spring 2005 Ana Rusu Oversampling (without noise-shaping) Sampling- Nyquist frequency
Conventional ADC with fB ≈ 0.5fN ,fB=analog signal bandwidth, fN=Nyquist frequency (=2 fB), Oversampling
Oversampled ADC with fB ≈ 0.5fN << 0.5fS, fS=sampling frequency, M(=OSR)= fS/2 fB
2B1611 Spring 2005 Ana Rusu Oversampling
Quantization Noise
Assume that the quantization noise e(k)
is white and is independent of fS. Baseband noise For a discrete-time quantizer (which is not in overload) with a step size, ∆ and
sampling frequency, fS the quantization noise power is distributed uniformly across the Nyquist bandwidth.
2B1611 Spring 2005 Ana Rusu Oversampling
Power spectral density of the quantization error (e) is
2 2 ∆ 1 Ne(f ) = e / fs = ( )⋅ 12 fs
The total quantization error power within the baseband
f / 2 2 If fB=fS/2 , the baseband quantization noise power is s 2 ∆ S = ∫ N (f )df = e = B0 e 12 −fs / 2 2 If fB 2B1611 Spring 2005 Ana Rusu Oversampling ⎛ V ⎞ ⎜ ref ⎟ SignalPower _ at _ fin ⎛ Vin,rms⎞ N SNR = = 20log⎜ ⎟ = 20log⎜ 2 2 ⎟ = 20log⎜⎛2 3 M ⎟⎞ BasebandNoisePower ⎝ erms ⎠ ⎜ ∆ 1 ⎟ ⎝ 2 ⎠ ⎜ ⋅ ⎟ ⎝ 12 M ⎠ SNRmax[dB] = 6.02N +1.76dB +10log(M) It is seen that a doubling of M, only gives a decrease of the inband noise of 1/√2 which corresponds to a 3dB (which corresponds to 0.5 bits of resolution) improvement in SNR (DR). A much greater improvement in resolution with increasing M can be obtained by embedding the quantizer in a feedback loop: ∆ modulation or ∆Σ modulation(noise- shaping). 2B1611 Spring 2005 Ana Rusu Oversampling & Noise-Shaping Delta Modulator (Predictive Modulator) Delta-Sigma Modulator (Noise-Shaping Modulator) 2B1611 Spring 2005 Ana Rusu Delta Modulator (Predictive Modulator) The predictive modulator reduces the quantization noise by only detecting the change of the signal rather than the absolute signal value using a delta modulator. The drawback of a predictive modulator is the exhibition of slope overload for rapidly changing input signals. Noise-Shaping (Sigma-Delta) modulator is derived from delta modulator: is a delta modulator with an additional integrator in front of quantizer. Noise-Shaping modulator also performs only a coarse quantization of the input signal, but it employs filtering and negative feedback to shift a large amount of the quantization noise to higher frequencies out of the signal band. Thereby the inband quantization noise is reduced and high resolutions can be achieved. Out-of- band noise, including quantization noise, is suppressed by a subsequent digital LPF (decimation filter). The output of the digital filter can be resampled at a lower sampling rate if the filter provides adequate antialiasing, as well as noise suppression. 2B1611 Spring 2005 Ana Rusu Noise-Shaping: Delta-Sigma (Sigma-Delta) Modulator Integrator accumulates the difference between the input signal and quantization signal. Feedback keeps the integrator output near zero, thus minimizing the low- frequency difference between input and quantization signals. The summator takes the difference (Delta) ∆Σ modulator with 1-bit quantization: between the input signal and the feedback a summator, one-bit ADC (1-bit signal. The integrator accumulates or sums quantizer) is just a comparator, 2 (Sigma) this difference and feeds the result levels DAC can be an analog switch to back, via the ADC (quantizer) and DAC, to ± Vref. the summer. This force the output of the 1-bit DAC is inherently linear. modulator to track the average of the input. The average signal feedback should ideally be the same as the input signal. http://www.analog.com/Analog_Root/static/techSupport/designTools/interactiveTools/sdtutorial/sdtutorial.html 2B1611 Spring 2005 Ana Rusu Oversampling Σ∆ A/D Converters System Architecture Components of an oversampling ADC: Σ∆ Modulator (or noise-shaper), which shapes the quantization noise and push the majority of the inband noise to higher frequencies. It modulates the analog input signal to a simple digital code, normally an one- bit serial-stream using a sampling rate Σ∆ ADCs can be implemented with: much higher than the Nyquist rate. • Low-Pass Σ∆ Modulators Digital Filter with two components: • Band-Pass Σ∆ Modulators Low-pass filter – used to remove the In high frequency quantization noise and • Single-loop architecture to preserve the input signal. • Cascaded architecture Decimator (or down-sampler) – it With down samples the high frequency • Single-bit quantizer modulator output into a low frequency • Multibit quantizer output and does some pre-filtering on the quantization noise. 2B1611 Spring 2005 Ana Rusu Σ∆ Modulator Architectures • Low-pass Σ∆ Modulators First-order Σ∆ Modulator High-order Single-Loop Σ∆ Modulators High-order Cascaded Σ∆ Modulators Multibit Σ∆ Modulators • Band-pass Σ∆ Modulators 2B1611 Spring 2005 Ana Rusu Σ∆ Modulator Architectures First-order Σ∆ Modulator (First-order Noise-Shaping) Principle The block diagram of a 1st order single-bit Σ∆ modulator (interpolator structure) Vin,max=0.4V, and the quantizer levels are at ±0.5V. When the input approaches 0.4, the modulator output is dominated by positive pulses; when the input is around –0.4, the output Time-domain response has few positive pulses; for input around zero, the output oscillates between two levels. The input range must be kept in between the 2 quantizer levels. The local average of the output is efficiently computed by a decimator. 2B1611 Spring 2005 Ana Rusu First-order Σ∆ Modulator (First-order Noise-Shaping) Time-domain: the output of the integrator u[k] at the th k sampling period, kTS u[]k = x[k −1]− q[k −1]+ u[k −1] The 1-bit quantizer delivers a signal y[k] which is either Principle -∆/2 or +∆/2 depending on the sign of its input u[k]: ∆ The block diagram of a 1st order Σ∆ modulator y[]k = sgn(u[]k ) ⋅ 2 (interpolator structure) where ∆ is the quantizer step size. The quantization error e[k] can be defined as e[k]= y[k]− u[k] The quantization error is modeled as an additive error sequence, e(k), with the z-transform E(z). If the DAC is ideal: q[k]= y[k] the output is y[]k = x[k −1]+ (e[k]− e[k −1]) Converting this expression to the z-domain Y(z) = z −1 ⋅ X(z) + (1− z −1 )E(z) -1 Signal Transfer Function STF(z)=HX(z)=Y(z)/X(z)=z -1 Noise Transfer Function NTF(z)=HE(z)=E(z)/X(z)=1-z 2B1611 Spring 2005 Ana Rusu First-order Σ∆ Modulator (First-order Noise-Shaping) jωT 2πfj/ f z-domain: z = e = e S The transfer function for the delaying discrete- Principle time integrator ( has a pole at dc) is The linear discrete-time model −1 of the modulator H(z) = z 1− z−1 Y(z) = H(z)⋅[X(z) − Y(z)]+ E(z) Y(z) = z−1 ⋅ X(z) + (1− z−1)E(z) where STF(z)=Hs(z)= z-1 is a simply delay and NTF(z)=HE(z) is a first-order HP filter −1 H E (z) = NTF(z) =1− z thus, in the output Y(z), the signal is only delayed, while the quantization error is filtered by the first-order high-pass filter. 2B1611 Spring 2005 Ana Rusu Frequency domain: to estimate the SNR and DR, we substitute z = e jωT = e2πfj/ fS for physical frequencies. where T=1/fS. Thus If Ne(f) is the power spectral density of the quantization error e(k), the spectral power density of the quantization noise in the modulator output is If it is assumed that the spectrum of the quantization error is white and if the quantization error power, SQ is then 2B1611 Spring 2005 Ana Rusu Frequency domain (cont): To determine the baseband quantization noise power at the modulator output, we assume that the quantization noise is white with a uniform spectral density SQ/fS, and the oversampling ratio is M= fS /(2 fB ). Then: 2B1611 Spring 2005 Ana Rusu First-order Σ∆ Modulator (First-order Noise-Shaping) Frequency domain (cont): The maximum signal-to-noise ratio (SNR) for a full-scale sinusoidal input signal (with an amplitude of at most ∆/2) is SNRmax[dB] = 6.02N +1.76 − 5.17 + 30log(M) Conclusion: Each doubling of M results in a 9 dB increase in SNR (DR), which corresponds to 1.5 bits of resolution. Because of the spectral tones that result from the correlation of the quantization error with the input, the practical SNR and DR of a 1st order single-bit Σ∆ modulators is not so large as this result indicates. Note: Another 1st order Σ∆ modulator structure: ”error-feedback” – is sensitive to coefficients mismatch. 2B1611 Spring 2005 Ana Rusu High-order Σ∆ Modulators High-order (L≥2) Σ∆ Modulators approaches: Single-loop Σ∆ modulators with Lth-order differentiator in the forward path and multi feedback paths- This approach is to increase the order of the loop filter such that a more effective noise shaping is achieved. Drawback: The major limitation of this solution is the difficulty of designing these high-order loops such that stability can be guaranteed under the various operating conditions. Potential instability for L≥3 that can be avoided by constraining signal range. Improved stability using multibit quantizer. An increase in SNR can be achieved if the zeros of NTF are distributed inside the signal band instead of locating all of them at dc (z=1)- by using local resonators Cascaded (multi-stage noise-shaping) Σ∆ modulators - Cascaded sigma-delta structures realize high-order noise shaping by cascading sigma-delta stages of second-order or first-order to avoid instability, and are suited for high-speed ADC with low OSR. Drawback: Sensitive to mismatches between the analog and digital circuitry. Due to the finite opamp gain and interstage gain mismatch, quantization error from the first stage leaks into the output of the cascade. 2B1611 Spring 2005 Ana Rusu High-Order Single-Loop Σ∆ Modulators (Noise Differencing Modulators) Noise differencing modulators can be implemented with a single quantizer and L nested loops. These Σ∆ modulators feed the output signal back several times and use several integrators in the feedforward path. However, limit cycle instability occurs for L>2. For an Lth order differentiator 1-bit Σ∆ modulator (Chain of integrators with distributed feedbacks) Y(z) = STF(z)⋅ X(z) + NTF(z)⋅ E(z) Y(z) = z−n ⋅ X(z) + (1− z−1)L E(z) −n −1 L Hx (z) = STF(z) = z ;HE (z) = NTF(z) = (1− z ) E(z) 2B1611 Spring 2005 Ana Rusu High-Order Single-Loop Σ∆ Modulators Σ∆ Modulator Order Effects 2B1611 Spring 2005 Ana Rusu High-Order Single-Loop Σ∆ Modulators Baseband Quantization noise for a Lth order 1-bit Σ∆ Modulator As for the 1st order modulator, we assume that the quantization noise is white with an uniform spectral density SQ/fS. Then, the quantization noise remaining in the baseband of the modulator output is ⎛ 3(2L+1) ⎞ SNRmax[dB] =10log⎜ ⎟ +10(2L +1)log(M) ⎝ 2π2L ⎠ Conclusion: Each doubling of M (OSR) now improve SNR by 6(L+0.5)dB or by (L+0.5)bits of resolution. 2B1611 Spring 2005 Ana Rusu Example: Second-Order Single-Bit Σ∆ Modulators Approach 1 Y(z) = z−1 ⋅ X(z) + (1− z−1)2E(z) The traditional 2nd order Σ∆ modulator is implemented using a non-delaying configuration for the first integrator followed by the second integrator in a delaying configuration. Approach 2 Y(z) = z−2 ⋅ X(z) + (1− z−1)2E(z) Conclusion: SNRmax[dB] = 6.02N +1.76 −12.9 + 50log(M) Each doubling of M results in a 15dB (2.5 bits) increase in SNR. 2B1611 Spring 2005 Ana Rusu Alternative Architectures for High-Order Single-Loop Σ∆ Modulators Chain of resonators with distributed feedback • Spread zeros over band-of-interest to improve SNR – using local resonators in an interpolative architecture Conclusions • Out-of-band noise increases as the noise- shaping order increases • Out-of-band noise peak controlled by poles of NTF 2B1611 Spring 2005 Ana Rusu Circuit Nonidealities Effects in Σ∆ Modulators Nonlinearities in single-bit Σ∆ Modulators • The quantizer is strongly nonlinear, but we use a linear model for analysis. Some of the effects caused by the nonlinearity of the quantizer (degrades the SNDR of Σ∆ modulator) are: - Dead zones: small, fast changes in the input signal cannot be sensed by the modulator, under certain conditions - Idle tones: for dc inputs, but not only, having rational values, the output of the modulator is periodic, its spectrum having discrete components. If these components are located inside the baseband, they will affect SNDR - SNDR degradation for large input amplitudes. In this case the quantizer saturates and the quantization noise increase. - Instability for order higher than 2. • Integrators Nonlinearity ( nonlinear opamp dc gain, nonlinear capacitors) 2B1611 Spring 2005 Ana Rusu Circuit Nonidealities Effect in Σ∆ Modulators Integrator Gain Errors −1 g0 ⋅(1+ ε)⋅ z If the integrator includes a gain factor g0, then the transfer function is H(z) = 1− z−1 Small deviations of gain from unity have little effect on the overall performance, providing a large gain in the feedback loop. 10% gain accuracy is usual tolerable. Integrator Leakage (finite opamp dc gain) If the opamp has a finite gain of A0, then the transfer function is z−1 H(z) = where P =1− 1 −1 0 A 1− P0 ⋅ z 0 Finite opamp gain moves pole at z=1 left by 1/A0. Flattens out noise at low frequency. Typically, require A0>OSR/π. 2B1611 Spring 2005 Ana Rusu Circuit Nonidealities Effect in Σ∆ Modulators Integrator Nonlinearity (nonlinear opamp dc gain, nonlinear capacitors) Solutions: Fully differential implementation, increase dc gain • Opamps: finite and nonlinear dc gain, SR, GBW, settling time • Switches: on-resistance, thermal noise Comparator : hysteresis (do not need precise comparators), offset (attenuated by the opamp dc gain). Must be fast enough DAC Linearity is very important - Single-bit DAC is inherently linear - Multibit DACs need linearization techniques (DEM, calibration,…) 2B1611 Spring 2005 Ana Rusu Circuit Nonidealities Effect in Σ∆ Modulators (from Medeiro) 2B1611 Spring 2005 Ana Rusu Stability Theory for Σ∆ Modulators Stability is an important issue because of the feedback loop. The selection of modulator coefficients need to take into account the loop stability. A modulator is stable if the input to the quantizer does not become overloaded, i.e. the quantizer error e(k) ≤±∆/2. The first-order modulators are inherently stable. All high-order (L>2) modulators are conditionally stable. Modulators with multibit quantizer have an improved stability There are many rigorous tests to guarantee stability For a single-stage modulators with 1-bit quantizer αH(z) 1 Y(z) = X(z) + E(z) 1+ αH(z)F(z) 1+ αH(z)F(z) 2B1611 Spring 2005 Ana Rusu Stability Theory for Σ∆ Modulators Stability of a single-stage modulators with 1-bit quantizer jω Stability can be achieved by keeping NTF(e ) ≤ 1.5 for 0 ≤ω≤π The modulator can be made more stable by placing the poles of NTF closer to its zeros, but the SNR (and DR) is degraded since the out-of-band gain of NTF it also reduced. Stability is also related to the input signal level. Typically need 50-80% of ∆ for stable input range. “Signal overload” may cause a conditionally stable modulator. Need additional mechanism to detect instability (look at input to quantizer, look for long strings of 1s or 0s at the comparator output) and to force (reset integrators) the loop to become stable. 2B1611 Spring 2005 Ana Rusu Implementation of Analog Σ∆ Modulators Implementation of Analog Integrators: Continuous-time: Active RC integrators MOSFET-C gm-C Discrete-time: Switched-Current Integrators Switched-Capacitor Integrators Continuous-Time Integrators + Higher frequency range + S/H is inside the loop, thus the errors introduced by its nonidealities are shaped as the quantization noise - Integrator output is sensitive to jitter - Needs large capacitors, linear resistors, low-noise and linear opamps - Frequency response of the loop is governed by the capacitors and MOS transconductance 2B1611 Spring 2005 Ana Rusu Implementation of Analog Σ∆ Modulators Switched-Capacitor Integrators + Easy to be simulated + Compatible with VLSI CMOS technology + Insensitive to jitter + Loop filter parameters are set by capacitor ratios ( highly accurate, better than1%) - Large capacitors required for high SNR (kt/C noise limit) - Difficult to prototype because the capacitor values are small, comparable with the parasitic capacitance an a breadboard. 2B1611 Spring 2005 Ana Rusu Implementation of Analog Σ∆ Modulators Single-ended vs. fully-differential SC Integrators Most of the Σ∆ modulators use fully differential SC implementation because: - Doubles the signal swing and increase the dynamic range by 6dB - Common-mode signals that may couple to the signal through the supply lines and substrate are cancelled - Charge injected by switches is reduced Single-ended Fully-Differential 2B1611 Spring 2005 Ana Rusu Implementation of Analog Σ∆ Modulators Switched-Current Integrators + High speed + Fully compatible to digital process technology + Ideal for mixed signal in CMOS tecnology - Sensitive to switch parasitics and charge injection - Current sources must be cascode to reduce the output conductance (high supply voltage) -Large Veff needed to reduce sensitivity to VT mismatch (high power dissipation) 2B1611 Spring 2005 Ana Rusu Implementation of Analog Σ∆ Modulators Example of CMOS SC Implementation for a single-ended 1st order Σ∆ Modulator The comparator latches on the falling edge of Φ2 1. SC implementation with two input capacitances 2. SC implementation with only one input capacitance 2B1611 Spring 2005 Ana Rusu Implementation of Analog Σ∆ Modulators Example of CMOS SC Implementation for a fully-differential 2nd order Σ∆ Modulator 2B1611 Spring 2005 Ana Rusu Implementation of Analog Σ∆ Modulators Opamp topology selection • Linear settling⇒high slew rate • High speed⇒single-stage opamp • Low distortion⇒dc gain>60dB • Wide dynamic range⇒low noise and large output swing • Reduced distortion⇒differential architecture Fully-differential SC approach: + Large commom-mode rejection + 3dB increase in SNR Comparator topology selection • A latched comparator • For high resolution is used a differential pair as input transconductor 2B1611 Spring 2005 Ana Rusu Implementation of Analog Σ∆ Modulators OTAs Comparator Telescopic cascode Folded cascode Latched comparator Best speed-power figure Good speed-power figure Note: The power dissipation of a Σ∆ modulator is a strong function of the dynamic range. 2B1611 Spring 2005 Ana Rusu Design Example: A 3rd order Σ∆ Modulator (Johns&Martin) 2B1611 Spring 2005 Ana Rusu 2B1611 Spring 2005 Ana Rusu A 3rd order single-stage modulator with multiple feedback paths and results the coefficients 2B1611 Spring 2005 Ana Rusu 2B1611 Spring 2005 Ana Rusu Circuit Implementation The fully-differential SC implementation of the 3rd order modulator 2B1611 Spring 2005 Ana Rusu Cascaded Σ∆ Modulators (Multi stAge noise SHaping=MASH Σ∆ Modulators ) Cascaded Σ∆ Modulator = Cascaded of two or more low-order and stable Σ∆ stages Quantization error of each stage is converted by the succeeding stages. The errors of all but the last single-loop modulator are then digitally cancelled. The cancellation of lower-order quantization noise terms depends on the precision of analog signal paths. Order of the noise shaping equals the sum of the orders of all stages No potential instability (each stage is only 1st or 2nd order) Scaling coefficients are used to control the input of the next stage and to utilize the full dynamic range of the next stage. 2B1611 Spring 2005 Ana Rusu Cascaded Σ∆ Modulators Second-order (1-1) Cascaded Σ∆ Modulator −2 −1 2 Y(z) = z X(z) + (1− z ) E2(z) 2B1611 Spring 2005 Ana Rusu Cascaded Σ∆ Modulators Third-order Cascaded Σ∆ Modulators Approaches: a. (1-1-1) cascaded modulators b. (2-1) cascaded modulators a. Third-order (1-1-1) Cascaded Modulator −3 −1 3 Y(z) = z X(z) + (1− z ) E3(z) 2B1611 Spring 2005 Ana Rusu Cascaded Σ∆ Modulators b. Third-order (2-1) Cascaded Modulator with scaling coefficients Advantages of (2-1): + It has better tone performance than (1-1-1) cascade for the same degree of noise cancellation because of second-order noise shaping in the first stage + Design flexibility The goal of the signal scaling is to maximize the overload level of the modulator using all of the available swing at the output of each integrator without clipping. Choose ai3,au3 based on the conventional configuration for overload, noise floor, noise tones. Choose af1, af2, af3, to limit voltage swings at integrator outputs. Compute remaining gain factors. 2B1611 Spring 2005 Ana Rusu Cascaded Σ∆ Modulators 4th order Cascaded Σ∆ Modulators Example of (2-2) MASH Implementation −4 1 −1 4 Yc(z) = z X(z) − (1− z ) Q2(z) b1 2B1611 Spring 2005 Ana Rusu Multibit Σ∆ Modulators The dynamic range of an ideal L-order multibit noise-difference sigma-delta modulator is given by ⎛ ⎞ 2L +1 B 2 where M is the oversampling ratio, L order of noise DR = 3 ⋅⎜ 2L +1⎟⋅ M ⋅⎜⎛2 −1⎟⎞ 2 ⎜ 2L ⎟ ⎝ ⎠ shaping and B is the number of bits in the ⎝ π ⎠ quantizer. Advantages Limitations + Reduces the OSR requirements - Feedback DAC nonlinearity - The + Out-of-band noise is reduced independent of DAC linearity errors are not shaped. the OSR or loop order (by 6 dB for every The DAC must be nearly as linear as additional bit) the complete converter. + Increases signal bandwidth for low OSR - Practical limitation of number of + Better stability with more aggressive noise feedback bits (6 bits). transfer functions + Reduces the decimation filter complexity an power consumption + Suitable for low-power, wideband applications 2B1611 Spring 2005 Ana Rusu Multibit Σ∆ Modulators Multibit Randomizer DAC Dynamic element matching (DEM) in a 3 bit DAC • The overall sigma-delta converter linearity and resolution are limited by the precision of the multibit DAC. • Randomization is used to effectively spread the nonlinearity over the whole frequency range. This white noise produced by mismatch is not shaped by feedback loop and will appear as more noise floor. • Many dynamic element-matching (DEM) techniques have been proposed to improve the accuracy of the internal D/A converter: noise-shaping, Data- Weighted-Averaging (DWA), etc. 2B1611 Spring 2005 Ana Rusu Multibit Σ∆ Modulators Digital Calibration Digitally corrected multibit Σ∆ A/D Converter • Digital calibration idea: the feedback loop forces the in-band frequency of x1(n) to very closely equal u(n) and thus x1(n) is still linearly related to u(n). Then, y(n) equals x1(n) if its nonlinearity equals that of the DAC • The DAC nonlinearity is stored in a word look-up RAM inside the digital correction block during the calibration phase. 2B1611 Spring 2005 Ana Rusu Comparison of Modulator Architectures ( from Norsworthy) 2B1611 Spring 2005 Ana Rusu Bandpass Σ∆ Modulators Used for A/D conversion of narrowband, high frequency signals. Applications: RF communication systems, spectrum analyzers, special purpose instrumentation for narrow-band sources, narrow BW signals digitization at radio or intermediate frequency AM, FM, cellular instrumentation (NMR etc.) In a digital radio receiver is convenient to perform the A/D conversion as close as possible to the antenna. ADC of IF signal alleviates problems due to DC offset, 1/f noise and I/Q channel mismatch as occur in conventional receivers. Conventional receiver using baseband ADC ADC performed at IF 2B1611 Spring 2005 Ana Rusu Bandpass Σ∆ Modulators Operate in the same manner as low-pass Σ∆ modulators, but for high-frequency and narrow-band signals by placing nulls in the quantization noise spectrum across the band of interest. The bandpass transfer function is realized by choosing H(z) (is a resonator) to have high gain near center frequency, f0. NTF shapes quantization noise to be small near center frequency. Oversampling ratio (OSR=M) is ratio of sampling frequency to twice bandwidth and is not related to centre frequency f M = S 2f∆ The resonator can be implemented as a discrete-time filter (in SC or SI technology) or as a continuous-time filter (using LC or GmC filters). The quantizer can be single- bit or multibit. Applications: RF communication systems, spectrum analyzers, special purpose instrumentation for narrow-band sources, narrow BW signals digitization at radio or intermediate frequency AM, FM, cellular instrumentation (NMR etc.) 2B1611 Spring 2005 Ana Rusu Bandpass Σ∆ Modulators Components: • Resonator – a bandpass filter of order 2N, N=1,2,... • Quantizer (1 bit or multibit) The signal transfer function is a band-pass one, whereas the noise-transfer function is a band rejected one and has the following characteristics: f ⋅(2N−1) - Center frequency is f = S o 4 - Bandwidth is f 2f = S ∆ M Lowpass to Bandpass transformation: The bandpass topology can easily be derived from lowpass topology with a transformation in the z domain (that preserves stability properties): z −1 → −z −2 For the 2nd order BP Σ∆ modulator the DR increases as for the 1st order LP Σ∆ modulator. 2B1611 Spring 2005 Ana Rusu Bandpass Σ∆ Modulators nd A 2 order bandpass (BP) modulator with fo=fS/4 H(z) is a resonator that has an infinite gain at the frequency f /4 S H(z) = z z2+1 Pol-zero locations of the noise transfer function Zero at z=1 Zeros at ±j st nd 1 order LP: lowpass zeros placed near DC 2 order BP: bandpass zeros placed around f0≠0 2B1611 Spring 2005 Ana Rusu Sigma-Delta A/D Converters Decimation Filters - to remove the out-of-band quantization noise and to enable resampling of the ∆Σ modulator output at a lower sampling rate. It does not result in any loss of information since the bandwidth of the original signal was fB. 2B1611 Spring 2005 Ana Rusu Decimation Filters Decimation by M Decimation reduce the sampling rate F by an integer factor, M. The input signal x(n) is first digitally filtered by a LPF (low-pass filter) h(n) with a digitally cutoff frequency of π/M. LPF removes all signal energy in x(n) above π/M to avoid aliasing in the decimation process. The band-limited signal, w(n) can then be resampled by discarding M-1 out of every M samples (sampling rate compression) to produce the output y(m) at a rate F/M that is free of aliasing. In practice, this process is typically performed by computing only one out of every M outputs of the digital filter. The digital filter is actually implemented at the low rate F/M. 2B1611 Spring 2005 Ana Rusu Decimation Filters Decimation filtering is commonly accomplished using FIR (finite impulse response) or IIR (infinite impulse response) filters. For a specified passband ripple and stopband attenuation, the number of coefficients needed in an FIR filter is proportional to fS/fT, where fS is the sampling rate of the input and fT is the width of the filter’s transition band (between the passband and the stop band). The decimation filtering can be accomplished in one stage or multistages (two or more). In many oversampling ADCs, the decimation filter has a very narrow passband relative to the sampling rate of the input. Than, the ratio fS/fT is quite high. If a single FIR stage is used for decimation from fS (for high sampling rate) to the Nyquist rate, the number of coefficients multiplications needed can be too high for a practical, power-efficient implementation. Solution: multistage decimation. 2B1611 Spring 2005 Ana Rusu Decimation Filters Multistage decimation 2B1611 Spring 2005 Ana Rusu Sigma-Delta D/A Converters The processes of decimation and interpolation are effect duals. Interpolation Filters – to increase the sampling rate of a discrete-time signal by a factor M, M-1 zero valued samples are inserted between the Nyquist rate samples. Then, a digital low-pass filter is used to remove the spectral images between the baseband and the image at fS=M•fN. 2B1611 Spring 2005 Ana Rusu Interpolation Filters Interpolating by L The input signal x(n), sampled at a rate F, is first increased in sampling rate by inserting L-1 zero-valued samples between each sample of x(n). The intermediate signal w(m) at a rate L•F contains the desired baseband information of x(n), but it also has L-1 imaged replications of this spectrum at frequencies above π/L that are undesired. These images are removed by a low-pass filter. 2B1611 Spring 2005 Ana Rusu Interpolation Filters Multistage interpolation filter Reconstruction filter 2B1611 Spring 2005 Ana Rusu Sigma-Delta Data Converters Digital Filter Design Considerations The design of a decimator or interpolator basically resolves around the design of a digital LPF with a single or multiple stopbands. Because of the multirate and/or multistage considerations, many of the classical filter design techniques are often ruled out in favor of designs that can take better advantage of the multirate criteria and achieve a more effective design. Use architectures that minimize the coefficient word lengths, eliminate the need for a dedicated high-speed parallel multiplier, reduce the memory storage requirements, or make the program control simpler. An approach to suppressing quantization noise that would be imaged into the baseband upon resampling is to place zeros at integer multiples of the resampling frequency fS/M. A convenient means of placing zeros at multiples of fS/M is to use a sinc filter. 2B1611 Spring 2005 Ana Rusu Sigma-Delta Data Converters Digital Filter Design Considerations sincL+1 is a cascaded of L+1 of averaging filters. An averaging filter is a linear-phase filter, with symmetric coefficients. If M is power of 2, is easy to implement (shift left). and for sinc results Frequency response ( z=ejω ) 2B1611 Spring 2005 Ana Rusu Sigma-Delta Data Converters sincL+1 Filter Implementation A sinc filter is most efficiently implemented by cascading L+1 stages of accumulators operating at the high sampling rate, followed by L+1 stages of cascaded differentiators operating at the low sample rate. Such architectures are inherently stable. The transfer function for this implementation of a sincL+1 decimation filter is 2B1611 Spring 2005 Ana Rusu Simulation Requirements for Σ∆ modulators • Simulation and modeling of the Σ∆ modulator is one of the most important issues in oversampling data converter design. • The design of oversampling data converters requires a behavioral simulation capability because of the need to simulate long data traces. The device level simulation using SPICE simulator is too slow for efficient design because of oversampling and fast transients in switching. • Simulation approaches: - Finite-Difference equations based on the z-transform: MIDAS, SWITCAP, TOSCA, etc. - Table lookup models - Time domain macromodels (only for transient response) - Circuit based macromodels 2B1611 Spring 2005 Ana Rusu Summary • Avantages of Oversampling • Advantages of Oversampling with Noise Shaping • Σ∆ A/D Converters • Σ∆ Modulator Architectures • Alternative approaches for high performance Σ∆ modulators • Circuit Nonidealities Effects • Implementation Issues of Analog Σ∆ Modulators • Decimation Filters • Σ∆ D/A Converters • Interpolation Filters 2B1611 Spring 2005 Ana Rusu