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Instruction Cycles & Bus Interconnect

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Instruction Cycles & Bus Interconnect Class Feedback • How is the 1st Lecture on the Computer Architecture Overview? – Is the amount of info too much, or not enough ? COMP 212 Lecture 2 – Is it difficult to understand ? Which part is difficult? Fall Semester, 2008 – Is the pace of the lecture okay ? Too fast , or about right ? – Other questions ? Instruction Cycles & Bus • My expectations: you will be okay if Interconnect – Some gory details are for your information only, no need to meorize them. – Understand lecture summary and review questions. – Do the homework, Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2 Z. Li, 2008 Lecture #1 Summary Lecture #1 Summary • Functional overview of computer: • Computer Components & Organization – Data processing: – CPU: computing and logics, process data, e.g. addition, multiplication » e.g. play MP3 music, encoding a picture into JPEG – Memory: store data for processing and presentation – Data movement: – I/O: communicate with computer peripherals like keyboard, camera, » moving data between computer and peripherals, or communicate with disks. remote devices, – Bus: mechanism for inter-connecting CPU, Mem and I/O devices » e.g, email, web access, youtube (invented with DEC PDP-8) – Data storage: • All modern computers are von Neumann architecture » store data for future use – Which has a stored program, instead of re-wiring circuits » Database, personal picture store – First implementation, IAS computer at Princeton Comp 212 Computer Org & Arch 3 Z. Li, 2008 Comp 212 Computer Org & Arch 4 Z. Li, 2008 Lecture #1 Summary Number System • Modern Computer Has been thru 3 Generations • Relationship between Decimal, Binary and Hex numbers: – Early years are Vacuum Tubes, e.g ENIAC Decimal Binary Hex – Second generations are Transistor based 0 0000 0h 1 0001 1h – Third generations are Integrated Circuits Based 2 0010 2h 3 0011 3h 4 0100 4h • Key Tricks for Architectural improvements 5 0101 5h 6 0110 6h – Pipeline: break up command executions into stages, allow parallelism 7 0111 7h 8 1000 8h among commands 9 1001 9h 10 1010 Ah – Superscalar: 11 1011 Bh 12 1100 Ch – 13 1101 Dh Multi-Core: parallel processors, APP level parallelism with OS support 14 1110 Eh 15 1111 Fh Comp 212 Computer Org & Arch 5 Z. Li, 2008 Comp 212 Computer Org & Arch 6 Z. Li, 2008 Overview of Lecture #2 Re-Cap of von Neumann Machine • In this lecture we will discuss computer component inter- • Von Neumann Architecture connect, – Data & Programs are stored in a single addressable memory – Overview of Computer Functions and Components – Content of memory is located/retrieved by address – Instruction Cycles and Interrupts – Sequential execution of commands – Bus Structure and example: PCI Comp 212 Computer Org & Arch 7 Z. Li, 2008 Comp 212 Computer Org & Arch 8 Z. Li, 2008 Program Concept What is a program? • Why program? • A sequence of steps – Hardwired systems are inflexible • For each step, an arithmetic or logical operation is done » You don’t want to have a computer each applications, like, email, mp3 • For each operation, a different set of control signals is playback, calendar, web ..etc. generated for the hardware – General purpose hardware can do different tasks, given correct control signals » Different state of the hardware. – Instead of re-wiring, supply a new set of control signals to achieve new functionality Comp 212 Computer Org & Arch 9 Z. Li, 2008 Comp 212 Computer Org & Arch 10 Z. Li, 2008 Function of Control Unit Functional Components • For each operation a unique code is provided • CPU: – e.g. ADD, MOVE – The Control Unit and the Arithmetic and Logic Unit constitute the • A hardware segment accepts the code and issues the Central Processing Unit control signals • I/O: – Will have examples in BUS operations – Data and instructions need to get into the system and results out • We have a computer! • Storage of code and results is needed – Main memory for temporary storage – Disk for permanent storage. Comp 212 Computer Org & Arch 11 Z. Li, 2008 Comp 212 Computer Org & Arch 12 Z. Li, 2008 An abstract von Neumann computer • CPU operates on a set of AC registers • Program related: How is the program executed inside a computer ? – PC: program counter – IR: instruction reg • Mem access: – MAR – MBR • I/O: – IAR – IBR Comp 212 Computer Org & Arch 13 Z. Li, 2008 Comp 212 Computer Org & Arch 14 Z. Li, 2008 Instruction and data in computer Instruction Cycle • Two steps: – Fetch: – Execute • Instruction: 16 bit – 4 bit Op code: total 16 possible instructions, » e.g 0001: load mem data at address to AC, 0010: store AC to mem at address – 12 bit address, or operand: » Can access 4096 different addresses in memory Comp 212 Computer Org & Arch 15 Z. Li, 2008 Comp 212 Computer Org & Arch 16 Z. Li, 2008 Fetch Cycle 4 types of instructions • Processor fetches instruction • Data move: CPU <-> Memory from memory location pointed to by PC (Program counter) – Data movement instructions between CPU and Mem • Increment PC: PC=PC+1 – Load mem data into CPU registers • Instruction loaded into – Store CPU register value to Mem Instruction Register (IR) – Expressed as OpCode = LOAD, Oprand= Addr • Processor interprets instruction and performs • Data move: CPU <-> I/O required actions-> go to the exec cycle – Data transfer between CPU and I/O module – OpCode = LOAD, Oprand = I/O port Comp 212 Computer Org & Arch 17 Z. Li, 2008 Comp 212 Computer Org & Arch 18 Z. Li, 2008 4 types of instructions Example Instruction Execution • Data processing • Consider an Addition task – Some arithmetic or logical operation on data, eg. Addition, – Y = [490] + [491] multiplication – Add data in mem location 490 with that of 491 and store the result Y • Control in [491] – Alteration of sequence of operations • Registers used in CPU – e.g. jump – PC : program counter, start at 300, for example • Combination of above – AC: CPU register for addition – IR: instruction reg in CPU – MBR/MAR: mem buffer and addr registers Comp 212 Computer Org & Arch 19 Z. Li, 2008 Comp 212 Computer Org & Arch 20 Z. Li, 2008 Addition Execution -1: Fetch Load Command Addition Execution-2: Exec Load Data • PC=PC+1, PC=301 • Data at [940]=0003 moved to CPU Reg AC – Load MAR 940, execute load mem • Current PC=300 – MBR = 003 • Fetch the instruction at [300] to IR – Load AC from MBR • IR = [1, 940] , • AC = 0003. – opcode=001, LOAD AC, Addr = 940 Comp 212 Computer Org & Arch 21 Z. Li, 2008 Comp 212 Computer Org & Arch 22 Z. Li, 2008 Addition Execution -3: Fetch ADD Command Addition Execution-4: Exec Add • PC=PC+1, PC=302 • Data at [941]=0002 add to CPU Reg AC • AC = 0003+0002=0005. • Current PC=301 • Fetch the instruction at [301] to IR • IR = [5, 941] , – opcode=101, ADD AC from mem address, Addr = 941 Comp 212 Computer Org & Arch 23 Z. Li, 2008 Comp 212 Computer Org & Arch 24 Z. Li, 2008 Addition Execution -5: Fetch Store Command Addition Execution-6: Exec Store AC • Current PC=302 • PC=PC+1, PC=303 • Fetch the instruction at [302] to • Data at AC=0005 store to memory IR location [941]. – • IR = [2, 941] , Set MAR = 941 – Set MBR = AC =0005 – opcode=010, store AC content to – memory with address 941 Execute mem store. Comp 212 Computer Org & Arch 25 Z. Li, 2008 Comp 212 Computer Org & Arch 26 Z. Li, 2008 Summary of Addition Execution Instruction Cycle State Diagram (more detailed) Mem, I/O related • It involves 3 main instructions – Load data from [940] to AC – Add AC with [941] – Store AC to [941] • Total 3 fetches and 3 executions • To move data between CPU and Mem, MBR and MAR are used. CPU insider operations Comp 212 Computer Org & Arch 27 Z. Li, 2008 Comp 212 Computer Org & Arch 28 Z. Li, 2008 Instruction Cycle Details Instruction Cycle Details • IAC (instruction addr calc) • OAC (operand addr calc) – PC=PC+1 – If the operand involves a mem location or • IF (instruction fetch) I/O , compute the address of the operand – Load [PC] to IR • OF (operand fetch) • IAD (instruction operation decoding) – Get the operand from mem or IO – Op code decoding, what to do: e.g – 0001: Load Mem to AC – 0010: Store AC to Mem – 0101: Add AC from Mem – 1101: Read I/O reg IOBR Comp 212 Computer Org & Arch 29 Z. Li, 2008 Comp 212 Computer Org & Arch 30 Z. Li, 2008 Instruction Cycle Details Program Control with a more powerful CPU • von Neumann machine with the following accessible registers and their reg • DO (data operation) address: 0000 0001 – ALU operations on CPU registers – R0, R1, R2, R3: general purpose registers, R0 R1 0010 0011 can load and save to memory directly R2 R3 – AC: addition register, can only move 0100 0101 between general registers, and do addition PC AC • OS (operand store) 0110 0111 – PC: program counter – Write the results in CPU registers back to MAR MBR – MAR: mem addr register mem or I/O devices, which involves another – MBR: mem buf register round of OAC. – IR: not directly accessible. Comp 212 Computer Org & Arch 31 Z. Li, 2008 Comp 212 Computer Org & Arch 32 Z. Li, 2008 Adding an array of data Instruction Set and Machine Code • Compute the summation • Data move between registers of data in [940], [941], …, [949], store it in [940] • Using program loop control for the execution, do not repeat addition 10 times. • How to do it ? – MOVE R1, R2; 0001 0000 0001 0010 – MOVE AC, R1; 0001 0000 0101 0001 – MOVE MAR, 0; 0011 0000 0000 0000 Comp 212 Computer Org & Arch 33 Z. Li, 2008 Comp 212 Computer Org & Arch 34 Z. Li, 2008 Data move between registers and memory ALU and Program Control • Stop the program: MOVE MAR, 540h; 0011 0101 0100 0000 • Jump on AC=0, reset PC to value hhh: LOAD R1; 0101 0000 0000 0001 SAVE R2; 0110 0000 0000 0010 Comp 212 Computer Org & Arch 35 Z.
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