Circuit Design and Applications of the ADM663A/ADM666A Micropower Linear Voltage Regulators by Khy Vijeh, Matt Smith

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Circuit Design and Applications of the ADM663A/ADM666A Micropower Linear Voltage Regulators by Khy Vijeh, Matt Smith AN-392 a APPLICATION NOTE ONE TECHNOLOGY WAY • P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700 Circuit Design and Applications of the ADM663A/ADM666A Micropower Linear Voltage Regulators by Khy Vijeh, Matt Smith GENERAL INFORMATION may be set using a suitable voltage divider connected to The ADM663A/ADM666A contains a micropower band- LBI. When the voltage on LBI falls below 1.3 V, the open gap reference voltage source; an error amplifier, A1; drain output LBO is pulled low. three comparators, C1, C2, C3, and a series pass output transistor. A P-channel FET and an NPN transistor are 22k used on the ADM663A while the ADM666A uses an NPN VIN VOUT2 output transistor. VOUT1 1.3V 0.5V CIRCUIT DESCRIPTION A1 C1 The internal bandgap reference is trimmed to 1.3 V SENSE ± 30 mV. This is used as a reference input to the error amplifier A1. The feedback signal from the regulator out- SHDN D E C2 VIN–50mV put is supplied to the other input by an on-chip voltage C O VSET divider or by two external resistors. When V SET is at D E C3 ground, the internal divider tap between R1 and R2, pro- R vides the error amplifier’s feedback signal giving a +5 V 50mV output. When V SET is at V IN, the internal divider tap be- R1 tween R2 and R3 provides the error amplifier’s feedback R2 A2 VTC signal giving a +3.3 V output. When V SET is at more than 0.9V 50 mV above ground and less than 50 mV below V IN, the R3 ADM663A GND error amplifier’s input is switched directly to the V SET pin, and external resistors are used to set the output voltage. The external resistors are selected so that the Figure 1. ADM663A Functional Block Diagram desired output voltage gives 1.3 V at V SET. V V Comparator C1 monitors the output current via the IN OUT SENSE input. This input, referenced to V OUT(2), monitors 1.3V 0.5V A1 C1 the voltage drop across a load sense resistor. If the volt- SENSE age drop exceeds 0.5 V, then the error amplifier A1 is disabled and the output current is limited. SHDN D E C2 VIN–50mV The ADM663A has an additional amplifier, A2, which C O VSET provides a temperature proportional output, V TC. If this D E is summed into the inverting input of the error amplifier, C3 R a negative temperature coefficient results at the output. 50mV This is useful when powering liquid crystal displays over R1 LBI wide temperature ranges. LBO R2 C4 The ADM666A has an additional comparator, C4, that 1.3V compares the voltage on the low battery input, LBI, pin R3 ADM666A GND to the internal +1.3 V reference. The output from the comparator drives an open drain FET connected to the Figure 2. ADM666A Functional Block Diagram low battery output pin, LBO. The low battery threshold Both the ADM663A and the ADM666A contain a shut- VIN SENSE +1.3V TO +15V +2V TO +16V RCL OUTPUT down (SHDN) input that can be used to disable the error V INPUT OUT2 amplifier and hence the voltage output. The power con- ADM663A sumption in shutdown reduces to less than 9 µA. ADM666A R2 SHDN Circuit Configurations VSET GND For a fixed +5 V output the V SET input is grounded and no R1 external resistors are necessary. This basic configura- tion is shown in Figure 3. For a fixed +3.3 V output, the Figure 5. Adjustable Output VSET input is connected to V IN as shown in Figure 4. Cur- rent limiting is not being utilized so the SENSE input is Table I. Output Voltage Selection connected to V OUT(2). V V +6V TO +16V SET OUT INPUT VIN SENSE +5V GND +5 V OUTPUT V V +3 V 0.1µF OUT2 IN ADM663A 0.1µF R1/R2 ADJ ADM666A Current Limiting VSET GND SHDN Current limiting may be achieved by using an external current sense resistor in series with V OUT(2). When the voltage across the sense resistor exceeds the internal 0.5 V threshold, current limiting is activated. The sense Figure 3. A Fixed +5 V Output resistor is therefore chosen such that the voltage across +4.5V TO +16V it will be 0.5 V when the desired current limit is reached. INPUT VIN SENSE +3.3V OUTPUT 0.5 VOUT2 = 0.1µF RCL ADM663A I 0.1µF CL ADM666A where R CL is the current sense resistor, I CL is the maxi- VSET GND SHDN mum current limit. The value chosen for R CL should also ensure that the cur- rent is limited to less than the 100 mA absolute maxi- Figure 4. A Fixed +3.3 V Output mum rating and also that the power dissipation will also be within the package maximum ratings. Output Voltage Setting If VSET is not connected to GND or to V IN, the output volt- If current limiting is employed, there will be an addi- age is set according to the following equation: tional voltage drop across the external sense resistor that must be considered when determining the regula- (R1+ R2) tors dropout voltage. V =V × OUT SET R1 If current limiting is not used, the SENSE input should where V SET = 1.30 V. be connected to V OUT(2). In this case, input current should be limited so that in case of short circuited output, The resistor values may be selected by first choosing a device power dissipation does not exceed the rated value for R1 and then selecting R2 according to the fol- maximum. lowing equation: Shutdown Input (SHDN) V The SHDN input allows the regulator to be turned off R2 = R1× OUT ±1 with a logic level signal. This will disable the output and 1. 3 0 reduce the current drain to a low quiescent (9 µA maxi- The input leakage current on V SET is 10 nA maximum. mum) current. This is very useful for low power applica- This allows large resistor values to be chosen for R1 and tions. The SHDN input should be driven with a CMOS R2 with little degradation in accuracy. For example, a logic level signal since the input threshold is 0.3 V. In 1 MΩ resistor may be selected for R1, and then R2 may TTL systems, an open collector driver with a pull-up re- be calculated accordingly. The tolerance on V SET is guar- sistor may be used. anteed at less than ±30 mV so in most applications, fixed If the shutdown function is not being used, then it resistors will be suitable. should be connected to GND. –2– Low Supply or Low Battery Detection High Current Operation The ADM666A contains on-chip circuitry for low power The ADM663A contains an additional output, V OUT1, suit- supply or battery detection. If the voltage on the LBI pin able for directly driving the base of an external NPN falls below the internal 1.3 V reference, then the open transistor. Figure 8 shows a configuration which can be drain output LBO will go low. The low threshold voltage used to provide +5 V with boosted current drive. A 1 Ω may be set to any voltage above 1.3 V by appropriate current sensing resistor limits the current at 0.5 A. resistor divider selection. VIN V R3 = R4 BATT ±1 + 10µF VIN 1. 3 V VOUT1 2N4237 V where R3 and R4 are the resistive divider resistors and OUT2 100Ω ADM663A 1.0Ω VBATT is the desired low voltage threshold. SHDN + SENSE +5V, 0.5A Since the LBI input leakage current is less than 10 nA, 10µF SHUTDOWN VSET GND OUTPUT large values may be selected for R3 and R4 in order to minimize loading. For example, a 6 V low threshold may be set using 10 M Ω for R3 and 2.7 M Ω for R4. Figure 8. ADM663A Boosted Output Current (0.5 A) +2V TO +16V INPUT Temperature Proportional Output VIN SENSE +1.3V TO +15V RCL OUTPUT The ADM663A contains a V TC output with a positive tem- R3 VOUT perature coefficient of +2.5 mV/ °C typ. This may be con- ADM666A R2 LBI nected to the summing junction of the error amplifier VSET R4 (VSET) through a resistor resulting in a negative tempera- SHDN LBO R1 LOW GND ture coefficient at the output of the regulator. This is BATTERY OUTPUT especially useful in multiplexed LCD displays to com- pensate for the inherent negative temperature coeffi- cient of the LCD threshold. At +25 °C, the voltage at the Figure 6. ADM666A Adjustable Output with Low VTC output is typically 0.9 V. The equations for setting Battery Detection both the output voltage and the tempco are given be- Low Output Detection low. If this function is not being used, then V TC should be The circuit in Figure 7 will generate a low LBO when out- left unconnected. put voltage drops below a preset value determined by R2 R2 the following equations: V =V 1+ + (V ±V ) OUT SET R1 R3 SET TC VOUT R2 + R3 = R1 ±1 = ±R2 1. 3 TCVOUT (TCVTC ) R3 V R3=(R1+R2) OL ±1 where V = +1.3 V, V = +0.9 V, TCV = +2.5 mV/ °C 1. 3 SET TC TC SENSE for VOUT = 5.0 V nominal, V OL = 3% of V OUT = 4.85 V and R1 V = 1 MΩ solving the equations simultaneously we will get VOUT2 OUT R2 R2 = 31 k Ω and R3 = 2.82 M Ω.
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