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Sequential Logic Sequential Logic References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall © UCB Principles of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian, Addison Wesley Clocked Systems: Finite State Machines Inputs Outputs Combinational Out = f(In, State) Logic Current state bits Next state bits Q D Clock or clocks Registers Registers serve as storage element to store past history Clocked Systems: Pipelined Systems Inputs Outputs D Q D Q D Q Logic Logic Registers Clock Registers serve as storage element to capture the output of each processing stage Storage Mechanisms • Positive feedback – Connect one or more output signals back to the input – Regenerative, signal can be held indefinitely, static • Charge-based – Use charge storage to store signal value – Need refreshing to overcome charge leakage, dynamic Positive Feedback: Two Cascaded Inverters Vi1 Vo1= Vi2 Vo2 Vi2= Vo1 Bi-Stability and Meta-Stability o1 o1 A A =V =V i2 i2 V V C C B B δ Vi1=Vo2 δ Vi1=Vo2 Gain larger than 1 amplifies Gain less than 1 reduces the deviation from C the deviation from A SR-Flip Flop • NOR-based SR flip-flop, positive logic Schematic Logic Symbol Characteristic table • NAND-based SR flip-flop, negative logic Forbidden state Schematic Logic Symbol Characteristic table JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input φ to synchronize changes in the output logic states of flip-flops • Forbidden state is eliminated, • But repeated toggling when J = K = 1, need to keep clock pulse small < propagation delay of FF Other Flip-Flops Toggle or T flip-flop Delay or D flip-flop Race Problem • A flip-flop is a latch if the gate is transparent while the clock is high (low) • Signal can raise around when φ is high • Solutions: – Reduce the pulse width of φ – Master-slave and edge-triggered FFs Master-Slave Flip-Flop • Either master or slave FF is in the hold mode • Pulse lengths of clock must be longer than propagation delay of latches • Asynchronous or synchronous inputs to initialize the flip-flop states One-Catching or Level-Sensitive QM QS Propagation Delay Based Edge-Triggered • Depend only on the value of In just before the clock transition Edge Triggered Flip-Flop Flip-Flop: Timing Definitions Maximum Clock Frequency t pFF + t p,comb + tsetup < T CMOS Clocked SR Flip-Flop VDD S M2 M4 Q Q Q Q φ M6 M8 φ M1 M3 R S M5 M7 R φ Transistor Sizing of SR Flip-Flop • Assume transistors of inverters are sized so that VM is VDD/2, mobility ratio µn/µp = 3 –(W/L)M1 = (W/L)M3 = 1.8/1.2 –(W/L)M2 = (W/L)M4 = 5.4/1.2 • To bring Q from 1 to 0, need to properly ratio the sizes of pseudo-NMOS inverter (M7-M8)-M4 –VOL must be lower than VDD/2 ⎛ V V 2 ⎞ ⎛ V V 2 ⎞ ⎜ DD DD ⎟ ⎜ DD DD ⎟ kn,M 78 ⎜()VDD −Vtn − ⎟ = k p,M 4 ⎜()VDD − |Vtp | − ⎟ ⎝ 2 8 ⎠ ⎝ 2 8 ⎠ µ p (W / L)M 78 ≥ (W / L)M 4 = (W / L)M 3 µn (W / L)M 7 = 2(W / L)M 78 ≥ 2(W / L)M 3 = (3.6 /1.2) Flip-Flop: Transistor Sizing Propagation Delay Pseudo- NMOS Inverter inverter M3-M4 (M5-M6)-M2 Complementary CMOS SR Flip-Flop VDD S φ M10 M12 φ R M9 M11 M2 M4 Q Q φ M6 M8 φ M1 M3 S M5 M7 R Eliminates pseudo-NMOS inverters ⇒ Faster switching and smaller transient current 6-Transistor SR Flip-Flop VDD M2 M4 φ φ Q Q S R M1 M3 CMOS D Flip-Flop VDD D Q Q Q Q φ φ φ D D Master-Slave D Flip-Flop φ VDD Q Q D D Negative-Level Sensitive D Flip-Flop VDD D D D Q φ φ Q Q Q φ Master-Slave D Flip-Flop φ VDD φ Q Q D D CVSL-Style Master-Slave D-FF VDD VDD Q Q φ D Charge-Based Storage D φ φ In D φ φ Pseudo-static Latch Layout of a D Flip-Flop Q φ In In Q φ Q φ φ φ φ Q Master-Slave Flip-Flop D φ φ A In B φ φ φ • Overlapping clocks can cause – race conditions – undefined signals φ 2 Phase Non-Overlapping Clocks D φ1 φ2 A In φ1 φ2 φ1 t p12 φ2 Asynchronous Setting D φ1 φ2 A In -Set φ1 φ2 2-phase Dynamic Flip-Flop φ1 φ2 A In D Input Output sampled Enabled φ1 φ2 Flip-flop Insensitive to Clock Overlap VDD VDD M2 M6 φ M4 φ M8 X D In C φ M3 CL1 φ M7 L2 M1 M5 φ-section φ-section C2MOS Latch or Clocked CMOS Latch C2MOS Latch Avoids Race Conditions VDD VDD M2 M6 X D In C 11M3 CL1 M7 L2 M1 M5 • Cascaded inverters: needs one pull-up followed by one pull-down, or vice versa to propagate signal • (1-1) overlap: Only the pull-down networks are active, input signal cannot propagate to the output • (0-0) overlap: only the pull-up networks are active C2MOS Latch Avoids Race Conditions •C2MOS latch is insensitive to overlap, as long a the rise and fall times of clock edges are sufficiently small Clocked CMOS Logic • Replace the inverter in a C2MOS latch with a complementary CMOS logic VDD VDD PUN PUN In1-3 φ M4 φ M8 X φ M3 CL1 φ M7 CL2 PDN PDN In1-3 • Divide the computation into stages: Pipelining Pipelining a Non-pipelineda Pipelined REG REG φ ⋅ log φ ⋅ log REG REG REG REG b φ b φ φ φ REG REG φ φ Tmin = t p,reg + t p,logic + tsetup,reg Tmin, pipe = t p,reg + max(t p,adder ,t p,abs ,t p,log ) + tsetup,reg Pipelined Logic using C2MOS VDD VDD VDD φ φ φ out In F G φ φ φ C1 C2 C3 NORA CMOS (NO-RAce logic) Race free as long as all the logic functions F and G between the latches are non-inverting Example VDD VDD VDD φ φ In φ φ Number of static inversion should be even NORA CMOS φ-module Logic Latch φ = 0 Precharge Hold φ = 1 Evaluate Evaluate NORA CMOS φ-module Logic Latch φ = 0 Evaluate Evaluate φ = 1 Precharge Hold NORA Logic • NORA data path consists of a chain of alternating φ and φ modules • Dynamic-logic rule: single 0 → 1 (1 → 0) transition for dynamic φn-block (φp-block) •C2MOS rule: – If dynamic blocks are present, even number of static inversions between a latch and a dynamic block – Otherwise, even number of static inversions between latches • Static logic may glitch, best to keep all of them after dynamic blocks Doubled C2MOS Latches Doubled n-C2MOS latch Doubled p-C2MOS latch TSPC - True Single Phase Clock Logic Including logic into Inserting logic between the latch the latches Simplified TSPC Latches A and A’ do not have full logic swing Master-Slave Flip-flops Positive-edge triggered D-FF Negative-edge triggered D-FF Master-Slave Simplified TSPC Flip-Flops • Positive edge-triggered D flip-flops • Reduces clock load Further Simplication Schmitt Trigger • VTC with hysteresis • Restores signal slopes Noise Suppression using Schmitt Trigger Sharp low-to-high transition CMOS Schmitt Trigger Moves switching threshold of first inverter Sizing of M3 and M4 •VM+ = 3.5V – M1 and M2 are in saturation; M4 is in triode region k 2 1 ()V −V = 2 M + tn 2 k 2 ⎛ ()V −V ⎞ 2 V −V − |V | + k ⎜ V − |V | V −V − DD M + ⎟ ()()DD M + tp 4 ⎜ DD tp ()DD M + ⎟ 2 ⎝ 2 ⎠ •VM- = 1.5V – M1 and M2 are in saturation; M3 is in triode region Schmitt Trigger: Simulated VTC CMOS Schmitt Trigger • In = 0, at steady state, VOut = VDD, VX = VDD -Vtn • In makes a 0→1 transition – Saturated load inverter M1-M5 discharges X – M2 inactive until VX = Vin -Vtn –UseVin to approximate VM- – M1-M5 in saturation k 2 k 2 1 ()V −V = 5 ()V −V 2 M − tn 2 DD M − Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator Transition-Triggered Monostable In DELAY Out t d td Detects changes in the input signal produces a pulse to initialize subsequent circuitry e.g., address transition detection in static memories Monostable Trigger (RC-based) Astable Multivibrators (Oscillators) T = 2 × tp × N Voltage Controller Oscillator (VCO) Schmitt trigger restores signal slopes Current starved inverter Decrease Vcontr to reduce discharge current ⇒ increase propagation delay of inverter ⇒ decreases oscillating frequency (quadratic dependency) Relaxation Oscillator T = 2 × (ln 3) × RC.
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