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JFET, MESFET, Hemts School of Electronics & 1 Other Useful FETs… Computing Systems 6.2, 5.8, 6.3 – JFET, MESFET, HEMTs Image for this lecture… a tool used by device designers… Silvaco ATLAS/BLAZE. Numerical analysis, solve using a mesh of points to implement equations, and crunches the numbers over and over again to refine the final data-set. 2D or 3D. Can take days to complete one simulation! SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 2 JFETs Computing Systems ! Consider this 3 terminal device… ! Note the gate (G) electrodes are equivalent (shorted together) ! Apply VD between drain (D) and source (S) and we get current flow … ‘source’ & ‘drain’ for electrons ! Apply negative voltage to G’s… What happens that might be useful for a transistor? Why the doping levels? SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 3 JFETs Computing Systems ! Apply negative voltage to G’s… ! Depletion regions expand, and can block the entire n-channel such that current flow is prohibited! How much current did it take to reverse bias the PN junctions? ! Amplification using a Junction Field Effect Transistor (JFET)! SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 4 JFETs Computing Systems ! We typically only need to focus on the channel region… ! What kind of current do we get? What carriers? I-V looks like what? ! However, a resistor behavior for the I-V is only valid for very low current levels… ! So what happens at higher current levels? Take a guess… hint, a resistor has a voltage drop across it… SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 5 JFETs Computing Systems Note: shape of depletion is because VD drop across resistive n-layer! Further increase VD , could V here ever be zero? ~ linear saturating saturated ! At higher current levels we can get Pinch-off (for Vg=Vs=0). Increase drain voltage VD, the VDS increases which should increase current flow. However, increasing VD reverse biases the PN junctions and ‘pinches-off’ the channel (causes current saturation). Depletion width tapered due to voltage drop… SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 6 JFETs Computing Systems ! We can bias VG and modulate the n- channel conductivity (depletion) ! Therefore we have created a transistor… ! Note, if we operated in saturation, small changes in VG will cause large changes in ID. And IG is small! ! Reverse dopings, how would Vg change? ! Check out this great simulation… try it out! Use the link or Google ‘JFET CAM UK’ http://www-g.eng.cam.ac.uk/mmg/ teaching/linearcircuits/jfet.html SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 7 JFETs Computing Systems ! Recall depletion region thickness for a pn junction. kT N A N D V0 = ln 2 ⎛ ⎞⎛ ⎞ q ni 2εkT NA ND 1 1 W = 2 ⎜ ln 2 ⎟⎜ + ⎟ q ⎝ ni ⎠⎝ NA ND ⎠ 2εV ⎛ 1 1 ⎞ W = 0 ⎜ + ⎟ q ⎝ NA ND ⎠ ! At a reverse bias V… 2ε(V −V )⎛ 1 1 ⎞ W = 0 ⎜ + ⎟ q ⎝ NA ND ⎠ ! The junction is p+ so NA>>ND, we can use this and V <<V to 0 GD Introduce Vp (W=a) and solve for it… approximate W as… −VGD (pinchoff ) = VP 2 2ε(−VGD ) …at pinch off W ≈ qa ND Why dep. qN W=a Vp = D 2ε on Nd only? SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 8 JFETs Computing Systems ! Recall effect of resistivity (ρ): ρ(Ω − cm)L ρL R = = A wt ! For the system at right substitute new values for L->dx and t->2h(x) to obtain the differential resistance: ρ dx R = Z 2h(x) ! Therefore current is (a Vx differential equation, 1st order, easiest to solve!): Z 2h(x) dV I = V /R = x D ρ dx ‘gradual channel approximation’, no abrupt change in h(x) with dx SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 9 JFETs Computing Systems ! We already know that: qa2N V = D V = V −V p 2ε Gx G x 2ε(−V ) W (x) ≈ Gx qN D ! The half width of the channel h(x) h(x) = a −W (x) Vx using above terms we can show that… ⎡ Vx −VG ⎤ h(x) = a ⎢1− ⎥ ⎣ VP ⎦ SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 10 JFETs Computing Systems ⎡ Vx −VG ⎤ ! Substitute: h(x) = a ⎢1− ⎥ ⎣ VP ⎦ Z 2h(x) dV ! Into: I = V /R = x D ρ dx ! Leads to: 2Za ⎡ V −V ⎤ I dx = 1− x G dV D ⎢ ⎥ x ρ ⎣ VP ⎦ Vx integrate both sides (but over what limits?) 3 3 2Za ⎡V 2 ⎛ V ⎞ 2 2 ⎛ V −V ⎞ 2 ⎤ ⎢ D G D G ⎥ ID L = VP + ⎜ − ⎟ − ⎜ ⎟ 2aZ conductance ρ ⎢VP 3 ⎝ VP ⎠ 3 ⎝ VP ⎠ ⎥ G = ⎣ ⎦ 0 ρL for the channel (mho’s) 3 3 for low ⎡ ⎛ ⎞ 2 ⎛ ⎞ 2⎤ ⎢V D 2 VG 2 VD −VG ⎥ current ID = G0VP + ⎜ − ⎟ − ⎜ ⎟ ⎢ V 3 V 3 V ⎥ levels ⎣ P ⎝ P ⎠ ⎝ P ⎠ ⎦ SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 11 JFETs Computing Systems ! Keep increasing Vd, at higher current levels we run into pinch-off and this term goes to unity (why?) VD − VG = VP 3 3 ⎡ ⎛ ⎞ 2 ⎛ ⎞ 2⎤ ⎢V D 2 VG 2 VD −VG ⎥ ID = G0VP + ⎜ − ⎟ − ⎜ ⎟ ⎢ V 3 V 3 V ⎥ ⎣ P ⎝ P ⎠ ⎝ P ⎠ ⎦ 3 ⎡ ⎛ ⎞ 2 ⎤ ⎢V D 2 VG 2⎥ ID (sat.) = G0VP + ⎜ − ⎟ − ⎢ V 3 V 3⎥ ⎣ P ⎝ P ⎠ ⎦ VD VG VP = VD −VG ⇒ =1+ So why for Id(sat.) is there no VD term? VP VP 3 Lets get rid of Vd…. first divide both ⎡ ⎛ ⎞ 2 ⎤ ⎢V G 2 VG 1⎥ sides by Vp and reorder. ID (sat.) = G0VP − ⎜ ⎟ + ⎢V 3 V 3⎥ ⎣ P ⎝ P ⎠ ⎦ SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 12 JFETs Computing Systems ! We can represent the device in the saturation region with an equivalent circuit: channel conductance 3 ⎡ ⎛ ⎞ 2 ⎤ ⎢V G 2 VG 1⎥ 2aZ ID (sat.) = G0VP − ⎜ ⎟ + G = ⎢V 3 V 3⎥ 0 ⎣ P ⎝ P ⎠ ⎦ ρL ⎡ 1/ 2⎤ ∂I (sat.) ⎛ −V ⎞ g (sat.) = D = G ⎢1 − G ⎥ ,(V < 0) m 0 ⎜ ⎟ G ∂VG ⎣⎢ ⎝ VP ⎠ ⎦⎥ ! gm has units of A/V (S or mhos). But it is more than just conductance, it transfers an input voltage to an output current… Transconductance! gm ! JFET F.O.M. is g /Z ! If you pick an apple from a tree, and find it has m transconductance, you could represent it this way! large amplification or switching (It doesn’t though, FYI… : ) with min device area… SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 13 JFETs Computing Systems ! Lastly, It can be shown experimentally that: ⎛ ⎞ 2 VG ID (sat.) ≅ IDSS ⎜1 + ⎟ (VG < 0) ⎝ VP ⎠ ! Where IDSS is the saturated drain current with V =0 G 2aZ I 1 G V V DSS = 3 0 P = P 3ρ L SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 14 JFETs Computing Systems JFETs used when need high current output with very low current input at gate (some BJT’s have too much input current, some MOSFET not enough output current). ∂I D (sat.) (1.8 − 0.3)mA gm (sat.) = = ∂VG 0.3V -3 easy to calculate gm ~5x10 mhos SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 15 JFETs Computing Systems SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 16 Wow! >50! Vertical JFET? Computing Systems SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 17 Review! Computing Systems ! Warmup, why is this called an operational transconductance amplifier? ! Do I need positive or negative gate voltage to turn off the JFET? ! If we keep increasing JFET drain voltage, what happens? Does the current keep increasing more and more, if not, what is this called? There are two terms describing this, one term is for the voltage at which this occurs, and the other term describes the current. ! Why is the JFET gate heavily doped? Hint, thing of the direction you want depletion to go… ! Why is a key advantage of using a JFET? Hint, the best amplifiers have very high input impedance (don’t require alot of input voltage or current). (a) zero input current, and high output current; (b) very small input current, and high output current; (c) large input current, and low output current; (d) small input current, and small output current; SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 18 Switch Gears… Don’t need PN! Computing Systems ! Remember, metal has a such a high density of electrons that it acts like n++. Metal W s/c qΦs qχ qΦm qV0 = q(Φm − Φs) q(Φm − χ) = qΦB …remember semiconductor side looks just like 1/2 of a PN junction SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 19 Key is Depletions Width… Computing Systems ! N-type Schottky Diode with Φ > Φ m s V I V q(V0 −V) q(Φm − χ) = qΦB V qV Metal W s/c Vr q(Φm − χ) = qΦB q(V0 + Vr ) qV0 = q(Φm − Φs) q(Φm − χ) = qΦB SECS 2077 – Semiconductor Devices © Instructor – Prof. Jason Heikenfeld School of Electronics & 20 Key is Depletions Width… Computing Systems ! MESFET Au-Ge : ohmic -only metal contacts Al : Schottky ! Depletion modulation using a Schottky Diode ! n-GaAs epitaxy grown on insulating GaAs subs. ! Etched to isolate devices (C, and J leakage!) ! Only need for high resolution patterning is the metal electrodes… ! So why make a GaAs MESFET instead of a Si MOSFET or JFET? Looking for 3 answers… (1) wider Eg (1.12!1.43 eV) for higher current (2) higher e mobility (1350!8500 cm2/V-s) (3) small features (only pattern metal!) ….
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