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United States Patent and Trademark Office Before UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD ARM LTD. and ARM, INC., Petitioners, v. COMPLEX MEMORY, LLC, Patent Owner IPR2019-00053 PATENT 5,890,195 PATENT OWNER PRELIMINARY RESPONSE TO PETITION PURSUANT TO 37 C.F.R. § 42.107(a) IPR2019-00053 U.S. Patent 5,890,195 Table of Contents I. INTRODUCTION 1 II. THE ’195 PATENT 1 A. Overview of the ’195 Patent 1 B. Prosecution History of the ’195 Patent 4 C. Claim Construction for the ’195 Patent 4 III. THERE IS NO REASONABLE LIKELIHOOD THAT AT LEAST ONE OF THE CHALLENGED CLAIMS IS UNPATENTABLE 5 A. GROUND 1 - Fukuda and Lin 5 1. Brief Overview of Fukuda 5 2. Brief Overview of Lin 6 3. Analysis of Claim 6 8 a. The combination of Fukuda and Lin fails to render obvious storing addresses in latches (a first storage type) for address lookup and storing data in registers (a second storage type) 8 b. Petitioners’ Assertions Regarding “Latches” and “Registers” are Technically and Legally Flawed 16 4. Ground 1 fails 20 B. GROUND 2 – Fukuda, Lin, and Matsuda 20 C. GROUND 3 – Smith and Horowitz 21 1. Brief Overview of Smith 21 2. Brief Overview of Horowitz 22 3. Analysis of Claim 6 22 a. The combination of Smith and Horowitz fails to render obvious storing addresses in latches (a first storage type) for address lookup and storing data in registers (a second storage type) 22 4. Ground 3 fails 24 D. GROUND 4 – Smith, Horowitz, and Matsuda 25 IV. PETITIONERS FAIL TO IDENTIFY ALL REAL PARTIES-IN- INTEREST 25 ii IPR2019-00053 U.S. Patent 5,890,195 V. CONCLUSION 29 Table of Exhibits Exhibits to Petition U.S. Patent No. 5,890,195 (“the ‘195 patent”) Ex. 1001 File History for the ’195 patent Ex. 1002 Declaration of Michael Shamos Ex. 1003 Curriculum Vitae of Michael Shamos Ex. 1004 U.S. Patent No. 5,619,676 to Fukuda et al. Ex. 1005 (“Fukuda”) Alan Smith, Cache Memories, Computing Surveys, Ex. 1006 Vol. 14, No. 3, pp. 473-530 (Sep. 1982) (“Smith”) U.S. Patent No. 5,423,019 to Lin et al. (“Lin”) Ex. 1007 Excerpt (pp. 523-24, 542, 677) from: Paul Horowitz Ex. 1008 and Winfield Hill, The Art of Electronics, Second Edition, Cambridge University Press (1989) (“Horowitz”) U.S. Patent No. 5,257,220 to Shin et al. (“Shin”) Ex. 1009 U.S. Patent No. 5,509,132 to Matsuda et al. Ex. 1010 (“Matsuda”) 4004 Single Chip 4-bit P-Channel Microprocessor, Ex. 1011 Intel Corporation, March 1987 (“4004 Datasheet”) Texas Instruments Inc. v. Complex Memory LLC, Ex. 1012 IPR2018-00823, EX1012: Exhibit A of Plaintiff Complex Memory LLC’s Infringement Contentions pursuant to L.R. 3-1 for Complex Memory, LLC v. Texas Instruments, Inc. et al., Case No. 2:17-cv-699 (“Infringement Contentions”) Texas Instruments Inc. v. Complex Memory LLC, Ex. 1013 IPR2018-00823, EX1013: Complaint for Patent Infringement for Complex Memory, LLC v. Texas Instruments, Inc. et al., Case No. 2:17-cv-699 (“Complaint”) Merriam-Webster Collegiate Dictionary, 10th Ed., Ex. 1014 Merriam-Webster, Incorporated, 1993, p. 404 (“Merriam-Webster Dictionary”) iii IPR2019-00053 U.S. Patent 5,890,195 CLIPPER 32-Bit Microprocessor: Introduction to the Ex. 1015 CLIPPER Architecture, Fairchild (Mar. 1986) (“CLIPPER”) Declaration of Rachel J. Watters regarding Smith Ex. 1016 (“Watters”) Declaration of Dr. Sylvia Hall-Ellis regarding Ex. 1017 Horowitz (“Hall-Ellis”) Texas Instruments Inc. v. Complex Memory LLC, Ex. 1018 IPR2018-00823, Paper No. 12 (PTAB Aug. 3, 2018) Exhibits for POPR Declaration of Steve Novak Ex. 2001 Appendix A: Curriculum Vitae of Steve Novak Ex. 2002 ARM Governance and Financial Report 2015, Ex. 2003 retrieved on February 5, 2019 from https://www.arm.com/company/investors/- /media/arm- com/company/Legacy%20Financial%20PDFs/ARM GFReport2015.pdf?la=en “STM32 32-bit Arm Cortex MCUs,” retrieved on Ex. 2004 February 5, 2019 from www.st.com/en/microcontrollers/stm32-32-bit-arm- cortex-mcus.html “ARM and Broadcom Extend Relationship With Ex. 2005 ARMv7 and ARMv8 Architecture Licenses,” retrieved on February 5, 2019 from www.arm.com/about/newsroom/arm-and-broadcom- extend-relationship-with-armv7-and-armv8- architecture-licenses.php “Motorola’s new X8 ARM chip: The cornerstone of Ex. 2006 Google’s always-on Android vision,” retrieved on February 5, 2019 from www.extremetech.com/computing/162139- motorolas-new-x8-arm-chip-the-cornerstone-of- googles-always-on-android-vision Complaint from Complex Memory, LLC v. Texas Ex. 2007 Instruments, Inc. et al., Case No. 2:17-cv-00699 (E.D.Tex. October 13, 2017) iv IPR2019-00053 U.S. Patent 5,890,195 I. INTRODUCTION Patent Owner (“PO”) Complex Memory, LLC submits this Preliminary Response to the Petition for Inter Partes Review (“’195 Pet.”) filed by Petitioners ARM LTD. and ARM, INC. Petitioners challenge Claims 6, 7, and 8. Claim 6 is in independent format, and claims 7 and 8 each depend from claim 6. The Board should dismiss the Petition in its entirety at least because, as PO shows below, (1) a dispositive claim element is entirely missing from the combination asserted in each of the Grounds of the Petition, and (2) Petitioners have failed to name at least one real party-in-interest. II. THE ’195 PATENT A. Overview of the ’195 Patent U.S. Patent No. 5,890,195 (“the ‘195 Patent”) is titled “DRAM with Integral SRAM Comprising a Plurality of Sets of Address Latches Each Associated with One of a Plurality of SRAM.” The ’195 Patent issued March 30, 1999 from United States Patent Application No. 08/855,944 and is a continuation-in-part of United States Patent No. 5,835,932, filed March 13, 1997. Petitioners challenge Claims 6, 7, and 8. Claim 6 is in independent format. Claim 6, annotated as referred to herein, reads: 6. [Preamble] A method of accessing blocks of data in a 1 IPR2019-00053 U.S. Patent 5,890,195 memory having a plurality registers and a memory array, comprising the steps of: [6a] receiving an address through an address port; [6b] comparing the received address with addresses previously stored in each of a plurality of latches; [6c] when a match occurs between the received address and a matching address stored in a one of the latches performing the substep of accessing a register corresponding to the latches storing the matching address through a data port; [6d and 6e] when a match does not occur between the received address and an address stored in one of the latches, performing the substeps of: exchanging data between a location in the memory array addressed by the received address and a selected one of the registers; and storing the received address in one of the latches corresponding to the selected register; [6f] modifying the received address to generate a modified address; [6g] exchanging data between a location in the memory array addressed by the modified address and a second selected one of the registers; and [6h] storing the modified address in of one of the latches corresponding to the second selected register. ʼ195 Patent at 19:8-33. The ’195 Patent describes a system that includes registers, to store data that was previously read from a memory (e.g., a DRAM cell array 402). ‘195 Patent at 3:57-4:4, 8:51-55, 9:26-36, 10:10-12, and 11:66-12:22. The registers provide 2 IPR2019-00053 U.S. Patent 5,890,195 faster access to cached data as compared to retrieving the data from the memory. ‘195 Patent at 3:57-4:4. When data is read from the memory, the data is stored in the registers, and the address of the data is stored in address latches (e.g., last row read (LRR) latches 502 or LRR latches 701) that are associated with the particular registers that store the data. In addition to reading the requested data and storing the data (in the registers) and storing the address of the data (in the latches), the system also caches non-requested data from the memory. ‘195 Patent at 10:54-11:18. In an example, the system modifies the address of the requested data and uses the modified address to access the memory. Id. The non-requested data read from the memory is stored into the registers. Id. The modified address is stored in latches associated with the non-requested data. Id. When a subsequent request for data is received, the address of the newly requested data is compared to the addresses in the latches. An address match indicates that the newly requested data is currently stored in the registers and can be accessed with reduced latency from the registers as compared to the memory. Because data is typically accessed within temporally or spatially adjacent areas in the memory, there is a substantial probability that an address match will occur. ‘195 Patent at 11:31-43. 3 IPR2019-00053 U.S. Patent 5,890,195 B. Prosecution History of the ’195 Patent United States Patent Application No. 08/855,944 (“the ’944 Application”) eventually issued as the ’195 Patent and was filed on May 14, 1997 as a continuation-in-part of United States Patent No. 5,835,932 filed March 13, 1997. The ’944 Application received a first action notice of allowance on December 3, 1998 without any rejections based on prior art. C. Claim Construction for the ’195 Patent Petitioners state that the challenged claims of the ’195 Patent should be interpreted under the Philips standard.
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