UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

ARM LTD. and ARM, INC., Petitioners,

v.

COMPLEX MEMORY, LLC, Patent Owner

IPR2019-00053 PATENT 5,890,195

PATENT OWNER PRELIMINARY RESPONSE TO PETITION PURSUANT TO 37 C.F.R. § 42.107(a)

IPR2019-00053 U.S. Patent 5,890,195 Table of Contents I. INTRODUCTION 1 II. THE ’195 PATENT 1 A. Overview of the ’195 Patent 1 B. Prosecution History of the ’195 Patent 4 C. Claim Construction for the ’195 Patent 4 III. THERE IS NO REASONABLE LIKELIHOOD THAT AT LEAST ONE OF THE CHALLENGED CLAIMS IS UNPATENTABLE 5 A. GROUND 1 - Fukuda and Lin 5 1. Brief Overview of Fukuda 5 2. Brief Overview of Lin 6 3. Analysis of Claim 6 8 a. The combination of Fukuda and Lin fails to render obvious storing addresses in latches (a first storage type) for address lookup and storing data in registers (a second storage type) 8 b. Petitioners’ Assertions Regarding “Latches” and “Registers” are Technically and Legally Flawed 16 4. Ground 1 fails 20 B. GROUND 2 – Fukuda, Lin, and Matsuda 20 C. GROUND 3 – Smith and Horowitz 21 1. Brief Overview of Smith 21 2. Brief Overview of Horowitz 22 3. Analysis of Claim 6 22 a. The combination of Smith and Horowitz fails to render obvious storing addresses in latches (a first storage type) for address lookup and storing data in registers (a second storage type) 22 4. Ground 3 fails 24 D. GROUND 4 – Smith, Horowitz, and Matsuda 25 IV. PETITIONERS FAIL TO IDENTIFY ALL REAL PARTIES-IN- INTEREST 25

ii IPR2019-00053 U.S. Patent 5,890,195 V. CONCLUSION 29

Table of Exhibits Exhibits to Petition U.S. Patent No. 5,890,195 (“the ‘195 patent”) Ex. 1001 File History for the ’195 patent Ex. 1002 Declaration of Michael Shamos Ex. 1003 Curriculum Vitae of Michael Shamos Ex. 1004 U.S. Patent No. 5,619,676 to Fukuda et al. Ex. 1005 (“Fukuda”) Alan Smith, Memories, Computing Surveys, Ex. 1006 Vol. 14, No. 3, pp. 473-530 (Sep. 1982) (“Smith”) U.S. Patent No. 5,423,019 to Lin et al. (“Lin”) Ex. 1007 Excerpt (pp. 523-24, 542, 677) from: Paul Horowitz Ex. 1008 and Winfield Hill, The Art of Electronics, Second Edition, Cambridge University Press (1989) (“Horowitz”) U.S. Patent No. 5,257,220 to Shin et al. (“Shin”) Ex. 1009 U.S. Patent No. 5,509,132 to Matsuda et al. Ex. 1010 (“Matsuda”) 4004 Single Chip 4-bit P-Channel , Ex. 1011 Corporation, March 1987 (“4004 Datasheet”) Texas Instruments Inc. v. Complex Memory LLC, Ex. 1012 IPR2018-00823, EX1012: Exhibit A of Plaintiff Complex Memory LLC’s Infringement Contentions pursuant to L.R. 3-1 for Complex Memory, LLC v. Texas Instruments, Inc. et al., Case No. 2:17-cv-699 (“Infringement Contentions”) Texas Instruments Inc. v. Complex Memory LLC, Ex. 1013 IPR2018-00823, EX1013: Complaint for Patent Infringement for Complex Memory, LLC v. Texas Instruments, Inc. et al., Case No. 2:17-cv-699 (“Complaint”) Merriam-Webster Collegiate Dictionary, 10th Ed., Ex. 1014 Merriam-Webster, Incorporated, 1993, p. 404 (“Merriam-Webster Dictionary”)

iii IPR2019-00053 U.S. Patent 5,890,195 CLIPPER 32-Bit Microprocessor: Introduction to the Ex. 1015 CLIPPER Architecture, Fairchild (Mar. 1986) (“CLIPPER”) Declaration of Rachel J. Watters regarding Smith Ex. 1016 (“Watters”) Declaration of Dr. Sylvia Hall-Ellis regarding Ex. 1017 Horowitz (“Hall-Ellis”) Texas Instruments Inc. v. Complex Memory LLC, Ex. 1018 IPR2018-00823, Paper No. 12 (PTAB Aug. 3, 2018)

Exhibits for POPR Declaration of Steve Novak Ex. 2001 Appendix A: Curriculum Vitae of Steve Novak Ex. 2002 ARM Governance and Financial Report 2015, Ex. 2003 retrieved on February 5, 2019 from https://www.arm.com/company/investors/- /media/arm- com/company/Legacy%20Financial%20PDFs/ARM GFReport2015.pdf?la=en “STM32 32-bit Arm Cortex MCUs,” retrieved on Ex. 2004 February 5, 2019 from www.st.com/en/microcontrollers/stm32-32-bit-arm- cortex-mcus.html “ARM and Broadcom Extend Relationship With Ex. 2005 ARMv7 and ARMv8 Architecture Licenses,” retrieved on February 5, 2019 from www.arm.com/about/newsroom/arm-and-broadcom- extend-relationship-with-armv7-and-armv8- architecture-licenses.php “Motorola’s new X8 ARM chip: The cornerstone of Ex. 2006 Google’s always-on Android vision,” retrieved on February 5, 2019 from www.extremetech.com/computing/162139- motorolas-new-x8-arm-chip-the-cornerstone-of- googles-always-on-android-vision Complaint from Complex Memory, LLC v. Texas Ex. 2007 Instruments, Inc. et al., Case No. 2:17-cv-00699 (E.D.Tex. October 13, 2017)

iv IPR2019-00053 U.S. Patent 5,890,195

I. INTRODUCTION

Patent Owner (“PO”) Complex Memory, LLC submits this Preliminary

Response to the Petition for Inter Partes Review (“’195 Pet.”) filed by Petitioners

ARM LTD. and ARM, INC. Petitioners challenge Claims 6, 7, and 8. Claim 6 is in independent format, and claims 7 and 8 each depend from claim 6.

The Board should dismiss the Petition in its entirety at least because, as PO shows below, (1) a dispositive claim element is entirely missing from the combination asserted in each of the Grounds of the Petition, and (2) Petitioners have failed to name at least one real party-in-interest.

II. THE ’195 PATENT A. Overview of the ’195 Patent

U.S. Patent No. 5,890,195 (“the ‘195 Patent”) is titled “DRAM with Integral

SRAM Comprising a Plurality of Sets of Address Latches Each Associated with One of a Plurality of SRAM.” The ’195 Patent issued March 30, 1999 from United States

Patent Application No. 08/855,944 and is a continuation-in-part of United States

Patent No. 5,835,932, filed March 13, 1997.

Petitioners challenge Claims 6, 7, and 8. Claim 6 is in independent format.

Claim 6, annotated as referred to herein, reads:

6. [Preamble] A method of accessing blocks of data in a

1 IPR2019-00053 U.S. Patent 5,890,195 memory having a plurality registers and a memory array, comprising the steps of: [6a] receiving an address through an address port; [6b] comparing the received address with addresses previously stored in each of a plurality of latches; [6c] when a match occurs between the received address and a matching address stored in a one of the latches performing the substep of accessing a register corresponding to the latches storing the matching address through a data port; [6d and 6e] when a match does not occur between the received address and an address stored in one of the latches, performing the substeps of: exchanging data between a location in the memory array addressed by the received address and a selected one of the registers; and storing the received address in one of the latches corresponding to the selected register; [6f] modifying the received address to generate a modified address; [6g] exchanging data between a location in the memory array addressed by the modified address and a second selected one of the registers; and [6h] storing the modified address in of one of the latches corresponding to the second selected register. ʼ195 Patent at 19:8-33.

The ’195 Patent describes a system that includes registers, to store data that was previously read from a memory (e.g., a DRAM array 402). ‘195 Patent at

3:57-4:4, 8:51-55, 9:26-36, 10:10-12, and 11:66-12:22. The registers provide

2 IPR2019-00053 U.S. Patent 5,890,195 faster access to cached data as compared to retrieving the data from the memory.

‘195 Patent at 3:57-4:4. When data is read from the memory, the data is stored in

the registers, and the address of the data is stored in address latches (e.g., last row read (LRR) latches 502 or LRR latches 701) that are associated with the particular registers that store the data.

In addition to reading the requested data and storing the data (in the registers) and storing the address of the data (in the latches), the system also caches non-requested data from the memory. ‘195 Patent at 10:54-11:18. In an example, the system modifies the address of the requested data and uses the modified address to access the memory. Id. The non-requested data read from the memory is stored into the registers. Id. The modified address is stored in latches associated with the non-requested data. Id.

When a subsequent request for data is received, the address of the newly requested data is compared to the addresses in the latches. An address match indicates that the newly requested data is currently stored in the registers and can be accessed with reduced latency from the registers as compared to the memory.

Because data is typically accessed within temporally or spatially adjacent areas in the memory, there is a substantial probability that an address match will occur.

‘195 Patent at 11:31-43.

3 IPR2019-00053 U.S. Patent 5,890,195 B. Prosecution History of the ’195 Patent

United States Patent Application No. 08/855,944 (“the ’944 Application”) eventually issued as the ’195 Patent and was filed on May 14, 1997 as a continuation-in-part of United States Patent No. 5,835,932 filed March 13, 1997.

The ’944 Application received a first action notice of allowance on December 3,

1998 without any rejections based on prior art.

C. Claim Construction for the ’195 Patent

Petitioners state that the challenged claims of the ’195 Patent should be interpreted under the Philips standard. Petitioners do not propose any explicit constructions for any of the terms in claims 6-8 of the ’195 Patent. Patent Owner respectfully submits that no explicit constructions are necessary and that all claim terms should be given their ordinary and customary meaning which is understood by a person of ordinary skill in the art in question at the time of the invention.

Philips v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir. 2005). Petitioners implicitly argue that the terms “latch” and “register” in claim 6 are interchangeable, but this argument is technically incorrect and does not rebut the Federal Circuit-approved presumption that different claim terms be afforded different meanings. See §

III(A)(3)(b).

4 IPR2019-00053 U.S. Patent 5,890,195 III. THERE IS NO REASONABLE LIKELIHOOD THAT AT LEAST ONE OF THE CHALLENGED CLAIMS IS UNPATENTABLE A. GROUND 1 - Fukuda and Lin

Ground 1 alleges that Claims 6 and 8 are obvious in view of the combination of Fukuda and Lin. Ground 1 fails for at least the following reasons.

1. Brief Overview of Fukuda

Fukuda describes a system that includes multiple memory modules

(collectively labelled 10) and multiple cache memories (collectively labelled 12).

EX1005, FIG. 1 (reproduced below).

In Fukuda, an address signal is input to the system through an address line and transferred to each memory module 10 through an address buffer 13, an

5 IPR2019-00053 U.S. Patent 5,890,195 14, and a cache controller 15. EX1005, 6:21-26. The cache

controller 15 determines whether or not data corresponding to the input address is stored in the cache memories 12. EX1005, 6:38-40. When data is stored in the cache memories 12, the data is output from the cache memories 12 with a data read out time that is shorter than a data read out time of the memory modules 10.

EX1005, 6:40-44.

2. Brief Overview of Lin

Lin describes a system that includes a main memory dynamic random-access memory (DRAM) 26, a cache data static random-access memory (SRAM) 34, and a cache tag SRAM 32. EX1007, FIG. 1 (reproduced below).

6 IPR2019-00053 U.S. Patent 5,890,195

The system of Lin eliminates the use of “valid” bits in the cache tag SRAM

32 and instead writes permanently non-cacheable tags to the cache tag SRAM 32 upon initialization to clear the cache tag SRAM 32 of any random data that may

duplicate a valid tag. EX1007, 6:13-16 and 25-42. Lin also describes additional

components and signals to be used for communication between the various

components of the system.

7 IPR2019-00053 U.S. Patent 5,890,195 3. Analysis of Claim 6

a. The combination of Fukuda and Lin fails to render obvious storing addresses in latches (a first storage type) for address lookup and storing data in registers (a second storage type)

Claim 6 recites “comparing the received address with addresses previously

stored in each of a plurality of latches,” and therefore Claim 6 recites that

addresses are stored in latches. Further, claim 6 recites “exchanging data between a location in the memory array addressed by the modified address and a second selected one of the registers,” and therefore recites that data retrieved from a location in the memory array is stored in a register. Thus, under the plain language of claim 6, different types of storage (latches vs. registers) must be used for different types of data (addresses vs. data retrieved from memory).

In Fukuda, the cache memories 12 include “tag memories” that store tag

addresses and “data memories” that store cached data. EX1005, 6:45-62. Fukuda is silent on the “tag memories” being of a different type of data storage than the

“data memories.” Fukuda does not describe using latches (i.e., a first storage type) in the tag memories to store the tag addresses (i.e., a first data type) but using registers (i.e., a second storage type) to store the cached data (i.e., a second data type).

Petitioners state that Fukuda “does not describe details regarding memory structures that can be used” in the cache memory 12. Petition, p. 39. However,

8 IPR2019-00053 U.S. Patent 5,890,195 Fukuda is not completely silent on this issue. Ex. 2001 ¶ [43]. The annotated diagram below is reproduced from page 38 of the Petition. In the diagram,

Petitioners label a tag memory and a data memory of Fukuda.

The above diagram clearly shows that under Petitioners’ theory, Fukuda’s

“tag memory” and “data memory” are just different groups of bits in each of the

rows of the same “cache memory” array 12. Ex. 2001 ¶ [44]. A POSITA would not use different types of storage (e.g., latches and registers) for different bits of a row within the same memory array. Ex. 2001 ¶ [44]. Doing so would introduce unnecessary complexity to cache memory operations, which are designed with

speed in mind. Ex. 2001 ¶ [44]. A POSITA would know that if tag bits and data

bits are being stored in the same row of the same memory array, then the tag and data bits in that row would be implemented using the same underlying storage technology. See Ex. 2001 ¶ [44].

9 IPR2019-00053 U.S. Patent 5,890,195 A POSITA would understand Fukuda as teaching that the “tag memory” and the “data memory” are implemented using the same type of storage. Ex. 2001 ¶

[45]. Although Fukuda recognizes the difference between latches and registers as exhibited by Fukuda using the terms “latch” (e.g., at 1:25-33 and 2:14) and

“register” (e.g., size memory register 19, prediction switching register 18, interrupt generation register 218, key word register 802, mask register 803, output register

808, etc.) in different portions of the Specification, Fukuda does not distinguish between the underlying structures of the “tag memory” and the “data memory” portions of the row in the cache memory array 12. Instead, the “tag memory” and the “data memory” portions of the row in the cache memory array 12 are both described using the same term “memory” rather than specific terms like “latch” and “register.” Fukuda therefore fails to disclose storing addresses in latches (a first type of storage) and storing data in registers (a second type of storage).

Lin does not describe using latches in the cache tag SRAM 32 to store the

tag addresses and using registers to store data. Instead, Lin is silent regarding the

internal components of the cache tag SRAM 32 and the cache data SRAM 34.

Both of the memory structures of Lin cited in the Petition (the cache tag

SRAM 32 and the cache data SRAM 34) are SRAMs, so if anything, Lin (like

Fukuda) implies that the same underlying data storage type is used for the cache tag SRAM 32 and the cache data SRAM 34. Ex. 2001 ¶ [47]. Although Lin

10 IPR2019-00053 U.S. Patent 5,890,195 recognizes the difference between latches and registers (explained further below),

Lin does not distinguish between the underlying structures of the cache tag SRAM

32 and the cache data SRAM 34. Instead, the cache tag SRAM 32 and the cache data SRAM 34 are described using the same term “SRAM.”

Lin teaches by example that registers are used for long-term storage in components that are accessible via a CPU bus. Ex. 2001 ¶ [48]. As an example of using registers for long-term storage that is accessible to a CPU, Lin describes:

[T]he chipset in the system of FIG. 2 operates in response to a plurality of command and configuration registers which may be written to or read from by the CPU 212... these registers are directly addressable in the I/O address space. Most values are written once during the system power-on sequence in response to instructions in system BIOS ROM 222.

EX1007, 36:32-40.

Lin also teaches by example that latches are used for short-term storage. Ex.

2001 ¶ [49]. As an example of using latches for short-term storage, Lin describes using latches for transferring information between busses in response to control signals from a bus controller (EBC 220) rather than the CPU:

“The address lines 208 of EISA bus 202 are further coupled to provide information via a latch and buffer 234 to the SA address lines 210 of ISA bus 203, which are in turn are coupled via a buffer in the latch/buffer 234 to provide information to the address lines 208 of EISA bus 202. An additional latch 236 couples other bits of address lines 208 of EISA bus 202 to the SA address lines 210 of ISA bus 203. The EBC 220 generates control signals for the buffers 218, 230 and 232 and latch/buffer 234.”

11 IPR2019-00053 U.S. Patent 5,890,195 EX1007, 25:16-25

The cache tag SRAM 32 and the cache data SRAM 34 perform long-term

storage and are accessible via a CPU bus. Thus, according to the teachings of Lin,

tag addresses are not stored in latches. Ex. 2001 ¶ [50].

Various “registers” in Lin are used for long-term storage of data over multiple-clock cycles, such that the data is accessible by the CPU 10 via the CPU bus 12:

Register Name Register Location Data Type Control Register I system controller control data (17:40-49, 17:50:53) chip 18 or controller 20, accessible to CPU Control Register II system controller control data (e.g., (17:40-49, 17:54:66) chip 18 or data cache enable, cache buffer controller 20, size) accessible to CPU Control Register III system controller control data (e.g., (17:40-49, 18:64- chip 18 or data caching 19:2, 8:35-37) buffer controller 20, enable/disable bit) accessible to CPU Shadow RAM system controller control data (e.g., Control Registers I, chip 18 or data enable shadow RAM II, III buffer controller 20, ranges) accessible to CPU

12 IPR2019-00053 U.S. Patent 5,890,195 (17:40-49, 17:66- 18:54) DRAM Control system controller control data (e.g., Registers I, II chip 18 or data DRAM bank size (17:40-49, 18:34-63) buffer controller 20, and wait states) accessible to CPU Non-Cacheable system controller data indicating user- Block 1 Register 1, 2 chip 18 or data defined non- (FIG. 10 A/B, 19:14- buffer controller 20, cacheable memory 32) accessible to CPU blocks DBC control register data buffer controller copy of control data (19:55-60) 20, accessible to from system CPU controller 18 Memory/Cache memory/cache control information; Controller registers controller (MCC) most values are (36:32-45, Table 213, accessible to written once, during VII). CPU system power-on sequence configuration EISA bus controller configuration registers (EBC) 220 information (36:20-21) EISA ID register (unspecified) EISA ID (36:7, 23)

In contrast, “latches” in Lin are used for short-term storage of data over partial clock cycles, where the data is accessible via signaling rather than via the

13 IPR2019-00053 U.S. Patent 5,890,195 CPU bus 12:

Latch Name Latch Location Data Type Latch and buffer 234 Between ISA bus Address bits 203 and EISA bus 202 Latch 236 Between ISA bus Address bits 203 and EISA bus 202 (Unnamed) LA (23:17) lines of Address bits, latched (8:20-25) the AT bus 38 during early part of AT bus cycle for access during later part of bus cycle Bus address latch Bus address lines Address bits (9:60) CA (16:8) Address System controller ROM and keyboard latch (SYSC) 18, at data from XD bus (col. 11, col. 13) address lines CA (Peripheral Data (16:8) Bus) DRAM Read Data System controller 18, Data for parity latch (col. 13) at Interface to Data checking Bus Controller Chip AT-bus 16-bit Slave System controller 18, Slave status, used for Status latch at Interface to Data bus conversion (col. 13) Bus Controller Chip

14 IPR2019-00053 U.S. Patent 5,890,195 DRAM Read Data Buffer controller 20, Data for parity latch (col. 18) at Interface to checking System Controller 18 Host Address Bus MCC 213, between Address bits transparent latches host address (HA) (col. 31) bus pins and multiplexed DRAM address (MA) bus pins Cache Address Bus MCC 213, latches Address bits latches (col. 33) that create the cache address bus CA[18:4] from the HA bus Latches unspecified Address/data byte (35:1-5) lane translation/swapping

In Lin, the Cache Tag SRAM 32 and the Cache Data SRAM 34 are each connected to and addressed by the CPU bus 12. EX1007, 8:10-12 and Fig. 1. The

Cache Tag SRAM 32 provides long-term (e.g., multiple clock cycle) storage of addresses that are used to identify the data that is stored in the Cache Data SRAM

34. The Cache Data SRAM 34 provides long-term (e.g., multiple clock cycle) storage of data. See generally EX1007, 4:22-39.

Thus, a POSITA would understand Lin as teaching that “latches” are used

15 IPR2019-00053 U.S. Patent 5,890,195 for short-term data storage and “registers” are used for long-term data storage with

CPU bus access. Ex. 2001 ¶ [54]. Further, a POSITA would recognize that Lin’s

Cache Tag SRAM 32 and Cache Data SRAM 34 perform long-term data storage

and are accessible to the CPU bus 12. Ex. 2001 ¶ [54]. Therefore, a POSITA

would recognize Lin as teaching that tag addresses are not stored in “latches.” Ex.

2001 ¶ [54].

b. Petitioners’ Assertions Regarding “Latches” and “Registers” are Technically and Legally Flawed

Petitioners assert that “‘latches,’ ‘registers,’ and ‘SRAMs’… are

interchangeable in terminology as understood by POSITAs.” Petition, p. 43.

However, A POSITA reading Lin would recognize that the latches, registers and

SRAM in Lin are not simply interchangeable in implementation. Ex. 2001 ¶ [55].

As explained above, Lin teaches that “latches” are used for short-term data storage

and that “registers” are used for long-term data storage with CPU bus access.

Thus, a POSITA would understand that Lin teaches that “latches” and “registers”

are not interchangeable. Ex. 2001 ¶ [55]. Further, a POSITA would understand

that Lin would not implement the Cache Tag SRAM 32 using “latches.” Ex. 2001

¶ [55].

Petitioners rely on the Declaration of Dr. Shamos (EX1003), at ¶ 54, to support the assertion that the term ‘latch’ and ‘register’ are interchangeable and that the term ‘latch’ “sometimes even refers to RAMs.” Petition, p. 16. However,

16 IPR2019-00053 U.S. Patent 5,890,195 Dr. Shamos’ declaration provides no support for this assertion. In ¶ 55, the declaration asserts that Shin (EX1009, a patent not cited in any of the Grounds) recites in its abstract that “[a] digital data memory unit and memory unit array, each unit of which . . . utilizes a digital storage element in the form of a register, latch, or memory cell, a comparator and control logic.” EX. 1003, ¶¶ 54-55. This quote, at best, indicates that the specific digital data memory unit and memory unit array of Shin is able to support a digital storage element that is in the recited forms.

Ex. 2001 ¶ [56]. The abstract of a single patent that is not cited in any of the

Grounds is not sufficient evidence to support the Petitioners’ assertion that the term “latch” is interchangeable with “register” and sometimes refers to “RAMs.”

Ex. 2001 ¶ [56]. This is especially true in view of the contrary evidence in Lin, a reference relied upon and included in Petitioners’ Grounds.

Petitioners also assert that “‘latches,’ ‘registers,’ and ‘SRAMs’… could be used as memory structures based on the disclosures of Fukuda and Lin… it would

have been obvious to use latches for the tag memories because those, too, would possess the desired properties [which Petitioners have not identified] for a cache

memory as disclosed in Lin.” Petition, p. 43 (underline added). However, Lin

teaches that “latches” are used for short-term storage and do not have the desired properties for tag memories (e.g., long-term storage and CPU bus access). Ex.

2001 ¶ [57].

17 IPR2019-00053 U.S. Patent 5,890,195 Petitioners further assert that “it would have simply been choosing from a

finite number of options available to be used as such memory structures… with a

reasonable expectation of success.” Petition, p. 44. Again, however, because Lin

teaches that “latches” are used for short-term storage and do not have the desired

properties for tag memories (e.g., long-term storage and CPU bus access), Lin

teaches that latches would not be considered as an option for a cache tag SRAM.

Lin teaches that using “latches” in a cache tag SRAM would not have a reasonable expectation of success. Thus, a POSITA following the teachings of Lin would not include latches in the alleged list of “finite options” to choose from with a reasonable expectation of success. Ex. 2001 ¶ [58]. Further, the standard for

obviousness is not that a POSITA could have simply selected another option. See

In re Cyclobenzaprine Hydrochloride Extended-Release Capsule Patent Litig., 676

F.3d 1063, 1070–71 (Fed. Cir. 2012) (“Where, however, a defendant urges an obviousness finding [based on pursuing one of a finite number of options] by merely throwing metaphorical darts at a board in hopes of arriving at a successful result, but the prior art gave either no indication of which parameters were critical or no direction as to which of many possible choices is likely to be successful, courts should reject hindsight claims of obviousness.”) (Internal quotations omitted).

Petitioners assert that using latches in the cache tag SRAM “would have

18 IPR2019-00053 U.S. Patent 5,890,195 been a simple substitution of one known interchangeable element for another to

obtain predictable results.” Petition, p. 44. However, as explained above Lin

teaches that latches, registers, and SRAM are not interchangeable. Further, substituting latches for registers, as suggested by Petitioners, would have led to a result inconsistent with the teaching of Lin. Thus, a POSITA reading Lin would not substitute latches for registers in an implementation calling for long-term storage of data with CPU bus access. Ex. 2001 ¶ [59].

Patent Owner’s expert Steve Novak notes that the combination of Fukuda with Lin as proposed by Petitioners would result in a cache memory in which the

“tag memories” and “data memories” of Fukuda are replaced with the cache tag

SRAM 34 and cache data SRAM 32, respectively, of Lin. Petition, p. 41; Ex. 2001

¶ [60]. As demonstrated above, Lin teaches that the cache tag SRAM 34 would not use latches. Therefore, the proposed combination does not disclose or suggest storing addresses in latches while storing data in registers. Ex. 2001 ¶ [60].

None of the four references cited by Petitioners for claim 6 (Fukuda, Lin,

Smith, and Horowitz) discloses the storage of address data in latches for address

lookup. Petitioners have not provided a single specific citation to Fukuda, Lin,

Smith, or Horowitz that discloses storing address data in latches for address

lookup. See Petition at pp. 42-54, 60-68. Instead, Petitioners request the Board to

conclude that two distinctly recited terms in the claim (“latch” and “register”) are

19 IPR2019-00053 U.S. Patent 5,890,195 somehow “interchangeable,” see, e.g., Petition at pp. 42-44, 48, 62-63. The use of

two different claim terms gives rise to the presumption that a different meaning

should be assigned to each, and Petitioners have failed to rebut this presumption.

See Bancorp Services, L.L.C. v. Hartford Life Insurance Co., 359 F.3d 1367, 1373

(Fed. Cir. 2004) (“[T]he use of both terms in close proximity in the same claim

gives rise to an inference that a different meaning should be assigned to each.”);

Ethicon Endo-Surgery, Inc. v. U.S. Surgical Corp., 93 F.3d 1572, 1579 (Fed. Cir.

1996) (“If the terms ‘pusher assembly’ and ‘pusher bar’ described a single element,

one would expect the claim to consistently refer to this element as either a ‘pusher

bar’ or a ‘pusher assembly,’ but not both, especially not within the same clause.”).

4. Ground 1 fails

For at least the foregoing reasons, Ground 1 fails to present a prima facie

case of obviousness for claim 6. Because claim 8 depends from claim 6, Ground 1

also fails to present a prima facie case of obviousness for claim 8.

B. GROUND 2 – Fukuda, Lin, and Matsuda

Ground 2 alleges that claim 7, which depends from claim 6, is rendered

obvious in view of the combination of Fukuda, Lin, and Matsuda. Petitioners do

not rely on Matsuda for any elements of claim 6. Petition, pp. 56-59. Thus,

Ground 2 fails for at least the same reasons as Ground 1.

20 IPR2019-00053 U.S. Patent 5,890,195 C. GROUND 3 – Smith and Horowitz

1. Brief Overview of Smith

Smith describes a cache that stores tags and data side-by-side in an array.

EX1006, Fig. 2 (reproduced below). The array receives the data and tags from a common input element and outputs selected data and addresses to a common output element. EX1006, Fig. 2 (reproduced below).

Smith also describes an alternative implementation in which address tags and data are stored separately in an address array and a data array, respectively.

EX1006, p. 477.

21 IPR2019-00053 U.S. Patent 5,890,195 2. Brief Overview of Horowitz

Horowitz describes that “the term ‘latch’ is usually reserved for a special kind of register: one in which the outputs follow the inputs when enabled, and hold the last value when disabled. Horowitz also describes that “[s]ince the term ‘latch’

has become ambiguous with use, the terms ‘transparent latch’ and ‘type D register’

are often used to distinguish these closely related devices.” EX1008, p. 523.

Horowitz describes that “some variations on the latch/register are as follows:

(a) random-access memories (RAMs) . . . (b) addressable latches . . . (c) a latch or register built into a larger chip[.]” EX1008, p. 524.

3. Analysis of Claim 6

a. The combination of Smith and Horowitz fails to render obvious storing addresses in latches (a first storage type) for address lookup and storing data in registers (a second storage type)

Smith describes a “side-by-side” implementation in which tag bits and data

bits are stored side-by-side in a single cache entry of an array. EX. 1006, Fig. 2;

Ex. 2001 ¶ [67]. Smith also describes a “separate arrays” implementation in which

address tags and data are stored in separate address and tag arrays, respectively.

EX1006, p. 477; Ex. 2001 ¶ [67].

In Smith, the data and tags are received from a common input element, and

data and tags are output to a common output element. EX1006, Fig. 2; Ex. 2001 ¶

[68]. Smith is silent regarding the type of storage elements used in the side-by-side

22 IPR2019-00053 U.S. Patent 5,890,195 implementation and the separate arrays implementation. Ex. 2001 ¶ [68].

Petitioners agree on this point, stating that in Smith “there are no particular memory structures disclosed for the different memories[.]” Petition, p. 61. A search for the term “latch” in Smith provides no results.

A POSITA would not use different types of storage (e.g., latches and

registers) for different bits of a row within the same memory array. See §

III(A)(3)(a); Ex. 2001 ¶ [69]. Doing so would introduce unnecessary complexity

to cache memory operations, which are designed with speed in mind. See §

III(A)(3)(a); Ex. 2001 ¶ [69]. This reasoning applies to the “side-by-side”

implementation of Smith as well. Ex. 2001 ¶ [69]. A POSITA would know that if

tag bits and data bits are being stored in the same row of an array, then the tag and data bits in that row would be implemented using the same underlying storage technology. Ex. 2001 ¶ [69]. Implementing alternating sections of latches and registers in each row of the array of Smith would introduce cost and complexity as

compared to implementing the array using, for example, all registers. Ex. 2001 ¶

[69].

Horowitz describes that “latches” and “registers” behave differently. Ex.

2001 ¶ [70]. In particular, a “latch” in Horowitz has different responses to control inputs than a (conventional) “register.” EX1008, p. 523 (describing two registers as having positive clock edge and three-state outputs or a reset; describing a latch

23 IPR2019-00053 U.S. Patent 5,890,195 as one in which outputs follow inputs when enabled and hold the last value when disabled). Ex. 2001 ¶ [70]. Because Horowitz describes a “latch” as different from a register and because a RAM is a “variation” on “latch/register,” Horowitz does not state that the terms are interchangeable. Ex. 2001 ¶ [70]. Horowitz therefore fails to rebut the presumption that the terms “latch” and “registers” should mean different things in claim 6 and are not interchangeable. See § II(C).

And contrary to Petitioners’ argument, Horowitz fails to disclose or suggest storing addresses in latches (a first storage type) and storing data in registers (a second storage type).

Further, the combination of Smith with Horowitz as proposed by Petitioners would result in the cache of Smith that stores address tags and data side-by-side in an array, or alternately, that stores address tags and data separately in an address array and a data array. Ex. 2001 ¶ [71]. Therefore, the proposed combination of

Smith with Horowitz would store addresses and data in the same type of storage.

Ex. 2001 ¶ [71]. The combination does not disclose or suggest storing addresses in latches while storing data in registers (i.e. different types of storage).

4. Ground 3 fails

For at least the foregoing reasons, Ground 3 fails to present a prima facie case of obviousness for claim 6. Because claim 8 depends from claim 6, Ground 3

also fails to present a prima facie case of obviousness for claim 8.

24 IPR2019-00053 U.S. Patent 5,890,195 D. GROUND 4 – Smith, Horowitz, and Matsuda

Ground 4 alleges that claim 7, which depends from claim 6, is rendered

obvious in view of the combination of Smith, Horowitz, and Matsuda. Petitioners

do not rely on Matsuda for any elements of claim 6. Petition, pp. 81-83. Thus,

Ground 4 fails for at least the same reasons as Ground 3.

IV. PETITIONERS FAIL TO IDENTIFY ALL REAL PARTIES-IN- INTEREST An IPR Petition must list “all real parties in interest.” 35 U.S.C. §312(a)(2)

(emphasis added). An IPR petitioner’s initial identification of the real parties in interest should be accepted “unless and until disputed by a patent owner.” Worlds

Inc. v. Bungee, Inc., No. 17-1481 (Fed. Cir. 2018). “Determining whether a party

is a real party in interest demands a flexible approach that takes into account both

equitable and practical considerations, with an eye toward determining whether the

non-party is a clear beneficiary that has a preexisting, established relationship with the petitioner.” Worlds at 17 (citing Applications in Internet Time, LLC v. RPX

Corp., 897 F.3d 1336, 1351 (Fed. Cir. 2018)) (Emphasis added, internal quotations

omitted).

Patent Owner submits that at least the following parties are real parties in

interest: STMicroelectronics Inc., Broadcom Corp., and Motorola Mobility LLC

(“Alleged RPIs”). Patent Owner has ongoing litigation (“Alleged RPI

Litigations”) against each of the Alleged RPIs for infringing, inter alia, the ’195

25 IPR2019-00053 U.S. Patent 5,890,195 Patent.1 Petitioners license technology related to each of the Alleged RPI

Litigations. Petitioners also have a longstanding practice to comply with industry

norms and indemnify its licensees (including the Alleged RPIs) “in the event that

the [licensed] technology licensed is held to infringe the IP of a third party.”2

Examples of ARM licensees include Texas Instruments, Inc. (“TI”) and each of the

Alleged RPIs: STMicroelectronics Inc., Broadcom Corp., and Motorola Mobility

LLC.3

Patent Owner filed suit against TI on October 13, 2017, alleging

infringement of, inter alia, the ’195 Patent. As demonstrated in the Infringement

Contentions for the ’195 Patent from that case, TI products incorporating certain

ARM cores were identified as infringing claims 6-8 of the ‘195 Patent.

1 See Complex Memory, LLC v. STMicroelectronics (N.D. Tex. Case No. 3:18-cv-03018);

Complex Memory, LLC v. Broadcom Corp. (N.D. Cal. Case No. 3:18-cv-07530); and Complex

Memory, LLC v. Motorola Mobility LLC (N.D. Ill. Case No. 1:18-cv-06255).

2 “It is common industry practice for licensors of technology to offer to indemnify their licensees for loss suffered by the licensee in the event that the technology licensed is held to infringe the IP

of a third party. Consistent with such practice, the Group provides such indemnification to its

licensees.” Exhibit 2003 (ARM 2015 Governance and Financial Report) at 91.

3 Petitioner has provided evidence regarding ARM licensees. See, e.g., Exhibit 2004 (ARM

Licenses to STMicroelectronics); Exhibit 2005 (ARM Licenses to Broadcom); and Exhibit 2006

(ARM Licenses to Motorola Inc., a predecessor of Motorola Mobility).

26 IPR2019-00053 U.S. Patent 5,890,195 Exhibit 1012. TI challenged claims 6-8 of the ’195 Patent in IPR2018-00823,

which was filed on March 22, 2018. The ’823 IPR filed by TI was dismissed after

Patent Owner and TI reached a settlement. Each of the Alleged RPI Litigations

remains ongoing.

On October 12, 2018 – just prior to the statutory bar date for filing an IPR by

a real party in interest with respect to TI – Petitioners filed the Petition for

IPR2019-00053, which Petitioners admit is “substantively identical” to the Petition

from the TI’s ’823 IPR. ’053 Petition, p. 1. The Board noted in its Order denying

Patent Owner’s request to submit a motion for additional discovery regarding

Petitioners’ licensees and its indemnity obligations (Paper No. 6) that the October

12, 2018 filing of the present Petition was within the one-year time limit of the

service of the district court complaint against TI. However, Patent Owner submits

that the timing of the instant petition (just prior to the one-year deadline) is

evidence that Petitioners believe that they were a real party in interest in TI’s ’823

IPR. Petitioners were an unnamed real party in interest with respect to TI’s ’823

IPR, because Petitioners had a prior, established relationship with TI by virtue of

being a technology licensor to TI and by virtue of its indemnity obligations to TI,

and, as an indemnitor, stood to benefit (e.g., in the form of reduced indemnity

liability) from institution of the ’823 IPR. In fact, Petitioners have admitted to

being a real party in interest in this IPR by virtue of having filed the Petition,

27 IPR2019-00053 U.S. Patent 5,890,195 despite Patent Owner not having asserted the ’195 Patent against Petitioners. As such, Petitioners admit to being a real party in interest by virtue of its licensor- licensee agreements. Therefore, 35 U.S.C. § 315 bars Petitioners from filing further IPRs challenging any of the patents asserted against TI, including the ’195

Patent.

An early settlement agreement was reached between Patent Owner and TI, prior to any real party in interest issue being briefed in the ’823 IPR. However,

Patent Owner submits that similar logic (Petitioners and their licensees being real

parties in interest) applies to the current IPR.

More specifically, Petitioners’ remaining licensees that are in suit with

Patent Owner (i.e., at least the Alleged RPIs) would be clear beneficiaries of an

IPR instituted to review the ‘195 Patent (e.g., through stays of litigation or

improved negotiating positions). In addition, such licensees have a preexisting,

established relationship with Petitioners, at least through a license and indemnity

agreement and likely a technology sharing agreement.4,5 Because such licensees

4 See note 3.

5 Petitioners admit and notify investors that they follow the “common industry practice” of indemnifying licensees. See note 2. Petitioners have also filed declaratory judgment actions when licensees have been accused of infringement. See, e.g., ARM LTD. and ARM INC.’s First

Amended Complaint for Declaratory Judgment, ARM, LTD. and ARM, INC. v. MOSAID

28 IPR2019-00053 U.S. Patent 5,890,195 are clear beneficiaries that have a preexisting, established relationship with the

Petitioners, such licensees are by definition real parties in interest. Worlds at 17.

By not properly listing all real parties in interest, Petitioners have harmed Patent

Owner6 and have failed to notify the Board of essential information.7 Petitioners’ failure to list any of its licensees, including the Alleged RPIs, in its Petition is an

independent reason to dismiss the Petition outright.

V. CONCLUSION

For at least the reasons set forth above, Patent Owner respectfully requests

that all challenges in the present IPR be dismissed.

Technologies Inc., Case No. 3:11-cv-03869 (N.D. Cal.), Docket No. 10, Aug. 26, 2011, ¶ 26

(“ARM has certain obligations to one or more of the Threatened Customers which include

certain obligations to indemnify its customers under certain conditions for threats of patent

infringement liability which implicate products, including processor cores, supplied by ARM.”)

6 For example, by effectively enabling the Alleged RPIs to escape the estoppel provisions of

35 U.S.C. § 315(e).

7 See, e.g., Bennet Regulator Guards, Inc. v. Atlanta Gas Light Co., 905 F.3d 1311, 1314 (Fed.

Cir. 2018) (failure to properly update real parties in interest created new conflicts and led to post-

decision reconstitution of Board).

29 IPR2019-00053 U.S. Patent 5,890,195

Date: February 6, 2019 Respectfully submitted,

By: /s/ Jeffrey G. Toler Jeffrey Toler, Reg. No. 38,342 Daniel Ford, Reg. No. 66,102 Attorney for Patent Owners

30 IPR2019-00053 U.S. Patent 5,890,195 CERTIFICATE OF COMPLIANCE

Pursuant to 37 C.F.R. § 42.24(d), we certify that this Preliminary Response

to Petition complies with the type-volume limitation of 37 C.F.R. § 42.24(b)

because it contains fewer than the limit of 14,000 words, as determined by the

word-processing program used to prepare the brief, excluding the parts of the brief

exempted by 37 C.F.R. § 42.24(a)(1).

Date: February 6, 2019 Respectfully submitted,

By: /s/ Jeffrey G. Toler Jeffrey G. Toler Attorney for Patent Owners Reg. No. 38,342

i IPR2019-00053 U.S. Patent 5,890,195 CERTIFICATE OF SERVICE

Pursuant to 37 C.F.R. §§ 42.6(e), we certify that an electronic copy of the foregoing PATENT OWNER’S PRELIMINARY RESPONSE PURSUANT TO 37

C.F.R. § 42.107(a) along with any accompanying exhibits was served on Petitioners’ counsel of record at the following address:

WILEY REIN LLP

Kevin P. Anderson, Reg. No. 43,471 [email protected]

Scott A. Felder, Reg. No. 47,558 [email protected]

Date: February 6, 2019 Respectfully submitted,

By: /s/ Diane Jacobs Diane Jacobs 8500 Bluffstone Cove Suite A201 Austin, Texas 78759 Telephone: 512-327-5515 Facsimile: 512-327-5575

ii