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Embedded Processors and CPU Cores Embedded Processors and CPU Cores EE8205: Embedded Computer Systems http://www.ee.ryerson.ca/~courses/ee8205/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview • CPU Basics Operation • Embedded CPUs • Nios-II CPU Organization • Nios-II Cores • MPS32K CPU Core Text by M. Wolf: part of Chapters/Sections 2.1, 2.2, 2.3 and 3.1-3.5 © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:1 Processor Architecture von Neumann Architecture • Memory holds data, instructions. • Central processing unit (CPU) fetches instructions from memory. • Separate CPU and memory distinguishes programmable computer. • CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc. address PC Memory data CPU 200 ADD r5, r1, r3 IR © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:2 Harvard Architecture address Data memory data PC CPU address Program memory data • Harvard architecture cannot use self-modifying code. • Harvard allows two simultaneous memory fetches. • Most DSPs use Harvard architecture for streaming data: . greater memory bandwidth . more predictable bandwidth © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:3 Instruction Execution Process Instruction Fetch: Reads next instruction into instruction register (IR). Instruction address is in the program counter (PC). Instruction Interpretation: Decodes the op-code, gets the required operands and routes them to ALU. Sequencing Determines the address of next instruction and loads it into the PC. Execution: Generates control signals of ALU for execution. © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:4 System Organization Memory and I/O having Separate Bus Memory Bus I/O Bus © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:5 Memory Mapped Peripherals © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:6 Single Accumulator Architecture © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:7 Cache Memory • Cache: Expensive but very fast memory directly connected to CPU interacting with slower but much larger main memory. • Invisible to OS and user programs but interact with memory management hardware. • Processor first checks if the addresses word is in cache. • If the word is not found in cache, a block of memory containing the word is moved to the cache. address data Cache Main CPU cache controller address Memory data data © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:8 Separate Data and Instruction Caches FF..FF copies of 16 instructions address instructions cache address instructions instructions registers processor address data data address copies of data data memory cache 00..0016 © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:9 A Unified Instruction and Data Cache FF..FF 16 registers instructions processor instructions address and data data copies of instructions address copies of data memory cache 00..00 instructions 16 and data © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:10 CPU Pipelining Improve performance by increasing instruction throughput. Ideal speedup is equal to number of stages in the pipeline. 1st Instruction (Adrs: PC) Fetch Decode Execute 2nd Instruction (Adrs: PC+1) Fetch Decode Execute 3rd Instruction (Adrs: PC+2) Fetch Decode Execute Time © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:11 CPU Pipelining What makes pipelining easy? • When all instructions are of the same length. • Few instruction formats. • Memory operands appear only in loads and stores. What makes pipelining hard? • Structural Hazards: Single memory • Control Hazards: Branch instructions • Data Hazards An instruction depends on a previous instruction © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:12 CPU Power Consumption • Most modern CPUs are designed with power consumption in mind to some degree. • Power vs. energy: . Heat depends on power consumption; . Battery life depends on energy consumption. Power Saving Strategies • Reduce power supply voltage. • Run at lower clock frequency. • Disable the CPU functional units with control signals when they are not in use. • Disconnect parts from power supply when not in use. © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:13 RISC Architecture RISC: Reduce Instruction Set Computer CISC: Complex Instruction Set Computer RISC Features • RISC instruction set attributes includes a load/store model of execution. (CISC has memory/register model) • A non-destructive triadic register file that provides a distinct and highly efficient data preservation model. (CISC has destructive accumulator/register file) • Normalized fixed length instructions. (CISC has variable length contextual-field instructions) Load/Store Model of Execution • The only instructions that can access main memory are load and store instructions. • All the other instructions operate on internal register files. • Increases concurrency, raising performance by de-coupling the loading and storing operation from data processing operations. © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:14 Non-Destructive Model Non-destructive architecture, Data Preserving Model, is fundamental to minimize the load-store traffic. For example in an addition instruction: RISC Model: AR <= BR + CR A combined load/store and non-destructive register model provides a dramatic boost in RISC performance. • RISC ability to minimize the load/store traffic from/to memory. • De-coupling load/store and processing operations. • Allow optimizing compilers to fill the stall slots. © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:15 Leading RISC Architectures SPARC, MIPS, ARM, ARM Cortex, Nios-II, µBlaze SPARC: Scalable Processor Architecture • The first and open RISC architecture • Created by Sun Microsystems in response to the declining performance enhancement of CISC microprocessors • RISC work is based on Patterson research at UC Berkeley MIPS32 4Kx based soft processor core. • Supported by 5 semiconductor licenses Cypress, Texas Instruments, LSI Logic, Fujitsu, and Bit • A flexible, scalable RISC architecture. Current implementations are in CMOS, ECL and GaAs. A complete architecture having: • Integer unit, Floating point unit • Memory Management and Cache Controller • Multiprocessing © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:16 Processor Operation Modes User mode . A user program is running. Certain instructions are not allowed. Memory mapping (base and bound) is enabled. Supervisor mode . The operating system is running. All instructions are allowed. Memory mapping (base and bound) is disabled. A single PSW (processor status word) bit sets the above two modes: For instance: PSW-bit =1 for Supervisor mode PSW-bit =0 for User mode © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:17 Interrupts A computer program has only two ways to determine the conditions that exist in internal and external circuits. • One method uses software instructions that jump to subroutine on some flag status. • The second method responds to hardware signals called interrupts that force the program to call interrupt-handling subroutines. • Interrupts take processor time only when action is required. • Processor can respond to an external event much faster by using interrupts. The whole programming of microcomputers and micro- controller by using interrupts is called real-time programming. Interrupts are often the only way in which real-time programming can be done successfully. © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:18 Interrupt based I/O Computers permit I/O modules to INTERRUPT a CPU during its normal operation. • I/O module asserts an interrupt request on the control bus. • CPU transfers the control to an interrupt handler routine. • Interrupt handler is generally part of the operating system. Interrupts . Allows the processor to execute other instructions while an I/O operation is in progress. Suspension of a processing caused by an event external to a processor in such a way that the computation can be resumed. Improves processing efficiency. © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:19 Instruction Cycle with Interrupts CPU check for interrupts at the end of each instruction and executes the interrupt handler if required. Interrupt Handler program identifies the nature/source of an interrupt and performs whatever actions are needed. • It takes over the control after the interrupt. • Control is transferred back to the interrupted program that will resume execution from the point of interruption. • Point of interruption can occur anywhere in a program. • State of the program is saved. (PC + PSW + relevant registers + …) User program 1 i Interrupt handler i+1 © G.N. Khan Embedded Processors and Cores – EE8205: Embedded Computer Systems Page:20 Interrupt Processing Hardware Device controller or other system h/w Software issues an interrupt Processor finishes Save remainder of execution of current process state instruction information Processor signals acknowledgment of interrupt Process interrupt
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