DOCSLIB.ORG

Rejuvenating Computer Architecture Research (And the Whole Semiconductor Industry) with Open-Source Hardware

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

Rejuvenating Computer Architecture Research (and the whole semiconductor industry) with Open-Source Hardware Krste Asanovic UC Berkeley, RISC-V Foundation, & SiFive Inc. [email protected] Keynote, MICRO-52, Columbus,Ohio October 14, 2019 What did Moore predict in famous Law? At lowest cost/component, number of components/die doubles every 12 months. 2 Moore’s Law: Worse than dead, now irrelevant! . Very few potential products in advanced nodes are constrained by marginal cost/transistor 3 CMOS Today . Wonderful, almost magical, technology . Fabricate billions of transistors . Reliably connect them with billions of wires . Clock at a few GHz . Dissipate <100W . Near 100% yield, cost a few $/die . Scaling continuing, if economically challenged . Manufacturing is least of our problems 4 Custom Chip Costs . NRE: Non-Recurring Engineering costs - Design + tooling for production . Marginal manufacturing cost/chip - Cost of each chip made once in production - Silicon manufacture plus package & test 5 Overall Cost/Project (grossly simplified) Expected lifetime cost Total cost Total Intercept set by NRE Expected lifetime shipments Total #transistors shipped 6 Chip Development Cost [Source: IBS] At $0.5B cost, not many $Bs markets in which to make a profit Caveat: figure assumes all IP developed from scratch and only leading projects do this, but do need >$100M return to justify <28nm tech 7 Overall Cost/Project <28nm Newer nodes Total cost Total End of Moore’s Law, Flat Design Productivity: NRE doubling each generation, but slope not Older changing, or increasing, each generation! node Total #transistors 8 “Moore’s Law” Business Model . Design standard part for the “killer socket” . Killer socket was PC, now smartphone, next is ??? . Sell 100s millions parts . Ideally, ~O(1) product, ~O(∞) volume . At infinite volume, profit set by marginal price/cost What Moore’s Law is about 9 New Vertical Semiconductor Business Model Instead of standard chip products, chip customers want own differentiated chip designs: . Apple, Samsung, Huawei for phones . Google, Amazon, Microsoft, Alibaba for client/cloud . Tesla for cars . End-system value justifies chip NRE But what about non-huge firms & startups, with great ideas but can’t afford NRE? 10 Semiconductor Industry Perfect Storm “Cold air” Custom chip design too costly, slow, risky “Hot air” New applications need capabilities from custom chips: Cloud AI, Edge Learning, Wearables, IoT, Autonomous Vehicles, … 1111 How did turn into a $1B acquisition with only 13 employees?* COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. 12 * https://www.sigarch.org/open-source-hardware-stone-soups-and-not-stone-statues-please Tech Stack Open-Source Technology from techstacks.io Infrastructure COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. 13 Talk Outline . History of open-source hardware . The RISC-V story . Reinvigorating the hardware industry . How architecture research can benefit and help 14 Early Days in Open-Source Hardware . SPICE released by Berkeley in 1973 . Mead & Conway VLSI revolution, late 70s, simplified design rules, spawned MOSIS fabrication service, and a generation of open-source tools – Magic/espresso/MIS/SIS/Lager (Berkeley), irsim (Stanford), chipmunk (Caltech) . Early 80s, university RISC projects (Stanford, Berkeley) used and help build open-source CAD tools . Together with C and BSD Unix, helped create the RISC workstation industry (Sun, MIPS, SGI, …) and the ECAD industry (Cadence, Mentor, Synopsys) 15 Ring Array Processor, (ICSI 1989) (Nelson Morgan, Jim Beck, Phil Kohn, Jeff Bilmes) . RAP Machine built for fast training of “big dumb” neural networks for speech recognition . Ring of TMS320C30 floating-point DSPs – Each DSP providing 32MFLOPS (32-bit FP) – Four DSPs/board, up to 10 boards connected at once (>1GFLOP/s peak, 640MB DRAM) – Neural net training rate of >100MCUPS (million connection updates per second) on 10 boards – FPGA ring connection used for systolic all-all communication during training/inference . Fast, flexible, but expensive – ~$100,000 each 16 Realization Group, ICSI, 1990 New naïve grad student joins Morgan’s group to build custom ANN VLSI for speech training This is a cool ANN architecture for which we need custom silicon! Unary-encoded inputs to avoid multiply, 12-bit weights 17 HiPNeT-1: (Highly Pipelined Network Trainer, 1990) Krste Asanovic, Brian Kingsbury, Nelson Morgan, John Wawrzynek . Custom architecture for neural algorithm . Ignores pipeline RAW hazards (net trains around them) . Predicted 200MCUPS in 16mm2 of 2µm CMOS running at 20MHz 18 The first few chips… . Used Magic, Irsim, plus other open-source tools . MOSIS had a “TinyChip” program – $500 to fab a 2.2mmx2.2mm chip in 2µm CMOS Sigmoid Multiplier unit JTAG (Brian) (Pawan latches Sinha) (Krste) Regfile 24b (Bertrand) Adder 8-bit datapath (Krste) (Brian) 19 Meanwhile, back at the speech ranch… There’s this even cooler And it doesn’t look ANN architecture for much like the last one. which we need custom Can you build a silicon! different chip? Time for a programmable architecture… 20 Torrent-0 (T0): A Vector Microprocessor . Vector supercomputers (like Crays) are very successful in scientific computing and have a clean programming model T0 idea: Add a vector coprocessor to a standard RISC scalar processor, all on one chip – Primary motivation was software support effort 21 System Design Choices . Which standard RISC? – Considered SPARC, HP PA, PowerPC, and Alpha – Chose MIPS because: simplest, good software tools, Unix desktop workstations for development, and a 64-bit extension path . Buy or build a MIPS core? – Commercial MIPS R3000 chips had coprocessor interface – No MIPS soft cores (no Verilog or synthesis tools yet) – MIPS asked for $2M for architectural licence (1992 dollars!) – Decided to roll our own MIPS-compatible core • vector coprocessor would have played havoc with caches • coprocessor interface too inefficient • commercial chip plus glue logic would blow our size and power budgets (to fit inside workstation) • couldn’t simulate whole system in our environment 22 T0 Block Diagram Address 1 KB . 32-bit datapaths Bus I-Cache VP0 Conditional Move . 16b*16b multiplies Scalar Clip Bus Shift Right . up to 96x32b ops/cycle Add . 40MHz, 1.0µm CMOS Multiply MIPS-II . 16.7 x 16.7 mm2 CPU Shift Left 28 Logic VMP 32 128 Vector Memory Vector Registers Pipeline Scan Logic TSIP Chains Shift Left Add 8 Data 8 Shift Right Bus Clip VP1 Conditional Move 23 T0-based SPERT-II Accelerator Board (1995) (40 MHz) (100 MHz) (60 MHz) . 35 boards shipped to 9 international sites . Used as production research platform for nine years – last time powered up for work in 2004! 24 Microprocessor ISAs in 1990s . From mid-1980s, Cambrian explosion of RISC ISAs – SPARC, MIPS, ARM, Precision, Clipper, AMD 29000, Intel i860, IBM POWER, DEC Alpha, … – ”Brainiac” versus “Speed Demon” design style wars – ACE/ARC initiative, Windows NT on RISC desktops . Extinction event: Intel Pentium P6 – Run clunky CISC ISA fast by breaking into micro-ops and using dynamic scheduling of microops – Use advanced manufacturing made possible by revenue from PC – Both a Brainiac and a Speed Demon, but compatible with whole x86 software ecosystem – RISC ISAs disappeared from workstations, and ultimately from servers – Down in the undergrowth, though, small creatures survived… 25 Mobile Computing Takes Off . For Newton project, Apple selects Acorn RISC Machine, and creates new company ”Advanced RISC Machines” in 1990 . In 90s, ARM develops new business model licensing soft cores, not selling chips . ARM becomes dominant in mobile & embedded computing 26 Closing up of hardware design . Late 90s transition from 0.25µm to 0.18µm is when open-source CAD tools stopped being competitive – Scalable CMOS design rules left too much on table – Foundry rules were under NDA – Magic had tough time scaling to 6 metal layers – Complex physical effects needed better tools (logic synthesis from Verilog, 3D extraction, power analysis, …) 27 Millennial Dark Ages Descend Only two dominant application ISAs (x86, ARM) Only big companies design silicon, rampant consolidation in semiconductor industry Little open-source hardware or tools activity Why Instruction Set Architecture matters . Why can’t Intel sell mobile chips? - 99%+ of mobile phones/tablets based on ARM v7/v8 ISA . Why can’t ARM partners sell servers? - 99%+ of laptops/desktops/servers based on AMD64 ISA (over 95%+ built by Intel) . How can IBM still sell mainframes? - IBM 360, oldest surviving ISA (50+ years) ISA is most important interface in computer system where software meets hardware Open Interfaces Work for Software! Field Open Standard Free, Open Implement. Proprietary Implement. Networking Ethernet, TCP/IP Many Many OS Posix Linux, FreeBSD M/S Windows Compilers C gcc, LLVM Intel icc, ARMcc Databases SQL MySQL, PostgresSQL Oracle 12C, M/S DB2 Graphics OpenGL Mesa3D M/S DirectX ISA ?????? ----------- x86, ARM, IBM360 . Why not successful free & open standards and free & open implementations, like other fields? 30 Companies and their ISAs Come and Go Proprietary ISA fortunes tied to business fortunes and whims . Digital Equipment Corporation - PDP-11, VAX, Alpha . Intel - i960, i860, Itanium . MIPS - Sold to Imagination, then bought by Wave AI startup, now opening R6? . SPARC - Was opened by Sun, acquired by Oracle, now closed down . ARM - Sold to Softbank at >40% premium - Now 25% sold off to Abu Dhabi investment fund 31 Today, many ISAs on one SoC ▪ Applications processor (usually ARM) ▪ Graphics processors ▪ Image processors ▪ Radio DSPs ▪ Audio DSPs ▪ Security processors ▪ Power-management processor ▪ > dozen ISAs on some SoCs – each with unique software stack Why? ▪ Apps processor ISA too big, inflexible for accelerators NVIDIA Tegra SoC ▪ IP bought from different places, each proprietary ISA ▪ Engineers build home-grown ISA cores 32 Do we need all these different ISAs? Must they be proprietary? Must they keep disappearing? What if there was one stable free and open ISA everyone could use for everything? 33 RISC-V Background . In 2010, after many years and many research projects using MIPS, SPARC, and x86, time for architecture group at UC Berkeley to choose ISA for next set of projects .
Recommended publications
  • Configurable RISC-V Softcore Processor for FPGA Implementation

    Configurable RISC-V Softcore Processor for FPGA Implementation

    1 Configurable RISC-V softcore processor for FPGA implementation Joao˜ Filipe Monteiro Rodrigues, Instituto Superior Tecnico,´ Universidade de Lisboa Abstract—Over the past years, the processor market has and development of several programming tools. The RISC-V been dominated by proprietary architectures that implement Foundation controls the RISC-V evolution, and its members instruction sets that require licensing and the payment of fees to are responsible for promoting the adoption of RISC-V and receive permission so they can be used. ARM is an example of one of those companies that sell its microarchitectures to participating in the development of the new ISA. In the list of the manufactures so they can implement them into their own members are big companies like Google, NVIDIA, Western products, and it does not allow the use of its instruction set Digital, Samsung, or Qualcomm. (ISA) in other implementations without licensing. The RISC-V The main goal of this work is the development of a RISC- instruction set appeared proposing the hardware and software V softcore processor to be implemented in an FPGA, using development without costs, through the creation of an open- source ISA. This way, it is possible that any project that im- a non-RISC-V core as the base of this architecture. The plements the RISC-V ISA can be made available open-source or proposed solution is focused on solving the problems and even implemented in commercial products. However, the RISC- limitations identified in the other RISC-V cores that were V solutions that have been developed do not present the needed analyzed in this thesis, especially in terms of the adaptability requirements so they can be included in projects, especially the and flexibility, allowing future modifications according to the research projects, because they offer poor documentation, and their performances are not suitable.
  • VOLUME V INFORMATIQUE NON AMERICAINE Première Partie Par L' Ingénieur Général De L'armement BOUCHER Henri TABLE

    VOLUME V INFORMATIQUE NON AMERICAINE Première Partie Par L' Ingénieur Général De L'armement BOUCHER Henri TABLE

    VOLUME V INFORMATIQUE NON AMERICAINE Première partie par l' Ingénieur Général de l'Armement BOUCHER Henri TABLE DES MATIERES INFORMATIQUE NON AMERICAINE Première partie 731 Informatique européenne (statistiques, exemples) 122 700 Histoire de l'Informatique allemande 1 701 Petits constructeurs 5 702 Les facturières de Kienzle Data System 16 703 Les minis de gestion de Nixdorf 18 704 Siemens & Halske AG 23 705 Systèmes informatiques d'origine allemande 38 706 Histoire de l'informatique britannique 40 707 Industriels anglais de l'informatique 42 708 Travaux des Laboratoires d' Etat 60 709 Travaux universitaires 63 710 Les coeurs synthétisables d' ARM 68 711 Computer Technology 70 712 Elliott Brothers et Elliott Automation 71 713 Les machines d' English Electric Company 74 714 Les calculateurs de Ferranti 76 715 Les études de General Electric Company 83 716 La patiente construction de ICL 85 Catalogue informatique – Volume E - Ingénieur Général de l'Armement Henri Boucher Page : 1/333 717 La série 29 d' ICL 89 718 Autres produits d' ICL, et fin 94 719 Marconi Company 101 720 Plessey 103 721 Systèmes en Grande-Bretagne 105 722 Histoire de l'informatique australienne 107 723 Informatique en Autriche 109 724 Informatique belge 110 725 Informatique canadienne 111 726 Informatique chinoise 116 727 Informatique en Corée du Sud 118 728 Informatique à Cuba 119 729 Informatique danoise 119 730 Informatique espagnole 121 732 Informatique finlandaise 128 733 Histoire de l'informatique française 130 734 La période héroïque : la SEA 140 735 La Compagnie
  • SIMD Extensions

    SIMD Extensions

    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
  • ​5G: Perspectives from a Chipmaker 5G Electronic Workshop, LETI Innovation Days – June 2019

    ​5G: Perspectives from a Chipmaker 5G Electronic Workshop, LETI Innovation Days – June 2019

    ​5G: Perspectives from a Chipmaker 5G electronic workshop, LETI Innovation Days – June 2019 Guillaume Vivier Sequans communications 1 ©2019 Sequans Communications |5G: Perspective from a chip maker – June 2019 MKT-FM-002-R15 Outline • Context, background, market • 5G chipmaker: process technology thoughts and challenges • Conclusion 2 ©2019 Sequans Communications |5G: Perspective from a chip maker – June 2019 5G overall landscape • 3GPP standardization started in Sep 2015 – 5G is wider than RAN (includes new core) – Rel. 15 completed in Dec 2018. ASN1 freeze for 4G-5G migration options in June 19 – Rel. 16 on-going, to be completed in Dec 2019 (June 2020) • Trials and more into 201 operators, 80+ countries (source GSA) • Commercial deployments announced in – Korea, USA, China, Australia, UAE 3 ©2019 Sequans Communications |5G: Perspective from a chip maker – June 2019 Ericsson Mobility Report Nov 2018 • “In 2024, we project that 5G will reach 40 percent population coverage and 1.5 billion subscriptions“ • Interestingly, the report highlights the fact that IoT will continue to grow, beyond LWPA, leveraging higher capability of LTE and 5G 4 ©2019 Sequans Communications |5G: Perspective from a chip maker – June 2019 5G overall landscape • eMBB: smartphone and FWA market – Main focus so far from the ecosystem • URLLC: the next wave – Verticals: Industry 4.0, gaming, media Private LTE/5G deployment, … – V2X and connected car • mMTC: – LPWA type of communication is served by cat-M and NB-IoT – 5G opens the door to new IoT cases not served by LPWA, • Example surveillance camera with image processing on the device • Flexibility is key – From Network side, NVF, SDN, Slicing, etc.
  • Computer Architecture Research with RISC-‐V

    Computer Architecture Research with RISC-‐V

    Computer Architecture Research with RISC-V Krste Asanovic UC Berkeley, RISC-V Foundaon, & SiFive Inc. [email protected] www.riscv.org CARRV, Boston, MA October 14, 2017 Only Two Big Mistakes Possible when Picking Research ISA § Design your own § Use someone else’s Promise of using commercially popular ISAs for research § Ported applicaons/workloads to study § Standard soRware stacks (compilers, OS) § Real commercial hardware to experiment with § Real commercial hardware to validate models with § ExisAng implementaons to study / modify § Industry is more interested in your results 3 Types of projects and standard ISAs used by me or my group in last 30 years § Experiments on real hardware plaorms: - Transputer arrays, SPARC workstaons, MIPS workstaons, POWER workstaons, ARMv7 handhelds, x86 desktops/ servers § Research chips built around modified MIPS ISA: - T0, IRAM, STC1, Scale, Maven § FPGA prototypes/simulaons using various ISAs: - RAMP Blue (modified Microblaze), RAMP Gold/ DIABLO (SPARC v8) § Experiments using soRware architectural simulators: - SimpleScalar (PISA), SMTsim (Alpha), Simics (SPARC,x86), Bochs (x86), MARSS (x86), Gem5(SPARC), PIN (Itanium, x86), … § And of course, other groups used some others too. RealiMes of using standard ISAs § Everything only works if you don’t change anything - Stock binary applicaons - Stock libraries - Stock compiler - Stock OS - Stock hardware implementaon § Add a new instrucAon, get a new non-standard ISA! - Need source code for the apps and recompile - Impossible for most real interesAng applicaons
  • Computer Hardware

    Computer Hardware

    Computer Hardware MJ Rutter mjr19@cam Michaelmas 2014 Typeset by FoilTEX c 2014 MJ Rutter Contents History 4 The CPU 10 instructions ....................................... ............................................. 17 pipelines .......................................... ........................................... 18 vectorcomputers.................................... .............................................. 36 performancemeasures . ............................................... 38 Memory 42 DRAM .................................................. .................................... 43 caches............................................. .......................................... 54 Memory Access Patterns in Practice 82 matrixmultiplication. ................................................. 82 matrixtransposition . ................................................107 Memory Management 118 virtualaddressing .................................. ...............................................119 pagingtodisk ....................................... ............................................128 memorysegments ..................................... ............................................137 Compilers & Optimisation 158 optimisation....................................... .............................................159 thepitfallsofF90 ................................... ..............................................183 I/O, Libraries, Disks & Fileservers 196 librariesandkernels . ................................................197
  • Validated Products List, 1993 No. 2

    Validated Products List, 1993 No. 2

    mmmmm NJST PUBLICATIONS NISTIR 5167 (Supersedes NISTIR 5103) Validated Products List 1993 No. 2 Programming Languages Database Language SQL Graphics GOSIP POSIX Judy B. Kailey Computer Security Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 April 1993 (Supersedes January 1993 issue) —QC 100 NIST . U56 #5167 1993 NISTIR 5167 (Supersedes NISTIR 5103) Validated Products List 1993 No. 2 Programming Languages Database Language SQL Graphics GOSIP POSIX Judy B. Kailey Computer Security Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 April 1993 (Supersedes January 1993 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Raymond Kammer, Acting Director FOREWORD The Validated Products List is a collection of registers describing implementations of Federal Information Processing Standards (FIPS) that have been validated for conformance to FTPS. The Validated Products List also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The Validated Products List is updated quarterly. iii iv TABLE OF CONTENTS 1. INTRODUCTION 1 1.1 Purpose 1 1.2 Document Organization 2 1.2.1 Programming Languages 2 1.2.2 Database
  • EDIT THIS 2021 ISRI 1201 Post-Hearing Letter 050621

    EDIT THIS 2021 ISRI 1201 Post-Hearing Letter 050621

    Juelsgaard Intellectual Property and Innovation Clinic Mills Legal Clinic Stanford Law School Crown Quadrangle May 7, 2021 559 Nathan Abbott Way Stanford, CA 94305-8610 [email protected] Regan Smith 650.724.1900 Mark Gray United States Copyright Office [email protected] [email protected] Re: Docket No. 2020-11 Exemptions to Prohibition Against Circumvention of Technological Measures Protecting Copyrighted Works Dear Ms. Smith and Mr. Gray: I write to respond to your April 27 post-hearing letter requesting the materials that I referenced during the April 21 hearing related to Proposed Class 10 (Computer Programs – Unlocking) that were not included in our written comments. In particular, I cited to three reports from the Global mobile Suppliers Association (“GSA”) to illustrate the rapid increase in cellular-enabled devices with 5G capabilities in the last three years. In March 2019, GSA had identified 33 announced 5G devices from 23 vendors in 7 different form factors.1 By March 2020, GSA had identified 253 announced 5G devices from 81 vendors in 16 different form factors, including the first 5G-enabled laptops, TVs, and tablets.2 And by April 2021, GSA had identified 703 announced 5G devices from 122 vendors in 22 different form factors.3 It should be noted that some of the 22 form factors, such as 5G modules,4 can be deployed across a wide range of use cases that are not directly tracked by the GSA reports.5 For example, one distributor of Quectel’s 5G modules described the target applications as including: Telematics & transport – vehicle tracking, asset tracking, fleet management Energy – electricity meters, gas/water meter, smart grid Payment – wireless pos [point of service], cash register, ATM, vending machine Security – surveillance, detectors Smart city – street lighting, smart parking, sharing economy Gateway – consumer/industrial router 1 GSA, 5G Device Ecosystem (Mar.
  • 5G, Lte & Iot Components Vendors Profiled (28)

    5G, Lte & Iot Components Vendors Profiled (28)

    5G, LTE & IOT COMPONENTS VENDORS PROFILED (28) Altair Semiconductor Ltd., a subsidiary of Sony Corp. / www.altair-semi.com Analog Devices Inc. (NYSE: ADI) / www.analog.com ARM Ltd., a subsidiary of SoftBank Group Corp. / www.arm.com Blu Wireless Technology Ltd. / www.bluwirelesstechnology.com Broadcom Corp. (Nasdaq: BRCM) / www.broadcom.com Cadence Design Systems Inc. / www.cadence.com Ceva Inc. (Nasdaq: CEVA) / www.ceva-dsp.com eASIC Corp. / www.easic.com GCT Semiconductor Inc. / www.gctsemi.com HiSilicon Technologies Co. Ltd. / www.hisilicon.com Integrated Device Technology Inc. (Nasdaq: IDTI) / www.idt.com Intel Corp. (Nasdaq: INTC) / www.intel.com Lime Microsystems Ltd. / www.limemicro.com Marvell Technology Group Ltd. (Nasdaq: MRVL) / www.marvell.com MediaTek Inc. / www.mediatek.com Microsemi Corp., a subsidiary of Microchip Technology Inc. (Nasdaq: MCHP) / www.microsemi.com MIPS, an IP licensing business unit of Wave Computing Inc. / www.mips.com Nordic Semiconductor ASA (OSX: NOD) / www.nordicsemi.com NXP Semiconductors N.V. (Nasdaq: NXPI) / www.nxp.com Octasic Inc. / www.octasic.com Peraso Technologies Inc. / www.perasotech.com Qualcomm Inc. (Nasdaq: QCOM) / www.qualcomm.com Samsung Electronics Co. Ltd. (005930:KS) / www.samsung.com Sanechips Technology Co. Ltd., a subsidiary of ZTE Corp. (SHE: 000063) / www.sanechips.com.cn Sequans Communications S.A. (NYSE: SQNS) / www.sequans.com Texas Instruments Inc. (NYSE: TXN) / www.ti.com Unisoc Communications Inc., a subsidiary of Tsinghua Unigroup Ltd. / www.unisoc.com Xilinx Inc. (Nasdaq: XLNX) / www.xilinx.com © HEAVY READING | AUGUST 2018 | 5G/LTE BASE STATION, RRH, CPE & IOT COMPONENTS .
  • RISC-V Geneology

    RISC-V Geneology

    RISC-V Geneology Tony Chen David A. Patterson Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2016-6 http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-6.html January 24, 2016 Copyright © 2016, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Introduction RISC-V is an open instruction set designed along RISC principles developed originally at UC Berkeley1 and is now set to become an open industry standard under the governance of the RISC-V Foundation (www.riscv.org). Since the instruction set architecture (ISA) is unrestricted, organizations can share implementations as well as open source compilers and operating systems. Designed for use in custom systems on a chip, RISC-V consists of a base set of instructions called RV32I along with optional extensions for multiply and divide (RV32M), atomic operations (RV32A), single-precision floating point (RV32F), and double-precision floating point (RV32D). The base and these four extensions are collectively called RV32G. This report discusses the historical precedents of RV32G. We look at 18 prior instruction set architectures, chosen primarily from earlier UC Berkeley RISC architectures and major proprietary RISC instruction sets. Among the 122 instructions in RV32G: ● 6 instructions do not have precedents among the selected instruction sets, ● 98 instructions of the 116 with precedents appear in at least three different instruction sets.
  • 956830 Deliverable D2.1 Initial Vision and Requirement Report

    956830 Deliverable D2.1 Initial Vision and Requirement Report

    European Core Technologies for future connectivity systems and components Call/Topic: H2020 ICT-42-2020 Grant Agreement Number: 956830 Deliverable D2.1 Initial vision and requirement report Deliverable type: Report WP number and title: WP2 (Strategy, vision, and requirements) Dissemination level: Public Due date: 31.12.2020 Lead beneficiary: EAB Lead author(s): Fredrik Tillman (EAB), Björn Ekelund (EAB) Contributing partners: Yaning Zou (TUD), Uta Schneider (TUD), Alexandros Kaloxylos (5G IA), Patrick Cogez (AENEAS), Mohand Achouche (IIIV/Nokia), Werner Mohr (IIIV/Nokia), Frank Hofmann (BOSCH), Didier Belot (CEA), Jochen Koszescha (IFAG), Jacques Magen (AUS), Piet Wambacq (IMEC), Björn Debaillie (IMEC), Patrick Pype (NXP), Frederic Gianesello (ST), Raphael Bingert (ST) Reviewers: Mohand Achouche (IIIV/Nokia), Jacques Magen (AUS), Yaning Zou (TUD), Alexandros Kaloxylos (5G IA), Frank Hofmann (BOSCH), Piet Wambacq (IMEC), Patrick Cogez (AENEAS) D 2.1 – Initial vision and requirement report Document History Version Date Author/Editor Description 0.1 05.11.2020 Fredrik Tillman (EAB) Outline and contributors 0.2 19.11.2020 All contributors First complete draft 0.3 18.12.2020 All contributors Second complete draft 0.4 21.12.2020 Björn Ekelund Third complete draft 1.0 21.12.2020 Fredrik Tillman (EAB) Final version List of Abbreviations Abbreviation Denotation 5G 5th Generation of wireless communication 5G PPP The 5G infrastructure Public Private Partnership 6G 6th Generation of wireless communication AI Artificial Intelligence ASIC Application
  • Processor Design：System-On-Chip Computing For

    Processor Design：System-On-Chip Computing For

    Processor Design Processor Design System-on-Chip Computing for ASICs and FPGAs Edited by Jari Nurmi Tampere University of Technology Finland A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN 978-1-4020-5529-4 (HB) ISBN 978-1-4020-5530-0 (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com Printed on acid-free paper All Rights Reserved © 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. To Pirjo, Lauri, Eero, and Santeri Preface When I started my computing career by programming a PDP-11 computer as a freshman in the university in early 1980s, I could not have dreamed that one day I’d be able to design a processor. At that time, the freshmen were only allowed to use PDP. Next year I was given the permission to use the famous brand-new VAX-780 computer. Also, my new roommate at the dorm had got one of the first personal computers, a Commodore-64 which we started to explore together. Again, I could not have imagined that hundreds of times the processing power will be available in an everyday embedded device just a quarter of century later.